From nobody Tue Feb 10 09:58:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645780321305388.6184423586201; Fri, 25 Feb 2022 01:12:01 -0800 (PST) Received: from localhost ([::1]:48544 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nNWds-0005Bu-8r for importer@patchew.org; Fri, 25 Feb 2022 04:12:00 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47382) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNVaD-0008BK-G3 for qemu-devel@nongnu.org; Fri, 25 Feb 2022 03:04:12 -0500 Received: from mail.loongson.cn ([114.242.206.163]:42142 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nNVZt-0002T2-6C for qemu-devel@nongnu.org; Fri, 25 Feb 2022 03:04:09 -0500 Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxqMg8jRhiw9UGAA--.8228S30; Fri, 25 Feb 2022 16:03:25 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Subject: [RFC PATCH v6 28/29] hw/loongarch: Add fdt support. Date: Fri, 25 Feb 2022 03:03:07 -0500 Message-Id: <20220225080308.1405-29-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220225080308.1405-1-yangxiaojuan@loongson.cn> References: <20220225080308.1405-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf9DxqMg8jRhiw9UGAA--.8228S30 X-Coremail-Antispam: 1UD129KBjvJXoW3Ar1kZw4xGryxJw1xtFy5Arb_yoW3uF4xpF W7AFWDWrW8Xrs3urs2g345uwn3Jr18GFW7Xa12grWFkayDWw18Zay8Aa9ayF15J34FqFyY vFZ5JrySg3WIgr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, richard.henderson@linaro.org, Song Gao Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645780322473100001 Content-Type: text/plain; charset="utf-8" Add tree nodes for 3A5000 device tree. - cpu nodes; - fw_cfg nodes; - pcie nodes. The lastest loongarch bios have supported fdt. - https://github.com/loongson/edk2 - https://github.com/loongson/edk2-platforms Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/loongarch/loongson3.c | 136 +++++++++++++++++++++++++++++++ include/hw/loongarch/loongarch.h | 5 ++ target/loongarch/cpu.c | 2 + target/loongarch/cpu.h | 3 + 4 files changed, 146 insertions(+) diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c index 5f0dcfa419..0ae6075a3e 100644 --- a/hw/loongarch/loongson3.c +++ b/hw/loongarch/loongson3.c @@ -34,6 +34,9 @@ #include "hw/firmware/smbios.h" #include "hw/acpi/aml-build.h" #include "qapi/qapi-visit-common.h" +#include "sysemu/device_tree.h" + +#include =20 #include "target/loongarch/cpu.h" =20 @@ -447,6 +450,126 @@ static void loongarch_irq_init(LoongArchMachineState = *lams, loongarch_devices_init(pch_pic); } =20 +static void create_fdt(LoongArchMachineState *lams) +{ + MachineState *ms =3D MACHINE(lams); + + ms->fdt =3D create_device_tree(&lams->fdt_size); + if (!ms->fdt) { + error_report("create_device_tree() failed"); + exit(1); + } + + /* Header */ + qemu_fdt_setprop_string(ms->fdt, "/", "compatible", + "linux,dummy-loongson3"); + qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); + qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); +} + +static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) +{ + int num; + const MachineState *ms =3D MACHINE(lams); + int smp_cpus =3D ms->smp.cpus; + + qemu_fdt_add_subnode(ms->fdt, "/cpus"); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); + + /* cpu nodes */ + for (num =3D smp_cpus - 1; num >=3D 0; num--) { + char *nodename =3D g_strdup_printf("/cpus/cpu@%d", num); + LoongArchCPU *cpu =3D LOONGARCH_CPU(qemu_get_cpu(num)); + + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); + qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", + cpu->dtb_compatible); + qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); + qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", + qemu_fdt_alloc_phandle(ms->fdt)); + g_free(nodename); + } + + /*cpu map */ + qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); + + for (num =3D smp_cpus - 1; num >=3D 0; num--) { + char *cpu_path =3D g_strdup_printf("/cpus/cpu@%d", num); + char *map_path; + + if (ms->smp.threads > 1) { + map_path =3D g_strdup_printf( + "/cpus/cpu-map/socket%d/core%d/thread%d", + num / (ms->smp.cores * ms->smp.threads), + (num / ms->smp.threads) % ms->smp.cores, + num % ms->smp.threads); + } else { + map_path =3D g_strdup_printf( + "/cpus/cpu-map/socket%d/core%d", + num / ms->smp.cores, + num % ms->smp.cores); + } + qemu_fdt_add_path(ms->fdt, map_path); + qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); + + g_free(map_path); + g_free(cpu_path); + } +} + +static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) +{ + char *nodename; + hwaddr base =3D FW_CFG_ADDR; + const MachineState *ms =3D MACHINE(lams); + + nodename =3D g_strdup_printf("/fw_cfg@%" PRIx64, base); + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, + "compatible", "qemu,fw-cfg-mmio"); + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", + 2, base, 2, 0x8); + qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); + g_free(nodename); +} + +static void fdt_add_pcie_node(const LoongArchMachineState *lams) +{ + char *nodename; + hwaddr base_mmio =3D LS7A_PCI_MEM_BASE; + hwaddr size_mmio =3D LS7A_PCI_MEM_SIZE; + hwaddr base_pio =3D LS7A_PCI_IO_BASE; + hwaddr size_pio =3D LS7A_PCI_IO_SIZE; + hwaddr base_pcie =3D LS_PCIECFG_BASE; + hwaddr size_pcie =3D LS_PCIECFG_SIZE; + hwaddr base =3D base_pcie; + + const MachineState *ms =3D MACHINE(lams); + + nodename =3D g_strdup_printf("/pcie@%" PRIx64, base); + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, + "compatible", "pci-host-ecam-generic"); + qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); + qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); + qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); + qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); + qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, + PCIE_MMCFG_BUS(LS_PCIECFG_SIZE - 1)); + qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", + 2, base_pcie, 2, size_pcie); + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", + 1, FDT_PCI_RANGE_IOPORT, 2, LS7A_PCI_IO_O= FFSET, + 2, base_pio, 2, size_pio, + 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, + 2, base_mmio, 2, size_mmio); + g_free(nodename); + qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size); +} + static void loongarch_init(MachineState *machine) { const char *cpu_model =3D machine->cpu_type; @@ -474,12 +597,16 @@ static void loongarch_init(MachineState *machine) exit(1); } =20 + create_fdt(lams); + /* Init CPUs */ for (i =3D 0; i < machine->smp.cpus; i++) { la_cpu =3D LOONGARCH_CPU(cpu_create(machine->cpu_type)); loongarch_cpu_init(la_cpu, i); } =20 + fdt_add_cpu_nodes(lams); + if (ram_size < 1 * GiB) { error_report("ram_size must be greater than 1G."); exit(1); @@ -519,6 +646,8 @@ static void loongarch_init(MachineState *machine) exit(1); } =20 + fdt_add_fw_cfg_node(lams); + if (kernel_filename) { loaderparams.ram_size =3D ram_size; loaderparams.kernel_filename =3D kernel_filename; @@ -543,6 +672,13 @@ static void loongarch_init(MachineState *machine) lams->machine_done.notify =3D loongarch_machine_done; qemu_add_machine_init_done_notifier(&lams->machine_done); =20 + fdt_add_pcie_node(lams); + + /* load fdt */ + MemoryRegion *fdt_rom =3D g_new(MemoryRegion, 1); + memory_region_init_rom(fdt_rom, NULL, "fdt", LA_FDT_SIZE, &error_fatal= ); + memory_region_add_subregion(get_system_memory(), LA_FDT_BASE, fdt_rom); + rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, LA_FDT_BASE); } =20 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) diff --git a/include/hw/loongarch/loongarch.h b/include/hw/loongarch/loonga= rch.h index 4df62b958d..1ae7824e2d 100644 --- a/include/hw/loongarch/loongarch.h +++ b/include/hw/loongarch/loongarch.h @@ -41,6 +41,9 @@ #define LA_BIOS_BASE 0x1c000000 #define LA_BIOS_SIZE (4 * 1024 * 1024) =20 +#define LA_FDT_BASE 0x1c400000 +#define LA_FDT_SIZE 0x100000 + /* Kernels can be configured with 64KB pages */ #define INITRD_PAGE_SIZE (64 * KiB) #define INITRD_BASE 0x04000000 @@ -61,6 +64,8 @@ typedef struct LoongArchMachineState { OnOffAuto acpi; char *oem_id; char *oem_table_id; + + int fdt_size; } LoongArchMachineState; =20 #define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("virt") diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index e31fbe935d..def084400a 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -335,6 +335,8 @@ static void loongarch_3a5000_initfn(Object *obj) env->cpucfg[i] =3D 0x0; } =20 + cpu->dtb_compatible =3D "loongarch,Loongson-3A5000"; + env->cpucfg[0] =3D 0x14c010; /* PRID */ =20 uint32_t data =3D 0; diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 883c7c05b2..424e9d64f0 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -361,6 +361,9 @@ struct LoongArchCPU { CPUNegativeOffsetState neg; CPULoongArchState env; QEMUTimer timer; + + /* 'compatible' string for this CPU for Linux device trees */ + const char *dtb_compatible; }; =20 #define TYPE_LOONGARCH_CPU "loongarch-cpu" --=20 2.27.0