From nobody Tue Sep 9 19:54:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645728314810250.73689568091004; Thu, 24 Feb 2022 10:45:14 -0800 (PST) Received: from localhost ([::1]:53378 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nNJ73-0003Gd-9H for importer@patchew.org; Thu, 24 Feb 2022 13:45:13 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52170) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNIzb-0008Sy-JB for qemu-devel@nongnu.org; Thu, 24 Feb 2022 13:37:31 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]:32816) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNIzY-0003EV-Pf for qemu-devel@nongnu.org; Thu, 24 Feb 2022 13:37:30 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-49-OEf90d9tNs6m9cB5uV4QEQ-1; Thu, 24 Feb 2022 13:37:26 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 895F18145EE; Thu, 24 Feb 2022 18:37:25 +0000 (UTC) Received: from localhost (unknown [10.39.208.2]) by smtp.corp.redhat.com (Postfix) with ESMTP id D76B58A16F; Thu, 24 Feb 2022 18:37:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1645727848; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7tiyf/OjL84Wd+PbyeHQpL07Nc86o5fw8ARcNy1mimM=; b=DIbfFI5ayT3Kw8EV3E3rVhYvcKVNEDjYmIDGiQF/xCbX2PI2yICbGOZQr/q+R/yex5Q6Tk 5JRLE7YlJljppjXBo3/Fs583pi2/9WgitPSeYjG4tZDGTQjxTIhIE/i8WmnIQ1jxYB3W6L yg2OrqVkxvuTGpFBogeFmCODkS+WYt8= X-MC-Unique: OEf90d9tNs6m9cB5uV4QEQ-1 From: marcandre.lureau@redhat.com To: qemu-devel@nongnu.org Subject: [PATCH 01/12] compiler.h: replace QEMU_WARN_UNUSED_RESULT with G_GNUC_WARN_UNUSED_RESULT Date: Thu, 24 Feb 2022 22:36:50 +0400 Message-Id: <20220224183701.608720-2-marcandre.lureau@redhat.com> In-Reply-To: <20220224183701.608720-1-marcandre.lureau@redhat.com> References: <20220224183701.608720-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=marcandre.lureau@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, f4bug@amsat.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645728316180100001 From: Marc-Andr=C3=A9 Lureau One less qemu-specific macro. It also helps to make some headers/units only depend on glib, and thus moved in standalone projects eventually. Signed-off-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Richard Henderson --- include/qemu-common.h | 2 +- include/qemu/compiler.h | 2 -- include/qemu/range.h | 4 ++-- scripts/cocci-macro-file.h | 2 +- block/qcow2-refcount.c | 20 +++++++++++--------- scripts/checkpatch.pl | 2 +- 6 files changed, 16 insertions(+), 16 deletions(-) diff --git a/include/qemu-common.h b/include/qemu-common.h index 6969f957b7c3..79977cb3ec43 100644 --- a/include/qemu-common.h +++ b/include/qemu-common.h @@ -29,7 +29,7 @@ int qemu_main(int argc, char **argv, char **envp); void *qemu_oom_check(void *ptr); =20 ssize_t qemu_write_full(int fd, const void *buf, size_t count) - QEMU_WARN_UNUSED_RESULT; + G_GNUC_WARN_UNUSED_RESULT; =20 #ifndef _WIN32 int qemu_pipe(int pipefd[2]); diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index f2bd050e3b9a..8385e477c18e 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -19,8 +19,6 @@ =20 #define QEMU_NORETURN __attribute__ ((__noreturn__)) =20 -#define QEMU_WARN_UNUSED_RESULT __attribute__((warn_unused_result)) - #define QEMU_SENTINEL __attribute__((sentinel)) =20 #if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__)) diff --git a/include/qemu/range.h b/include/qemu/range.h index f62b363e0d12..7e2b1cc447af 100644 --- a/include/qemu/range.h +++ b/include/qemu/range.h @@ -114,8 +114,8 @@ static inline uint64_t range_upb(Range *range) * @size may be 0. If the range would overflow, returns -ERANGE, otherwise * 0. */ -static inline int QEMU_WARN_UNUSED_RESULT range_init(Range *range, uint64_= t lob, - uint64_t size) +G_GNUC_WARN_UNUSED_RESULT +static inline int range_init(Range *range, uint64_t lob, uint64_t size) { if (lob + size < lob) { return -ERANGE; diff --git a/scripts/cocci-macro-file.h b/scripts/cocci-macro-file.h index c2fcea8e77a2..9daec24d7825 100644 --- a/scripts/cocci-macro-file.h +++ b/scripts/cocci-macro-file.h @@ -20,7 +20,7 @@ =20 /* From qemu/compiler.h */ #define QEMU_NORETURN __attribute__ ((__noreturn__)) -#define QEMU_WARN_UNUSED_RESULT __attribute__((warn_unused_result)) +#define G_GNUC_WARN_UNUSED_RESULT __attribute__((warn_unused_result)) #define QEMU_SENTINEL __attribute__((sentinel)) =20 #if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__)) diff --git a/block/qcow2-refcount.c b/block/qcow2-refcount.c index 461457225274..4c7bf5c2b5db 100644 --- a/block/qcow2-refcount.c +++ b/block/qcow2-refcount.c @@ -32,9 +32,11 @@ =20 static int64_t alloc_clusters_noref(BlockDriverState *bs, uint64_t size, uint64_t max); -static int QEMU_WARN_UNUSED_RESULT update_refcount(BlockDriverState *bs, - int64_t offset, int64_t length, uint64_t adden= d, - bool decrease, enum qcow2_discard_type type); + +G_GNUC_WARN_UNUSED_RESULT +static int update_refcount(BlockDriverState *bs, + int64_t offset, int64_t length, uint64_t addend, + bool decrease, enum qcow2_discard_type type); =20 static uint64_t get_refcount_ro0(const void *refcount_array, uint64_t inde= x); static uint64_t get_refcount_ro1(const void *refcount_array, uint64_t inde= x); @@ -802,12 +804,12 @@ found: /* XXX: cache several refcount block clusters ? */ /* @addend is the absolute value of the addend; if @decrease is set, @adde= nd * will be subtracted from the current refcount, otherwise it will be adde= d */ -static int QEMU_WARN_UNUSED_RESULT update_refcount(BlockDriverState *bs, - int64_t offset, - int64_t length, - uint64_t addend, - bool decrease, - enum qcow2_discard_type= type) +static int update_refcount(BlockDriverState *bs, + int64_t offset, + int64_t length, + uint64_t addend, + bool decrease, + enum qcow2_discard_type type) { BDRVQcow2State *s =3D bs->opaque; int64_t start, last, cluster_offset; diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index a07f0effb540..797738a8e839 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -224,7 +224,7 @@ our $Attribute =3D qr{ const| volatile| QEMU_NORETURN| - QEMU_WARN_UNUSED_RESULT| + G_GNUC_WARN_UNUSED_RESULT| QEMU_SENTINEL| QEMU_PACKED| G_GNUC_PRINTF --=20 2.35.1.273.ge6ebfd0e8cbb From nobody Tue Sep 9 19:54:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645728859264359.37451854912354; Thu, 24 Feb 2022 10:54:19 -0800 (PST) Received: from localhost ([::1]:60886 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nNJFk-0000GR-Qy for importer@patchew.org; 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Thu, 24 Feb 2022 18:37:35 +0000 (UTC) Received: from localhost (unknown [10.39.208.2]) by smtp.corp.redhat.com (Postfix) with ESMTP id 389757FCE6; Thu, 24 Feb 2022 18:37:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1645727859; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KNWh9Wc1PnX2Ji9Izrzrd5tRkQPYDwIaovB2g6lUWKk=; b=gGYiQRggUOnvYNtA/pZY/+GGAqFaftRc0UkE8A3O6DFuaihKaOwGofL/pUhqun4NhryzKm zfLOCO6CE4ifNhMjSGZ6uzF4emgLX2laOYkmhRbs2sLqaF+ddvBKIIz0I3fw7EJoiwdGmt t0OCR7Z6xoLp16vjDS4M2BJbBWJ6TcY= X-MC-Unique: PBsqVkRqPaeomj73j04KPg-1 From: marcandre.lureau@redhat.com To: qemu-devel@nongnu.org Subject: [PATCH 02/12] compiler.h: replace QEMU_SENTINEL with G_GNUC_NULL_TERMINATED Date: Thu, 24 Feb 2022 22:36:51 +0400 Message-Id: <20220224183701.608720-3-marcandre.lureau@redhat.com> In-Reply-To: <20220224183701.608720-1-marcandre.lureau@redhat.com> References: <20220224183701.608720-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=marcandre.lureau@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, f4bug@amsat.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645728860487100001 From: Marc-Andr=C3=A9 Lureau One less qemu-specific macro. It also helps to make some headers/units only depend on glib, and thus moved in standalone projects eventually. Signed-off-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Richard Henderson --- include/qemu/compiler.h | 2 -- include/qom/object.h | 6 +++--- scripts/cocci-macro-file.h | 2 +- scripts/checkpatch.pl | 2 +- 4 files changed, 5 insertions(+), 7 deletions(-) diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index 8385e477c18e..0a5e67fb970e 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -19,8 +19,6 @@ =20 #define QEMU_NORETURN __attribute__ ((__noreturn__)) =20 -#define QEMU_SENTINEL __attribute__((sentinel)) - #if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__)) # define QEMU_PACKED __attribute__((gcc_struct, packed)) #else diff --git a/include/qom/object.h b/include/qom/object.h index fae096f51cce..5f3d5b5bf532 100644 --- a/include/qom/object.h +++ b/include/qom/object.h @@ -616,7 +616,7 @@ Object *object_new_with_props(const char *typename, Object *parent, const char *id, Error **errp, - ...) QEMU_SENTINEL; + ...) G_GNUC_NULL_TERMINATED; =20 /** * object_new_with_propv: @@ -676,7 +676,7 @@ void object_apply_compat_props(Object *obj); * * Returns: %true on success, %false on error. */ -bool object_set_props(Object *obj, Error **errp, ...) QEMU_SENTINEL; +bool object_set_props(Object *obj, Error **errp, ...) G_GNUC_NULL_TERMINAT= ED; =20 /** * object_set_propv: @@ -728,7 +728,7 @@ void object_initialize(void *obj, size_t size, const ch= ar *typename); bool object_initialize_child_with_props(Object *parentobj, const char *propname, void *childobj, size_t size, const char *type, - Error **errp, ...) QEMU_SENTINEL; + Error **errp, ...) G_GNUC_NULL_TERMINATED; =20 /** * object_initialize_child_with_propsv: diff --git a/scripts/cocci-macro-file.h b/scripts/cocci-macro-file.h index 9daec24d7825..3d1e9b50919a 100644 --- a/scripts/cocci-macro-file.h +++ b/scripts/cocci-macro-file.h @@ -21,7 +21,7 @@ /* From qemu/compiler.h */ #define QEMU_NORETURN __attribute__ ((__noreturn__)) #define G_GNUC_WARN_UNUSED_RESULT __attribute__((warn_unused_result)) -#define QEMU_SENTINEL __attribute__((sentinel)) +#define G_GNUC_NULL_TERMINATED __attribute__((sentinel)) =20 #if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__)) # define QEMU_PACKED __attribute__((gcc_struct, packed)) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 797738a8e839..ddc6003de280 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -225,7 +225,7 @@ our $Attribute =3D qr{ volatile| QEMU_NORETURN| G_GNUC_WARN_UNUSED_RESULT| - QEMU_SENTINEL| + G_GNUC_NULL_TERMINATED| QEMU_PACKED| G_GNUC_PRINTF }x; --=20 2.35.1.273.ge6ebfd0e8cbb From nobody Tue Sep 9 19:54:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=MrKuDEU/6LjpVnJf1BPKI/F7HDjtqs4rOhpxMKDt7fk=; b=f4q1HB4g9bDTSPVTtEpiAmhqoQJl61HL8FljwkDmwJsfRMPm99XzoE7NpddxfoY23oXGFD 6MMFgFEqwl3Zh/ae82DejQBZPVOETI2NGcvu2TXiHZ93o3cKbRLAXRTXf3icPAyWRaYDRh 6+YB3/YEhJHPOyLo3ykVjTQZ8fr/Wm8= X-MC-Unique: gcB0kXxrPpCTWkJhikYWxw-1 From: marcandre.lureau@redhat.com To: qemu-devel@nongnu.org Subject: [PATCH 03/12] osdep.h: move qemu_build_not_reached() Date: Thu, 24 Feb 2022 22:36:52 +0400 Message-Id: <20220224183701.608720-4-marcandre.lureau@redhat.com> In-Reply-To: <20220224183701.608720-1-marcandre.lureau@redhat.com> References: <20220224183701.608720-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=marcandre.lureau@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Signed-off-by: Marc-Andr=C3=A9 Lureau --- include/qemu/compiler.h | 16 ---------------- include/qemu/osdep.h | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index 0a5e67fb970e..a2d2d48dcf34 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -151,22 +151,6 @@ #define QEMU_ALWAYS_INLINE #endif =20 -/** - * qemu_build_not_reached() - * - * The compiler, during optimization, is expected to prove that a call - * to this function cannot be reached and remove it. If the compiler - * supports QEMU_ERROR, this will be reported at compile time; otherwise - * this will be reported at link time due to the missing symbol. - */ -extern void QEMU_NORETURN QEMU_ERROR("code path is reachable") - qemu_build_not_reached_always(void); -#if defined(__OPTIMIZE__) && !defined(__NO_INLINE__) -#define qemu_build_not_reached() qemu_build_not_reached_always() -#else -#define qemu_build_not_reached() g_assert_not_reached() -#endif - /** * In most cases, normal "fallthrough" comments are good enough for * switch-case statements, but sometimes the compiler has problems diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 7bcce3bceb0f..fb72b0006d5c 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -157,6 +157,22 @@ extern "C" { #define assert(x) g_assert(x) #endif =20 +/** + * qemu_build_not_reached() + * + * The compiler, during optimization, is expected to prove that a call + * to this function cannot be reached and remove it. If the compiler + * supports QEMU_ERROR, this will be reported at compile time; otherwise + * this will be reported at link time due to the missing symbol. + */ +extern void QEMU_NORETURN QEMU_ERROR("code path is reachable") + qemu_build_not_reached_always(void); +#if defined(__OPTIMIZE__) && !defined(__NO_INLINE__) +#define qemu_build_not_reached() qemu_build_not_reached_always() +#else +#define qemu_build_not_reached() g_assert_not_reached() +#endif + /* * According to waitpid man page: * WCOREDUMP --=20 2.35.1.273.ge6ebfd0e8cbb From nobody Tue Sep 9 19:54:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645729472508554.3301211288621; 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Thu, 24 Feb 2022 18:38:08 +0000 (UTC) Received: from localhost (unknown [10.39.208.2]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1D8DF7FCE6; Thu, 24 Feb 2022 18:37:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1645727890; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ikLC1zAlL6jwuf89JZyDxTHPAgNLirY21wF4Ta1IOhw=; b=GpufqM9tJCVAa0yCmviblnnlhIJufi23Wz4oH0FjjHAHbKvHl6UC2GtdY+C79/7dL7g7tt pBMFzh0KFoUVHZi6UtahORPoJBK5qdMC/zdC98IoO3DEAhEMtYZnrW/xBxLEqkbuk2XKao yOv4u3FDn/xeESqVUwoRvgGD5QgP8bA= X-MC-Unique: jyq_9Q1qN5ymduQGzIb1Jw-1 From: marcandre.lureau@redhat.com To: qemu-devel@nongnu.org Subject: [PATCH 04/12] compiler.h: replace QEMU_NORETURN with G_NORETURN Date: Thu, 24 Feb 2022 22:36:53 +0400 Message-Id: <20220224183701.608720-5-marcandre.lureau@redhat.com> In-Reply-To: <20220224183701.608720-1-marcandre.lureau@redhat.com> References: <20220224183701.608720-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=marcandre.lureau@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, f4bug@amsat.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645729473927100003 From: Marc-Andr=C3=A9 Lureau G_NORETURN was introduced in glib 2.68, fallback to G_GNUC_NORETURN in glib-compat. Note that this attribute must be placed before the function declaration (bringing a bit of consistency in qemu codebase usage). Signed-off-by: Marc-Andr=C3=A9 Lureau --- accel/tcg/internal.h | 3 +-- include/exec/exec-all.h | 20 +++++++++---------- include/exec/helper-head.h | 2 +- include/glib-compat.h | 4 ++++ include/hw/core/cpu.h | 2 +- include/hw/core/tcg-cpu-ops.h | 6 +++--- include/hw/hw.h | 2 +- include/qemu/compiler.h | 2 -- include/qemu/osdep.h | 2 +- include/qemu/thread.h | 2 +- include/tcg/tcg-ldst.h | 4 ++-- include/tcg/tcg.h | 2 +- linux-user/user-internals.h | 2 +- scripts/cocci-macro-file.h | 2 +- target/alpha/cpu.h | 10 +++++----- target/arm/internals.h | 12 +++++------ target/hppa/cpu.h | 2 +- target/i386/tcg/helper-tcg.h | 24 +++++++++++----------- target/microblaze/cpu.h | 6 +++--- target/mips/tcg/tcg-internal.h | 16 +++++++-------- target/nios2/cpu.h | 6 +++--- target/openrisc/exception.h | 2 +- target/ppc/cpu.h | 14 ++++++------- target/ppc/internal.h | 6 +++--- target/riscv/cpu.h | 10 +++++----- target/s390x/s390x-internal.h | 6 +++--- target/s390x/tcg/tcg_s390x.h | 12 +++++------ target/sh4/cpu.h | 6 +++--- target/sparc/cpu.h | 10 +++++----- target/xtensa/cpu.h | 2 +- accel/stubs/tcg-stub.c | 4 ++-- bsd-user/signal.c | 2 +- hw/misc/mips_itu.c | 2 +- linux-user/signal.c | 2 +- monitor/hmp.c | 2 +- qemu-img.c | 9 +++++---- target/alpha/helper.c | 10 +++++----- target/arm/pauth_helper.c | 4 ++-- target/arm/tlb_helper.c | 6 +++--- target/hexagon/op_helper.c | 8 ++++---- target/hppa/cpu.c | 2 +- target/hppa/op_helper.c | 4 ++-- target/i386/tcg/bpt_helper.c | 2 +- target/i386/tcg/excp_helper.c | 30 ++++++++++++++-------------- target/i386/tcg/misc_helper.c | 6 +++--- target/i386/tcg/sysemu/misc_helper.c | 6 +++--- target/openrisc/exception.c | 2 +- target/openrisc/exception_helper.c | 2 +- target/riscv/op_helper.c | 4 ++-- target/rx/op_helper.c | 20 +++++++++---------- target/s390x/tcg/excp_helper.c | 20 +++++++++---------- target/sh4/op_helper.c | 4 ++-- target/sparc/mmu_helper.c | 8 ++++---- target/tricore/op_helper.c | 2 +- tcg/tcg.c | 2 +- tests/fp/fp-bench.c | 2 +- tests/fp/fp-test.c | 2 +- scripts/checkpatch.pl | 2 +- 58 files changed, 185 insertions(+), 183 deletions(-) diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h index 881bc1ede0b1..3092bfa96430 100644 --- a/accel/tcg/internal.h +++ b/accel/tcg/internal.h @@ -14,8 +14,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc, target_ulong cs_base, uint32_t flags, int cflags); - -void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); +G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); void page_init(void); void tb_htable_init(void); =20 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 35d8e93976f5..d7510411ad7a 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -61,10 +61,10 @@ void restore_state_to_opc(CPUArchState *env, Translatio= nBlock *tb, */ bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exi= t); =20 -void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu); -void QEMU_NORETURN cpu_loop_exit(CPUState *cpu); -void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); -void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); +G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); +G_NORETURN void cpu_loop_exit(CPUState *cpu); +G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); +G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); =20 /** * cpu_loop_exit_requested: @@ -697,9 +697,9 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_= t *old_set, * Use the TCGCPUOps hook to record cpu state, do guest operating system * specific things to raise SIGSEGV, and jump to the main cpu loop. */ -void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, - MMUAccessType access_type, - bool maperr, uintptr_t ra); +G_NORETURN void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, + bool maperr, uintptr_t ra); =20 /** * cpu_loop_exit_sigbus: @@ -711,9 +711,9 @@ void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu,= target_ulong addr, * Use the TCGCPUOps hook to record cpu state, do guest operating system * specific things to raise SIGBUS, and jump to the main cpu loop. */ -void QEMU_NORETURN cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, - MMUAccessType access_type, - uintptr_t ra); +G_NORETURN void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, + MMUAccessType access_type, + uintptr_t ra); =20 #else static inline void mmap_lock(void) {} diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index b974eb394ae0..047df0f2918b 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -46,7 +46,7 @@ #define dh_ctype_ptr void * #define dh_ctype_cptr const void * #define dh_ctype_void void -#define dh_ctype_noreturn void QEMU_NORETURN +#define dh_ctype_noreturn G_NORETURN void #define dh_ctype(t) dh_ctype_##t =20 #ifdef NEED_CPU_H diff --git a/include/glib-compat.h b/include/glib-compat.h index 3113a7d2af84..43a562974d80 100644 --- a/include/glib-compat.h +++ b/include/glib-compat.h @@ -147,4 +147,8 @@ qemu_g_test_slow(void) =20 #pragma GCC diagnostic pop =20 +#ifndef G_NORETURN +#define G_NORETURN G_GNUC_NORETURN +#endif + #endif diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fc1238f57708..f7b6f6e2b021 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1008,7 +1008,7 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vad= dr addr, vaddr len); */ AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); =20 -void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) +G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...) G_GNUC_PRINTF(2, 3); =20 /* $(top_srcdir)/cpu.c */ diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index e13898553aff..fbe6b76764cf 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -78,9 +78,9 @@ struct TCGCPUOps { * @do_unaligned_access: Callback for unaligned access handling * The callback must exit via raising an exception. */ - void (*do_unaligned_access)(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) QEMU_NORET= URN; + G_NORETURN void (*do_unaligned_access)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); =20 /** * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by A= RM diff --git a/include/hw/hw.h b/include/hw/hw.h index 34377f5309d3..045c1c8b09b3 100644 --- a/include/hw/hw.h +++ b/include/hw/hw.h @@ -5,6 +5,6 @@ #error Cannot include hw/hw.h from user emulation #endif =20 -void QEMU_NORETURN hw_error(const char *fmt, ...) G_GNUC_PRINTF(1, 2); +G_NORETURN void hw_error(const char *fmt, ...) G_GNUC_PRINTF(1, 2); =20 #endif diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index a2d2d48dcf34..2704c314dcac 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -17,8 +17,6 @@ #define QEMU_EXTERN_C extern #endif =20 -#define QEMU_NORETURN __attribute__ ((__noreturn__)) - #if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__)) # define QEMU_PACKED __attribute__((gcc_struct, packed)) #else diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index fb72b0006d5c..74473867f3f6 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -165,7 +165,7 @@ extern "C" { * supports QEMU_ERROR, this will be reported at compile time; otherwise * this will be reported at link time due to the missing symbol. */ -extern void QEMU_NORETURN QEMU_ERROR("code path is reachable") +G_NORETURN extern void QEMU_ERROR("code path is reachable") qemu_build_not_reached_always(void); #if defined(__OPTIMIZE__) && !defined(__NO_INLINE__) #define qemu_build_not_reached() qemu_build_not_reached_always() diff --git a/include/qemu/thread.h b/include/qemu/thread.h index 460568d67d53..af19f2b3fc7d 100644 --- a/include/qemu/thread.h +++ b/include/qemu/thread.h @@ -188,7 +188,7 @@ void qemu_thread_create(QemuThread *thread, const char = *name, void *qemu_thread_join(QemuThread *thread); void qemu_thread_get_self(QemuThread *thread); bool qemu_thread_is_self(QemuThread *thread); -void qemu_thread_exit(void *retval) QEMU_NORETURN; +G_NORETURN void qemu_thread_exit(void *retval); void qemu_thread_naming(bool enable); =20 struct Notifier; diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index bf40942de4ab..121a156933a5 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -72,8 +72,8 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong ad= dr, uint64_t val, =20 #else =20 -void QEMU_NORETURN helper_unaligned_ld(CPUArchState *env, target_ulong add= r); -void QEMU_NORETURN helper_unaligned_st(CPUArchState *env, target_ulong add= r); +G_NORETURN void helper_unaligned_ld(CPUArchState *env, target_ulong addr); +G_NORETURN void helper_unaligned_st(CPUArchState *env, target_ulong addr); =20 #endif /* CONFIG_SOFTMMU */ #endif /* TCG_LDST_H */ diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 42f5b500ed6a..592692ba72bd 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -395,7 +395,7 @@ typedef TCGv_ptr TCGv_env; #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 /* Helper can be safely suppressed if the return value is not used. */ #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 -/* Helper is QEMU_NORETURN. */ +/* Helper is G_NORETURN. */ #define TCG_CALL_NO_RETURN 0x0008 =20 /* convenience version of most used call flags */ diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h index a8fdd6933b23..7a13a58ca02f 100644 --- a/linux-user/user-internals.h +++ b/linux-user/user-internals.h @@ -64,7 +64,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, abi_long arg5, abi_long arg6, abi_long arg7, abi_long arg8); extern __thread CPUState *thread_cpu; -void QEMU_NORETURN cpu_loop(CPUArchState *env); +G_NORETURN void cpu_loop(CPUArchState *env); const char *target_strerror(int err); int get_osversion(void); void init_qemu_uname_release(void); diff --git a/scripts/cocci-macro-file.h b/scripts/cocci-macro-file.h index 3d1e9b50919a..d247a5086e91 100644 --- a/scripts/cocci-macro-file.h +++ b/scripts/cocci-macro-file.h @@ -19,7 +19,7 @@ */ =20 /* From qemu/compiler.h */ -#define QEMU_NORETURN __attribute__ ((__noreturn__)) +#define G_NORETURN __attribute__ ((__noreturn__)) #define G_GNUC_WARN_UNUSED_RESULT __attribute__((warn_unused_result)) #define G_GNUC_NULL_TERMINATED __attribute__((sentinel)) =20 diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index e81921150392..6beb2bcfe832 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -438,8 +438,8 @@ void alpha_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU =20 void alpha_cpu_list(void); -void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); -void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); +G_NORETURN void dynamic_excp(CPUAlphaState *, uintptr_t, int, int); +G_NORETURN void arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); =20 uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env); void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); @@ -456,9 +456,9 @@ void alpha_cpu_record_sigbus(CPUState *cs, vaddr addres= s, bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; +G_NORETURN void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, i= nt mmu_idx, + uintptr_t retaddr); void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/target/arm/internals.h b/target/arm/internals.h index 3f05748ea47b..d8eb0ae4f5bd 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -102,13 +102,13 @@ FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-= be-1 prefix */ * and target exception level. This should be called from helper functions, * and never returns because we will longjump back up to the CPU main loop. */ -void QEMU_NORETURN raise_exception(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_el); +G_NORETURN void raise_exception(CPUARMState *env, uint32_t excp, + uint32_t syndrome, uint32_t target_el); =20 /* * Similarly, but also use unwinding to restore cpu state. */ -void QEMU_NORETURN raise_exception_ra(CPUARMState *env, uint32_t excp, +G_NORETURN void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, uint32_t target_e= l, uintptr_t ra); =20 @@ -600,9 +600,9 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env= , bool secstate); bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); =20 /* Raise a data fault alignment exception for the specified virtual addres= s */ -void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) QEMU_NORE= TURN; +G_NORETURN void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr= ); =20 /* arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 93c119532a2a..c17b5b9c871d 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -344,6 +344,6 @@ extern const VMStateDescription vmstate_hppa_cpu; void hppa_cpu_alarm_timer(void *); int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); #endif -void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_= t ra); +G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t r= a); =20 #endif /* HPPA_CPU_H */ diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 0a4401e917f9..34167e2e29ca 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -69,27 +69,27 @@ static inline target_long lshift(target_long x, int n) void tcg_x86_init(void); =20 /* excp_helper.c */ -void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); -void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_inde= x, - uintptr_t retaddr); -void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_ind= ex, - int error_code); -void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_= index, - int error_code, uintptr_t retadd= r); -void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_in= t, - int error_code, int next_eip_addend); +G_NORETURN void raise_exception(CPUX86State *env, int exception_index); +G_NORETURN void raise_exception_ra(CPUX86State *env, int exception_index, + uintptr_t retaddr); +G_NORETURN void raise_exception_err(CPUX86State *env, int exception_index, + int error_code); +G_NORETURN void raise_exception_err_ra(CPUX86State *env, int exception_ind= ex, + int error_code, uintptr_t retaddr); +G_NORETURN void raise_interrupt(CPUX86State *nenv, int intno, int is_int, + int error_code, int next_eip_addend); =20 /* cc_helper.c */ extern const uint8_t parity_table[256]; =20 /* misc_helper.c */ void cpu_load_eflags(CPUX86State *env, int eflags, int update_mask); -void do_pause(CPUX86State *env) QEMU_NORETURN; +G_NORETURN void do_pause(CPUX86State *env); =20 /* sysemu/svm_helper.c */ #ifndef CONFIG_USER_ONLY -void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, - uint64_t exit_info_1, uintptr_t retaddr); +G_NORETURN void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, + uint64_t exit_info_1, uintptr_t retaddr); void do_vmexit(CPUX86State *env); #endif =20 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e9cd0b88dea4..76c24d40d404 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -359,9 +359,9 @@ struct MicroBlazeCPU { void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); #endif /* !CONFIG_USER_ONLY */ -void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) QEMU_NORET= URN; +G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 466768aec487..1d1e950e458e 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -18,18 +18,18 @@ void mips_tcg_init(void); =20 void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb= ); -void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; +G_NORETURN void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, in= t mmu_idx, + uintptr_t retaddr); =20 const char *mips_exception_name(int32_t exception); =20 -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exce= ption, - int error_code, uintptr_t pc); +G_NORETURN void do_raise_exception_err(CPUMIPSState *env, uint32_t excepti= on, + int error_code, uintptr_t pc); =20 -static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, - uint32_t exception, - uintptr_t pc) +G_NORETURN static inline void do_raise_exception(CPUMIPSState *env, + uint32_t exception, + uintptr_t pc) { do_raise_exception_err(env, exception, 0, pc); } diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index d2ba0c5bbd82..60b314d3d634 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -196,9 +196,9 @@ void nios2_cpu_do_interrupt(CPUState *cs); void dump_mmu(CPUNios2State *env); void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; +G_NORETURN void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, i= nt mmu_idx, + uintptr_t retaddr); =20 void do_nios2_semihosting(CPUNios2State *env); =20 diff --git a/target/openrisc/exception.h b/target/openrisc/exception.h index 333bf846388d..f62fc314c1f4 100644 --- a/target/openrisc/exception.h +++ b/target/openrisc/exception.h @@ -22,6 +22,6 @@ =20 #include "cpu.h" =20 -void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp); +G_NORETURN void raise_exception(OpenRISCCPU *cpu, uint32_t excp); =20 #endif /* TARGET_OPENRISC_EXCEPTION_H */ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 5b01d409b31a..8355ed2cf6b6 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2491,13 +2491,13 @@ static inline void cpu_get_tb_cpu_state(CPUPPCState= *env, target_ulong *pc, } #endif =20 -void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception); -void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception, - uintptr_t raddr); -void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exceptio= n, - uint32_t error_code); -void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t excep= tion, - uint32_t error_code, uintptr_t r= addr); +G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception); +G_NORETURN void raise_exception_ra(CPUPPCState *env, uint32_t exception, + uintptr_t raddr); +G_NORETURN void raise_exception_err(CPUPPCState *env, uint32_t exception, + uint32_t error_code); +G_NORETURN void raise_exception_err_ra(CPUPPCState *env, uint32_t exceptio= n, + uint32_t error_code, uintptr_t radd= r); =20 #if !defined(CONFIG_USER_ONLY) static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 6aa9484f34a5..8094e0b03371 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -286,9 +286,9 @@ void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; +G_NORETURN void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int= mmu_idx, + uintptr_t retaddr); #endif =20 #endif /* PPC_INTERNAL_H */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8183fb86d5db..e0cf15697bf4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -448,9 +448,9 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, boo= l enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; +G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, = int mmu_idx, + uintptr_t retaddr); bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -484,8 +484,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, = uint32_t priv, void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); =20 void riscv_translate_init(void); -void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, - uint32_t exception, uintptr_t pc); +G_NORETURN void riscv_raise_exception(CPURISCVState *env, + uint32_t exception, uintptr_t pc); =20 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 6fc8cad2d586..6aba7fd0ca8a 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -280,9 +280,9 @@ void s390_cpu_record_sigbus(CPUState *cs, vaddr address, bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; +G_NORETURN void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, i= nt mmu_idx, + uintptr_t retaddr); #endif =20 =20 diff --git a/target/s390x/tcg/tcg_s390x.h b/target/s390x/tcg/tcg_s390x.h index 2f54ccb02745..78558912f99f 100644 --- a/target/s390x/tcg/tcg_s390x.h +++ b/target/s390x/tcg/tcg_s390x.h @@ -14,11 +14,11 @@ #define TCG_S390X_H =20 void tcg_s390_tod_updated(CPUState *cs, run_on_cpu_data opaque); -void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env, - uint32_t code, uintptr_t ra); -void QEMU_NORETURN tcg_s390_data_exception(CPUS390XState *env, uint32_t dx= c, - uintptr_t ra); -void QEMU_NORETURN tcg_s390_vector_exception(CPUS390XState *env, uint32_t = vxc, - uintptr_t ra); +G_NORETURN void tcg_s390_program_interrupt(CPUS390XState *env, + uint32_t code, uintptr_t ra); +G_NORETURN void tcg_s390_data_exception(CPUS390XState *env, uint32_t dxc, + uintptr_t ra); +G_NORETURN void tcg_s390_vector_exception(CPUS390XState *env, uint32_t vxc, + uintptr_t ra); =20 #endif /* TCG_S390X_H */ diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index fb9dd9db2ffd..7465d6afee96 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -209,9 +209,9 @@ void superh_cpu_dump_state(CPUState *cpu, FILE *f, int = flags); hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; +G_NORETURN void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, = int mmu_idx, + uintptr_t retaddr); =20 void sh4_translate_init(void); void sh4_cpu_list(void); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 5a7f1ed5d617..5b3eda98b39b 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -574,11 +574,11 @@ void sparc_cpu_do_interrupt(CPUState *cpu); hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, - uintptr_t retaddr); -void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN; +G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, + uintptr_t retaddr); +G_NORETURN void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t); =20 #ifndef NO_CPU_IO_DEFS /* cpu_init.c */ diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 02143f2f7768..5b4a22816ff8 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -582,7 +582,7 @@ int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteAr= ray *buf, int reg); int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) QEMU_NORETURN; + uintptr_t retaddr) G_NORETURN; =20 #define cpu_list xtensa_cpu_list =20 diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index d8162673ae8d..ea4a0dd2fbcc 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -28,12 +28,12 @@ void *probe_access(CPUArchState *env, target_ulong addr= , int size, g_assert_not_reached(); } =20 -void QEMU_NORETURN cpu_loop_exit(CPUState *cpu) +G_NORETURN void cpu_loop_exit(CPUState *cpu) { g_assert_not_reached(); } =20 -void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc) +G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc) { g_assert_not_reached(); } diff --git a/bsd-user/signal.c b/bsd-user/signal.c index 0bc6d2edbd93..87b7246452fa 100644 --- a/bsd-user/signal.c +++ b/bsd-user/signal.c @@ -346,7 +346,7 @@ static int core_dump_signal(int sig) } =20 /* Abort execution with signal. */ -static void QEMU_NORETURN dump_core_and_abort(int target_sig) +G_NORETURN static void dump_core_and_abort(int target_sig) { CPUArchState *env =3D thread_cpu->env_ptr; CPUState *cpu =3D env_cpu(env); diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 80683fed318b..88b53dde0101 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -189,7 +189,7 @@ static void wake_blocked_threads(ITCStorageCell *c) c->blocked_threads =3D 0; } =20 -static void QEMU_NORETURN block_thread_and_exit(ITCStorageCell *c) +G_NORETURN static void block_thread_and_exit(ITCStorageCell *c) { c->blocked_threads |=3D 1ULL << current_cpu->cpu_index; current_cpu->halted =3D 1; diff --git a/linux-user/signal.c b/linux-user/signal.c index 27a0ff30e971..b4e638471259 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -725,7 +725,7 @@ void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong a= ddr, } =20 /* abort execution with signal */ -static void QEMU_NORETURN dump_core_and_abort(int target_sig) +G_NORETURN static void dump_core_and_abort(int target_sig) { CPUState *cpu =3D thread_cpu; CPUArchState *env =3D cpu->env_ptr; diff --git a/monitor/hmp.c b/monitor/hmp.c index 35827a843ddd..08c5095f5dcc 100644 --- a/monitor/hmp.c +++ b/monitor/hmp.c @@ -308,7 +308,7 @@ void help_cmd(Monitor *mon, const char *name) static const char *pch; static sigjmp_buf expr_env; =20 -static void G_GNUC_PRINTF(2, 3) QEMU_NORETURN +G_NORETURN static void G_GNUC_PRINTF(2, 3) expr_error(Monitor *mon, const char *fmt, ...) { va_list ap; diff --git a/qemu-img.c b/qemu-img.c index 30850bcf4610..bb9762c13b00 100644 --- a/qemu-img.c +++ b/qemu-img.c @@ -98,7 +98,8 @@ static void format_print(void *opaque, const char *name) printf(" %s", name); } =20 -static void QEMU_NORETURN G_GNUC_PRINTF(1, 2) error_exit(const char *fmt, = ...) +G_NORETURN G_GNUC_PRINTF(1, 2) +static void error_exit(const char *fmt, ...) { va_list ap; =20 @@ -110,18 +111,18 @@ static void QEMU_NORETURN G_GNUC_PRINTF(1, 2) error_e= xit(const char *fmt, ...) exit(EXIT_FAILURE); } =20 -static void QEMU_NORETURN missing_argument(const char *option) +G_NORETURN static void missing_argument(const char *option) { error_exit("missing argument for option '%s'", option); } =20 -static void QEMU_NORETURN unrecognized_option(const char *option) +G_NORETURN static void unrecognized_option(const char *option) { error_exit("unrecognized option '%s'", option); } =20 /* Please keep in synch with docs/tools/qemu-img.rst */ -static void QEMU_NORETURN help(void) +G_NORETURN static void help(void) { const char *help_msg =3D QEMU_IMG_VERSION diff --git a/target/alpha/helper.c b/target/alpha/helper.c index b7e7f73b15cc..40e27b1dc701 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -514,7 +514,7 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) =20 /* This should only be called from translate, via gen_excp. We expect that ENV->PC has already been updated. */ -void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error) +G_NORETURN void helper_excp(CPUAlphaState *env, int excp, int error) { CPUState *cs =3D env_cpu(env); =20 @@ -524,8 +524,8 @@ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int = excp, int error) } =20 /* This may be called from any of the helpers to set up EXCEPTION_INDEX. = */ -void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr, - int excp, int error) +G_NORETURN void dynamic_excp(CPUAlphaState *env, uintptr_t retaddr, + int excp, int error) { CPUState *cs =3D env_cpu(env); =20 @@ -539,8 +539,8 @@ void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uin= tptr_t retaddr, cpu_loop_exit(cs); } =20 -void QEMU_NORETURN arith_excp(CPUAlphaState *env, uintptr_t retaddr, - int exc, uint64_t mask) +G_NORETURN void arith_excp(CPUAlphaState *env, uintptr_t retaddr, + int exc, uint64_t mask) { env->trap_arg0 =3D exc; env->trap_arg1 =3D mask; diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index cd6df18150bf..eebd5f2cda84 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -382,8 +382,8 @@ static uint64_t pauth_strip(CPUARMState *env, uint64_t = ptr, bool data) return pauth_original_ptr(ptr, param); } =20 -static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el, - uintptr_t ra) +G_NORETURN static void pauth_trap(CPUARMState *env, int target_el, + uintptr_t ra) { raise_exception_ra(env, EXCP_UDEF, syn_pactrap(), target_el, ra); } diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index b79004e0cca6..aa8f0cbbbccb 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -79,9 +79,9 @@ static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUF= aultInfo *fi, return fsr; } =20 -static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, ARMMMUFaultInfo *= fi) +G_NORETURN static void arm_deliver_fault(ARMCPU *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi) { CPUARMState *env =3D &cpu->env; int target_el; diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 057baf9a48f5..3a5219009e6b 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -34,9 +34,9 @@ #define SF_MANTBITS 23 =20 /* Exceptions processing helpers */ -static void QEMU_NORETURN do_raise_exception_err(CPUHexagonState *env, - uint32_t exception, - uintptr_t pc) +G_NORETURN static void do_raise_exception_err(CPUHexagonState *env, + uint32_t exception, + uintptr_t pc) { CPUState *cs =3D env_cpu(env); qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); @@ -44,7 +44,7 @@ static void QEMU_NORETURN do_raise_exception_err(CPUHexag= onState *env, cpu_loop_exit_restore(cs, pc); } =20 -void QEMU_NORETURN HELPER(raise_exception)(CPUHexagonState *env, uint32_t = excp) +G_NORETURN void HELPER(raise_exception)(CPUHexagonState *env, uint32_t exc= p) { do_raise_exception_err(env, excp, 0); } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 37b763fca0ff..f584ff75dc7e 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -72,7 +72,7 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disasse= mble_info *info) } =20 #ifndef CONFIG_USER_ONLY -static void QEMU_NORETURN +G_NORETURN static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index b0dec4ebf468..52ae70cf9f40 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -27,7 +27,7 @@ #include "fpu/softfloat.h" #include "trace.h" =20 -void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp) +G_NORETURN void HELPER(excp)(CPUHPPAState *env, int excp) { CPUState *cs =3D env_cpu(env); =20 @@ -35,7 +35,7 @@ void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int ex= cp) cpu_loop_exit(cs); } =20 -void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_= t ra) +G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t r= a) { CPUState *cs =3D env_cpu(env); =20 diff --git a/target/i386/tcg/bpt_helper.c b/target/i386/tcg/bpt_helper.c index b6c1fff16e51..bc34ac27fea7 100644 --- a/target/i386/tcg/bpt_helper.c +++ b/target/i386/tcg/bpt_helper.c @@ -22,7 +22,7 @@ #include "exec/helper-proto.h" #include "helper-tcg.h" =20 -void QEMU_NORETURN helper_single_step(CPUX86State *env) +G_NORETURN void helper_single_step(CPUX86State *env) { #ifndef CONFIG_USER_ONLY check_hw_breakpoints(env, true); diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c index bdae887d0abc..f375419324ee 100644 --- a/target/i386/tcg/excp_helper.c +++ b/target/i386/tcg/excp_helper.c @@ -25,13 +25,13 @@ #include "exec/helper-proto.h" #include "helper-tcg.h" =20 -void QEMU_NORETURN helper_raise_interrupt(CPUX86State *env, int intno, +G_NORETURN void helper_raise_interrupt(CPUX86State *env, int intno, int next_eip_addend) { raise_interrupt(env, intno, 1, 0, next_eip_addend); } =20 -void QEMU_NORETURN helper_raise_exception(CPUX86State *env, int exception_= index) +G_NORETURN void helper_raise_exception(CPUX86State *env, int exception_ind= ex) { raise_exception(env, exception_index); } @@ -87,10 +87,10 @@ static int check_exception(CPUX86State *env, int intno,= int *error_code, * env->eip value AFTER the interrupt instruction. It is only relevant if * is_int is TRUE. */ -static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno, - int is_int, int error_code, - int next_eip_addend, - uintptr_t retaddr) +G_NORETURN static void raise_interrupt2(CPUX86State *env, int intno, + int is_int, int error_code, + int next_eip_addend, + uintptr_t retaddr) { CPUState *cs =3D env_cpu(env); =20 @@ -111,31 +111,31 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86Stat= e *env, int intno, =20 /* shortcuts to generate exceptions */ =20 -void QEMU_NORETURN raise_interrupt(CPUX86State *env, int intno, int is_int, - int error_code, int next_eip_addend) +G_NORETURN void raise_interrupt(CPUX86State *env, int intno, int is_int, + int error_code, int next_eip_addend) { raise_interrupt2(env, intno, is_int, error_code, next_eip_addend, 0); } =20 -void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_ind= ex, - int error_code) +G_NORETURN void raise_exception_err(CPUX86State *env, int exception_index, + int error_code) { raise_interrupt2(env, exception_index, 0, error_code, 0, 0); } =20 -void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_= index, - int error_code, uintptr_t retadd= r) +G_NORETURN void raise_exception_err_ra(CPUX86State *env, int exception_ind= ex, + int error_code, uintptr_t retaddr) { raise_interrupt2(env, exception_index, 0, error_code, 0, retaddr); } =20 -void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index) +G_NORETURN void raise_exception(CPUX86State *env, int exception_index) { raise_interrupt2(env, exception_index, 0, 0, 0, 0); } =20 -void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_inde= x, - uintptr_t retaddr) +G_NORETURN void raise_exception_ra(CPUX86State *env, int exception_index, + uintptr_t retaddr) { raise_interrupt2(env, exception_index, 0, 0, 0, retaddr); } diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index 5769db5ace80..da1c6db6dc35 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -80,7 +80,7 @@ void helper_rdtscp(CPUX86State *env) env->regs[R_ECX] =3D (uint32_t)(env->tsc_aux); } =20 -void QEMU_NORETURN helper_rdpmc(CPUX86State *env) +G_NORETURN void helper_rdpmc(CPUX86State *env) { if (((env->cr[4] & CR4_PCE_MASK) =3D=3D 0 ) && ((env->hflags & HF_CPL_MASK) !=3D 0)) { @@ -93,7 +93,7 @@ void QEMU_NORETURN helper_rdpmc(CPUX86State *env) raise_exception_err(env, EXCP06_ILLOP, 0); } =20 -void QEMU_NORETURN do_pause(CPUX86State *env) +G_NORETURN void do_pause(CPUX86State *env) { CPUState *cs =3D env_cpu(env); =20 @@ -102,7 +102,7 @@ void QEMU_NORETURN do_pause(CPUX86State *env) cpu_loop_exit(cs); } =20 -void QEMU_NORETURN helper_pause(CPUX86State *env, int next_eip_addend) +G_NORETURN void helper_pause(CPUX86State *env, int next_eip_addend) { cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0, GETPC()); env->eip +=3D next_eip_addend; diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/= misc_helper.c index 9ccaa054c4ca..cebdf6fafe61 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -470,7 +470,7 @@ void helper_flush_page(CPUX86State *env, target_ulong a= ddr) tlb_flush_page(env_cpu(env), addr); } =20 -static void QEMU_NORETURN do_hlt(CPUX86State *env) +G_NORETURN static void do_hlt(CPUX86State *env) { CPUState *cs =3D env_cpu(env); =20 @@ -480,7 +480,7 @@ static void QEMU_NORETURN do_hlt(CPUX86State *env) cpu_loop_exit(cs); } =20 -void QEMU_NORETURN helper_hlt(CPUX86State *env, int next_eip_addend) +G_NORETURN void helper_hlt(CPUX86State *env, int next_eip_addend) { cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC()); env->eip +=3D next_eip_addend; @@ -497,7 +497,7 @@ void helper_monitor(CPUX86State *env, target_ulong ptr) cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0, GETPC()); } =20 -void QEMU_NORETURN helper_mwait(CPUX86State *env, int next_eip_addend) +G_NORETURN void helper_mwait(CPUX86State *env, int next_eip_addend) { CPUState *cs =3D env_cpu(env); =20 diff --git a/target/openrisc/exception.c b/target/openrisc/exception.c index 28c1fce5232a..8699c3dcea42 100644 --- a/target/openrisc/exception.c +++ b/target/openrisc/exception.c @@ -22,7 +22,7 @@ #include "exec/exec-all.h" #include "exception.h" =20 -void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp) +G_NORETURN void raise_exception(OpenRISCCPU *cpu, uint32_t excp) { CPUState *cs =3D CPU(cpu); =20 diff --git a/target/openrisc/exception_helper.c b/target/openrisc/exception= _helper.c index d02a1cf0aa14..3e011d37f700 100644 --- a/target/openrisc/exception_helper.c +++ b/target/openrisc/exception_helper.c @@ -30,7 +30,7 @@ void HELPER(exception)(CPUOpenRISCState *env, uint32_t ex= cp) raise_exception(cpu, excp); } =20 -static void QEMU_NORETURN do_range(CPUOpenRISCState *env, uintptr_t pc) +G_NORETURN static void do_range(CPUOpenRISCState *env, uintptr_t pc) { CPUState *cs =3D env_cpu(env); =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 1a75ba11e68f..df3573688325 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -24,8 +24,8 @@ #include "exec/helper-proto.h" =20 /* Exceptions processing helpers */ -void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, - uint32_t exception, uintptr_t pc) +G_NORETURN void riscv_raise_exception(CPURISCVState *env, + uint32_t exception, uintptr_t pc) { CPUState *cs =3D env_cpu(env); cs->exception_index =3D exception; diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index 11f952d34099..66d8b29b1bc8 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -24,8 +24,8 @@ #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" =20 -static inline void QEMU_NORETURN raise_exception(CPURXState *env, int inde= x, - uintptr_t retaddr); +G_NORETURN static inline void raise_exception(CPURXState *env, int index, + uintptr_t retaddr); =20 static void _set_psw(CPURXState *env, uint32_t psw, uint32_t rte) { @@ -418,8 +418,8 @@ uint32_t helper_divu(CPURXState *env, uint32_t num, uin= t32_t den) } =20 /* exception */ -static inline void QEMU_NORETURN raise_exception(CPURXState *env, int inde= x, - uintptr_t retaddr) +G_NORETURN static inline void raise_exception(CPURXState *env, int index, + uintptr_t retaddr) { CPUState *cs =3D env_cpu(env); =20 @@ -427,22 +427,22 @@ static inline void QEMU_NORETURN raise_exception(CPUR= XState *env, int index, cpu_loop_exit_restore(cs, retaddr); } =20 -void QEMU_NORETURN helper_raise_privilege_violation(CPURXState *env) +G_NORETURN void helper_raise_privilege_violation(CPURXState *env) { raise_exception(env, 20, GETPC()); } =20 -void QEMU_NORETURN helper_raise_access_fault(CPURXState *env) +G_NORETURN void helper_raise_access_fault(CPURXState *env) { raise_exception(env, 21, GETPC()); } =20 -void QEMU_NORETURN helper_raise_illegal_instruction(CPURXState *env) +G_NORETURN void helper_raise_illegal_instruction(CPURXState *env) { raise_exception(env, 23, GETPC()); } =20 -void QEMU_NORETURN helper_wait(CPURXState *env) +G_NORETURN void helper_wait(CPURXState *env) { CPUState *cs =3D env_cpu(env); =20 @@ -451,12 +451,12 @@ void QEMU_NORETURN helper_wait(CPURXState *env) raise_exception(env, EXCP_HLT, 0); } =20 -void QEMU_NORETURN helper_rxint(CPURXState *env, uint32_t vec) +G_NORETURN void helper_rxint(CPURXState *env, uint32_t vec) { raise_exception(env, 0x100 + vec, 0); } =20 -void QEMU_NORETURN helper_rxbrk(CPURXState *env) +G_NORETURN void helper_rxbrk(CPURXState *env) { raise_exception(env, 0x100, 0); } diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 4e7648f301b3..ee6359755760 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -33,8 +33,8 @@ #include "hw/boards.h" #endif =20 -void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env, - uint32_t code, uintptr_t ra) +G_NORETURN void tcg_s390_program_interrupt(CPUS390XState *env, + uint32_t code, uintptr_t ra) { CPUState *cs =3D env_cpu(env); =20 @@ -45,8 +45,8 @@ void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XSta= te *env, cpu_loop_exit(cs); } =20 -void QEMU_NORETURN tcg_s390_data_exception(CPUS390XState *env, uint32_t dx= c, - uintptr_t ra) +G_NORETURN void tcg_s390_data_exception(CPUS390XState *env, uint32_t dxc, + uintptr_t ra) { g_assert(dxc <=3D 0xff); #if !defined(CONFIG_USER_ONLY) @@ -62,8 +62,8 @@ void QEMU_NORETURN tcg_s390_data_exception(CPUS390XState = *env, uint32_t dxc, tcg_s390_program_interrupt(env, PGM_DATA, ra); } =20 -void QEMU_NORETURN tcg_s390_vector_exception(CPUS390XState *env, uint32_t = vxc, - uintptr_t ra) +G_NORETURN void tcg_s390_vector_exception(CPUS390XState *env, uint32_t vxc, + uintptr_t ra) { g_assert(vxc <=3D 0xff); #if !defined(CONFIG_USER_ONLY) @@ -87,7 +87,7 @@ void HELPER(data_exception)(CPUS390XState *env, uint32_t = dxc) * this is only for the atomic operations, for which we want to raise a * specification exception. */ -static void QEMU_NORETURN do_unaligned_access(CPUState *cs, uintptr_t reta= ddr) +G_NORETURN static void do_unaligned_access(CPUState *cs, uintptr_t retaddr) { S390CPU *cpu =3D S390_CPU(cs); CPUS390XState *env =3D &cpu->env; @@ -619,9 +619,9 @@ void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, do_unaligned_access(cs, retaddr); } =20 -static void QEMU_NORETURN monitor_event(CPUS390XState *env, - uint64_t monitor_code, - uint8_t monitor_class, uintptr_t r= a) +G_NORETURN static void monitor_event(CPUS390XState *env, + uint64_t monitor_code, + uint8_t monitor_class, uintptr_t ra) { /* Store the Monitor Code and the Monitor Class Number into the lowcor= e */ stq_phys(env_cpu(env)->as, diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 752669825f02..c5c3b9f645ca 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -57,8 +57,8 @@ void helper_ldtlb(CPUSH4State *env) #endif } =20 -static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int ind= ex, - uintptr_t retaddr) +G_NORETURN static inline void raise_exception(CPUSH4State *env, int index, + uintptr_t retaddr) { CPUState *cs =3D env_cpu(env); =20 diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index f2668389b07a..7e3f46b9cfd7 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -924,10 +924,10 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, va= ddr addr) } =20 #ifndef CONFIG_USER_ONLY -void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, - uintptr_t retaddr) +G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, + uintptr_t retaddr) { SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 9476d10d0065..68e46446c1a7 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -25,7 +25,7 @@ =20 /* Exception helpers */ =20 -static void QEMU_NORETURN +G_NORETURN static void raise_exception_sync_internal(CPUTriCoreState *env, uint32_t class, int ti= n, uintptr_t pc, uint32_t fcd_pc) { diff --git a/tcg/tcg.c b/tcg/tcg.c index 528277d1d3c3..aea0bd8100e1 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -320,7 +320,7 @@ static void set_jmp_reset_offset(TCGContext *s, int whi= ch) } =20 /* Signal overflow, starting over with fewer guest insns. */ -static void QEMU_NORETURN tcg_raise_tb_overflow(TCGContext *s) +static void G_NORETURN tcg_raise_tb_overflow(TCGContext *s) { siglongjmp(s->jmp_trans, -2); } diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index c24baf85350a..2c068b47e117 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -545,7 +545,7 @@ static int round_name_to_mode(const char *name) return -1; } =20 -static void QEMU_NORETURN die_host_rounding(enum rounding rounding) +G_NORETURN static void die_host_rounding(enum rounding rounding) { fprintf(stderr, "fatal: '%s' rounding not supported on this host\n", round_names[rounding]); diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 352dd71c44fa..9831fc5c595f 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -921,7 +921,7 @@ static void parse_args(int argc, char *argv[]) } } =20 -static void QEMU_NORETURN run_test(void) +G_NORETURN static void run_test(void) { unsigned int i; =20 diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index ddc6003de280..41f85699d030 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -223,7 +223,7 @@ our $Sparse =3D qr{ our $Attribute =3D qr{ const| volatile| - QEMU_NORETURN| + G_NORETURN| G_GNUC_WARN_UNUSED_RESULT| G_GNUC_NULL_TERMINATED| QEMU_PACKED| --=20 2.35.1.273.ge6ebfd0e8cbb From nobody Tue Sep 9 19:54:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645728997102166.61032032271657; Thu, 24 Feb 2022 10:56:37 -0800 (PST) Received: from localhost ([::1]:34978 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nNJI2-0001wo-VK for importer@patchew.org; Thu, 24 Feb 2022 13:56:34 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52760) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNJ0X-000150-OH for qemu-devel@nongnu.org; Thu, 24 Feb 2022 13:38:30 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]:35404) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNJ0K-0003Py-JG for qemu-devel@nongnu.org; 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bh=pcjvjcaDtVmzu8OGH23h2GJ6X2ENvGSrBr5zKq8PWRY=; b=WVkWgXydtpyO/BsRXWGSuFQzrEA/73bA7BWvROaGAyxNVrHpVgiHUDX4d5ATeXY2eSk2Dv 5dG1DuTnOQMyObOF4x8ulMobSIcE08gzZVDNbqFQK9IGN2PX7eOPMdtAY6UMIFMvj3PIz4 2+Z0GHrwJKWtD1aYjktByHypvB98elk= X-MC-Unique: PQKB3HKyM0-ceOkyz1VBTA-1 From: marcandre.lureau@redhat.com To: qemu-devel@nongnu.org Subject: [PATCH 05/12] compiler.h: drop __printf__ macro MinGW/glib workaround Date: Thu, 24 Feb 2022 22:36:54 +0400 Message-Id: <20220224183701.608720-6-marcandre.lureau@redhat.com> In-Reply-To: <20220224183701.608720-1-marcandre.lureau@redhat.com> References: <20220224183701.608720-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=marcandre.lureau@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, f4bug@amsat.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645728999163100001 From: Marc-Andr=C3=A9 Lureau This workaround was added in commit 95df51a4 ("w32: Always use standard instead of native format strings"), as it claimed glib was using __printf__ attribute. This is surprising, since glib has always used G_GNUC_PRINTF which, as the name implies, uses __gnu_printf__ when possible. Apparently, the workaound is no longer relevant though, I don't see the warnings. Signed-off-by: Marc-Andr=C3=A9 Lureau --- include/qemu/compiler.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index 2704c314dcac..eb29b72c14d7 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -73,14 +73,6 @@ #define QEMU_BUILD_BUG_ON_ZERO(x) (sizeof(QEMU_BUILD_BUG_ON_STRUCT(x)) - \ sizeof(QEMU_BUILD_BUG_ON_STRUCT(x))) =20 -#if !defined(__clang__) && defined(_WIN32) -/* - * Map __printf__ to __gnu_printf__ because we want standard format string= s even - * when MinGW or GLib include files use __printf__. - */ -# define __printf__ __gnu_printf__ -#endif - #ifndef __has_warning #define __has_warning(x) 0 /* compatibility with non-clang compilers */ #endif --=20 2.35.1.273.ge6ebfd0e8cbb From nobody Tue Sep 9 19:54:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 24 Feb 2022 13:38:26 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 250561091DA7; Thu, 24 Feb 2022 18:38:25 +0000 (UTC) Received: from localhost (unknown [10.39.208.2]) by smtp.corp.redhat.com (Postfix) with ESMTP id 5D34F866C5; Thu, 24 Feb 2022 18:38:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1645727909; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iKH2YRw461wsoQGs7ixYk52roLtiX0XIcMDHNHQi/Ao=; b=Ldp3qt6MuC1Vij0HApV8dCBlxP4iYN1pYdUuBZcmzRIJT6KmXxGV+a2agYTHG/7/ugekwh 5i0FuOzPy/wFPLRj9POJ/w+MLFQegZaC1bx521MPH8ts8wavUyfW0881tV67aK9WpaNCg/ ufca4RqqGVJzEvniM3HBjasjaff5cSs= X-MC-Unique: ciqhx63KNLWv4UQ9c8S_zQ-1 From: marcandre.lureau@redhat.com To: qemu-devel@nongnu.org Subject: [PATCH 06/12] Replace config-time define HOST_WORDS_BIGENDIAN Date: Thu, 24 Feb 2022 22:36:55 +0400 Message-Id: <20220224183701.608720-7-marcandre.lureau@redhat.com> In-Reply-To: <20220224183701.608720-1-marcandre.lureau@redhat.com> References: <20220224183701.608720-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=marcandre.lureau@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, f4bug@amsat.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645729067580100001 From: Marc-Andr=C3=A9 Lureau Replace a config-time define with a compile time condition define (compatible with clang and gcc) that must be declared prior to its usage. This avoids having a global configure time define, but also prevents from bad usage, if the config header wasn't included before. This can help to make some code independent from qemu too. gcc supports __BYTE_ORDER__ from about 4.6 and clang from 3.2. Signed-off-by: Marc-Andr=C3=A9 Lureau --- meson.build | 1 - accel/tcg/atomic_template.h | 4 +- audio/audio.h | 2 +- hw/display/pl110_template.h | 6 +-- hw/net/can/ctucan_core.h | 2 +- hw/net/vmxnet3.h | 4 +- include/exec/cpu-all.h | 4 +- include/exec/cpu-common.h | 2 +- include/exec/memop.h | 2 +- include/exec/memory.h | 2 +- include/fpu/softfloat-types.h | 2 +- include/hw/core/cpu.h | 2 +- include/hw/i386/intel_iommu.h | 6 +-- include/hw/i386/x86-iommu.h | 4 +- include/hw/virtio/virtio-access.h | 6 +-- include/hw/virtio/virtio-gpu-bswap.h | 2 +- include/libdecnumber/dconfig.h | 2 +- include/net/eth.h | 2 +- include/qemu/bswap.h | 8 ++-- include/qemu/compiler.h | 2 + include/qemu/host-utils.h | 2 +- include/qemu/int128.h | 2 +- include/ui/qemu-pixman.h | 2 +- net/util.h | 2 +- target/arm/cpu.h | 8 ++-- target/arm/translate-a64.h | 2 +- target/arm/vec_internal.h | 2 +- target/i386/cpu.h | 2 +- target/mips/cpu.h | 2 +- target/ppc/cpu.h | 2 +- target/s390x/tcg/vec.h | 2 +- target/xtensa/cpu.h | 2 +- tests/fp/platform.h | 4 +- accel/kvm/kvm-all.c | 4 +- audio/dbusaudio.c | 2 +- disas.c | 2 +- hw/core/loader.c | 4 +- hw/display/artist.c | 6 +-- hw/display/pxa2xx_lcd.c | 2 +- hw/display/vga.c | 12 +++--- hw/display/virtio-gpu-gl.c | 2 +- hw/s390x/event-facility.c | 2 +- hw/virtio/vhost.c | 2 +- linux-user/arm/nwfpe/double_cpdo.c | 4 +- linux-user/arm/nwfpe/fpa11_cpdt.c | 4 +- linux-user/ppc/signal.c | 3 +- linux-user/syscall.c | 6 +-- net/net.c | 4 +- target/alpha/translate.c | 2 +- target/arm/crypto_helper.c | 2 +- target/arm/helper.c | 2 +- target/arm/kvm64.c | 4 +- target/arm/neon_helper.c | 2 +- target/arm/sve_helper.c | 4 +- target/arm/translate-sve.c | 6 +-- target/arm/translate-vfp.c | 2 +- target/arm/translate.c | 2 +- target/hppa/translate.c | 2 +- target/i386/tcg/translate.c | 2 +- target/mips/tcg/lmmi_helper.c | 2 +- target/mips/tcg/msa_helper.c | 54 ++++++++++++------------- target/ppc/arch_dump.c | 2 +- target/ppc/int_helper.c | 22 +++++----- target/ppc/kvm.c | 4 +- target/ppc/mem_helper.c | 2 +- target/riscv/vector_helper.c | 2 +- target/s390x/tcg/translate.c | 2 +- target/sparc/vis_helper.c | 4 +- tcg/tcg-op.c | 4 +- tcg/tcg.c | 12 +++--- tests/qtest/vhost-user-blk-test.c | 2 +- tests/qtest/virtio-blk-test.c | 2 +- ui/vdagent.c | 2 +- ui/vnc.c | 2 +- util/bitmap.c | 2 +- util/host-utils.c | 2 +- target/ppc/translate/vmx-impl.c.inc | 4 +- target/ppc/translate/vsx-impl.c.inc | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 +- target/s390x/tcg/translate_vx.c.inc | 2 +- tcg/aarch64/tcg-target.c.inc | 4 +- tcg/arm/tcg-target.c.inc | 4 +- tcg/mips/tcg-target.c.inc | 2 +- tcg/ppc/tcg-target.c.inc | 10 ++--- tcg/riscv/tcg-target.c.inc | 4 +- 85 files changed, 173 insertions(+), 173 deletions(-) diff --git a/meson.build b/meson.build index b1d2fcecbdcf..a97c6b0b5dbc 100644 --- a/meson.build +++ b/meson.build @@ -1574,7 +1574,6 @@ config_host_data.set('QEMU_VERSION_MICRO', meson.proj= ect_version().split('.')[2] =20 config_host_data.set_quoted('CONFIG_HOST_DSOSUF', host_dsosuf) config_host_data.set('HAVE_HOST_BLOCK_DEVICE', have_host_block_device) -config_host_data.set('HOST_WORDS_BIGENDIAN', host_machine.endian() =3D=3D = 'big') =20 have_coroutine_pool =3D get_option('coroutine_pool') if get_option('debug_stack_usage') and have_coroutine_pool diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index fc165031e868..404a530f7c2a 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -63,7 +63,7 @@ the ATOMIC_NAME macro, and redefined below. */ #if DATA_SIZE =3D=3D 1 # define END -#elif defined(HOST_WORDS_BIGENDIAN) +#elif HOST_BIG_ENDIAN # define END _be #else # define END _le @@ -196,7 +196,7 @@ GEN_ATOMIC_HELPER_FN(umax_fetch, MAX, DATA_TYPE, new) =20 /* Define reverse-host-endian atomic operations. Note that END is used within the ATOMIC_NAME macro. */ -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN # define END _le #else # define END _be diff --git a/audio/audio.h b/audio/audio.h index cbb10f4816e5..3d5ecdecd5c1 100644 --- a/audio/audio.h +++ b/audio/audio.h @@ -32,7 +32,7 @@ =20 typedef void (*audio_callback_fn) (void *opaque, int avail); =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define AUDIO_HOST_ENDIANNESS 1 #else #define AUDIO_HOST_ENDIANNESS 0 diff --git a/hw/display/pl110_template.h b/hw/display/pl110_template.h index 877419aa817a..00877853225d 100644 --- a/hw/display/pl110_template.h +++ b/hw/display/pl110_template.h @@ -15,18 +15,18 @@ =20 #if ORDER =3D=3D 0 #define NAME glue(lblp_, BORDER) -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define SWAP_WORDS 1 #endif #elif ORDER =3D=3D 1 #define NAME glue(bbbp_, BORDER) -#ifndef HOST_WORDS_BIGENDIAN +#if !HOST_BIG_ENDIAN #define SWAP_WORDS 1 #endif #else #define SWAP_PIXELS 1 #define NAME glue(lbbp_, BORDER) -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define SWAP_WORDS 1 #endif #endif diff --git a/hw/net/can/ctucan_core.h b/hw/net/can/ctucan_core.h index bbc09ae06785..608307a6310c 100644 --- a/hw/net/can/ctucan_core.h +++ b/hw/net/can/ctucan_core.h @@ -31,7 +31,7 @@ #include "exec/hwaddr.h" #include "net/can_emu.h" =20 -#ifndef HOST_WORDS_BIGENDIAN +#if !HOST_BIG_ENDIAN #define __LITTLE_ENDIAN_BITFIELD 1 #endif =20 diff --git a/hw/net/vmxnet3.h b/hw/net/vmxnet3.h index 5b3b76ba7ad1..bf4f6de74a07 100644 --- a/hw/net/vmxnet3.h +++ b/hw/net/vmxnet3.h @@ -35,7 +35,7 @@ #define __le32 uint32_t #define __le64 uint64_t =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN #define __BIG_ENDIAN_BITFIELD #else #endif @@ -800,7 +800,7 @@ struct Vmxnet3_DriverShared { #undef __le16 #undef __le32 #undef __le64 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN #undef __BIG_ENDIAN_BITFIELD #endif =20 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 84caf5c3d9f2..cbc8a19783e4 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -34,13 +34,13 @@ =20 /* some important defines: * - * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and + * HOST_BIG_ENDIAN : whether the host cpu is big endian and * otherwise little endian. * * TARGET_WORDS_BIGENDIAN : same for target cpu */ =20 -#if defined(HOST_WORDS_BIGENDIAN) !=3D defined(TARGET_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN !=3D defined(TARGET_WORDS_BIGENDIAN) #define BSWAP_NEEDED #endif =20 diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index de5f444b1931..3ea13d73a84d 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -34,7 +34,7 @@ enum device_endian { DEVICE_LITTLE_ENDIAN, }; =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN #else #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN diff --git a/include/exec/memop.h b/include/exec/memop.h index 2a885f3917b4..44f923ed4660 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -28,7 +28,7 @@ typedef enum MemOp { MO_SIGN =3D 0x08, /* Sign-extended, otherwise zero-extended. */ =20 MO_BSWAP =3D 0x10, /* Host reverse endian. */ -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN MO_LE =3D MO_BSWAP, MO_BE =3D 0, #else diff --git a/include/exec/memory.h b/include/exec/memory.h index 4d5997e6bbae..e40653f0d19e 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -2931,7 +2931,7 @@ static inline MemOp devend_memop(enum device_endian e= nd) QEMU_BUILD_BUG_ON(DEVICE_HOST_ENDIAN !=3D DEVICE_LITTLE_ENDIAN && DEVICE_HOST_ENDIAN !=3D DEVICE_BIG_ENDIAN); =20 -#if defined(HOST_WORDS_BIGENDIAN) !=3D defined(TARGET_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN !=3D defined(TARGET_WORDS_BIGENDIAN) /* Swap if non-host endianness or native (target) endianness */ return (end =3D=3D DEVICE_HOST_ENDIAN) ? 0 : MO_BSWAP; #else diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 8abd9ab4ec9c..7a6ea881d83e 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -103,7 +103,7 @@ typedef struct { #define make_floatx80(exp, mant) ((floatx80) { mant, exp }) #define make_floatx80_init(exp, mant) { .low =3D mant, .high =3D exp } typedef struct { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN uint64_t high, low; #else uint64_t low, high; diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index f7b6f6e2b021..d3e8ef33d3a1 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -180,7 +180,7 @@ struct CPUClass { typedef union IcountDecr { uint32_t u32; struct { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN uint16_t high; uint16_t low; #else diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 41783ee46d5e..ecea17c26cc4 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -145,7 +145,7 @@ enum { /* Interrupt Remapping Table Entry Definition */ union VTD_IR_TableEntry { struct { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN uint32_t __reserved_1:8; /* Reserved 1 */ uint32_t vector:8; /* Interrupt Vector */ uint32_t irte_mode:1; /* IRTE Mode */ @@ -172,7 +172,7 @@ union VTD_IR_TableEntry { #endif uint32_t dest_id; /* Destination ID */ uint16_t source_id; /* Source-ID */ -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN uint64_t __reserved_2:44; /* Reserved 2 */ uint64_t sid_vtype:2; /* Source-ID Validation Type */ uint64_t sid_q:2; /* Source-ID Qualifier */ @@ -191,7 +191,7 @@ union VTD_IR_TableEntry { /* Programming format for MSI/MSI-X addresses */ union VTD_IR_MSIAddress { struct { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN uint32_t __head:12; /* Should always be: 0x0fee */ uint32_t index_l:15; /* Interrupt index bit 14-0 */ uint32_t int_mode:1; /* Interrupt format */ diff --git a/include/hw/i386/x86-iommu.h b/include/hw/i386/x86-iommu.h index 5ba0c056d60c..7637edb430a4 100644 --- a/include/hw/i386/x86-iommu.h +++ b/include/hw/i386/x86-iommu.h @@ -87,7 +87,7 @@ struct X86IOMMUIrq { struct X86IOMMU_MSIMessage { union { struct { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN uint32_t __addr_head:12; /* 0xfee */ uint32_t dest:8; uint32_t __reserved:8; @@ -108,7 +108,7 @@ struct X86IOMMU_MSIMessage { }; union { struct { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN uint16_t trigger_mode:1; uint16_t level:1; uint16_t __resved:3; diff --git a/include/hw/virtio/virtio-access.h b/include/hw/virtio/virtio-a= ccess.h index 6818a23a2d35..90cbb77782b5 100644 --- a/include/hw/virtio/virtio-access.h +++ b/include/hw/virtio/virtio-access.h @@ -149,7 +149,7 @@ static inline uint64_t virtio_ldq_p(VirtIODevice *vdev,= const void *ptr) =20 static inline uint16_t virtio_tswap16(VirtIODevice *vdev, uint16_t s) { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN return virtio_access_is_big_endian(vdev) ? s : bswap16(s); #else return virtio_access_is_big_endian(vdev) ? bswap16(s) : s; @@ -215,7 +215,7 @@ static inline void virtio_tswap16s(VirtIODevice *vdev, = uint16_t *s) =20 static inline uint32_t virtio_tswap32(VirtIODevice *vdev, uint32_t s) { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN return virtio_access_is_big_endian(vdev) ? s : bswap32(s); #else return virtio_access_is_big_endian(vdev) ? bswap32(s) : s; @@ -229,7 +229,7 @@ static inline void virtio_tswap32s(VirtIODevice *vdev, = uint32_t *s) =20 static inline uint64_t virtio_tswap64(VirtIODevice *vdev, uint64_t s) { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN return virtio_access_is_big_endian(vdev) ? s : bswap64(s); #else return virtio_access_is_big_endian(vdev) ? bswap64(s) : s; diff --git a/include/hw/virtio/virtio-gpu-bswap.h b/include/hw/virtio/virti= o-gpu-bswap.h index 5faac0d8d5f3..912410848597 100644 --- a/include/hw/virtio/virtio-gpu-bswap.h +++ b/include/hw/virtio/virtio-gpu-bswap.h @@ -29,7 +29,7 @@ virtio_gpu_ctrl_hdr_bswap(struct virtio_gpu_ctrl_hdr *hdr) static inline void virtio_gpu_bswap_32(void *ptr, size_t size) { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN =20 size_t i; struct virtio_gpu_ctrl_hdr *hdr =3D (struct virtio_gpu_ctrl_hdr *) ptr; diff --git a/include/libdecnumber/dconfig.h b/include/libdecnumber/dconfig.h index 0f7dccef1f4e..2bc0ba7f1444 100644 --- a/include/libdecnumber/dconfig.h +++ b/include/libdecnumber/dconfig.h @@ -28,7 +28,7 @@ 02110-1301, USA. */ =20 =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN #define WORDS_BIGENDIAN 1 #else #define WORDS_BIGENDIAN 0 diff --git a/include/net/eth.h b/include/net/eth.h index 7767ae880ecc..6e699b0d7a4a 100644 --- a/include/net/eth.h +++ b/include/net/eth.h @@ -159,7 +159,7 @@ struct tcp_hdr { u_short th_dport; /* destination port */ uint32_t th_seq; /* sequence number */ uint32_t th_ack; /* acknowledgment number */ -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN u_char th_off : 4, /* data offset */ th_x2:4; /* (unused) */ #else diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h index 2d3bb8bbedda..9dff7c7dbbc9 100644 --- a/include/qemu/bswap.h +++ b/include/qemu/bswap.h @@ -84,7 +84,7 @@ static inline void bswap64s(uint64_t *s) *s =3D bswap64(*s); } =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN #define be_bswap(v, size) (v) #define le_bswap(v, size) glue(bswap, size)(v) #define be_bswaps(v, size) @@ -188,7 +188,7 @@ CPU_CONVERT(le, 64, uint64_t) * a compile-time constant if you pass in a constant. So this can be * used to initialize static variables. */ -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN # define const_le32(_x) \ ((((_x) & 0x000000ffU) << 24) | \ (((_x) & 0x0000ff00U) << 8) | \ @@ -211,7 +211,7 @@ typedef union { =20 typedef union { float64 d; -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN struct { uint32_t upper; uint32_t lower; @@ -235,7 +235,7 @@ typedef union { =20 typedef union { float128 q; -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN struct { uint32_t upmost; uint32_t upper; diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index eb29b72c14d7..8c7da00c56ba 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -7,6 +7,8 @@ #ifndef COMPILER_H #define COMPILER_H =20 +#define HOST_BIG_ENDIAN (__BYTE_ORDER__ =3D=3D __ORDER_BIG_ENDIAN__) + #if defined __clang_analyzer__ || defined __COVERITY__ #define QEMU_STATIC_ANALYSIS 1 #endif diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index ca979dc6ccde..f19bd2910563 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host-utils.h @@ -88,7 +88,7 @@ static inline uint64_t muldiv64(uint64_t a, uint32_t b, u= int32_t c) union { uint64_t ll; struct { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN uint32_t high, low; #else uint32_t low, high; diff --git a/include/qemu/int128.h b/include/qemu/int128.h index 2c4064256cdf..37e07fd6dd92 100644 --- a/include/qemu/int128.h +++ b/include/qemu/int128.h @@ -205,7 +205,7 @@ typedef struct Int128 Int128; * a union with other integer types). */ struct Int128 { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN int64_t hi; uint64_t lo; #else diff --git a/include/ui/qemu-pixman.h b/include/ui/qemu-pixman.h index 806ddcd7cdab..0c775604d173 100644 --- a/include/ui/qemu-pixman.h +++ b/include/ui/qemu-pixman.h @@ -19,7 +19,7 @@ * feeding libjpeg / libpng and writing screenshots. */ =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN # define PIXMAN_BE_r8g8b8 PIXMAN_r8g8b8 # define PIXMAN_BE_x8r8g8b8 PIXMAN_x8r8g8b8 # define PIXMAN_BE_a8r8g8b8 PIXMAN_a8r8g8b8 diff --git a/net/util.h b/net/util.h index 358185fd5034..288312979f09 100644 --- a/net/util.h +++ b/net/util.h @@ -30,7 +30,7 @@ * Structure of an internet header, naked of options. */ struct ip { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN uint8_t ip_v:4, /* version */ ip_hl:4; /* header length */ #else diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6a4d50e8219..d007cedb2802 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -95,7 +95,7 @@ enum { * therefore useful to be able to pass TCG the offset of the least * significant half of a uint64_t struct member. */ -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) #define offsetofhigh32(S, M) offsetof(S, M) #else @@ -380,7 +380,7 @@ typedef struct CPUARMState { union { /* Fault address registers. */ struct { uint64_t _unused_far0; -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN uint32_t ifar_ns; uint32_t dfar_ns; uint32_t ifar_s; @@ -417,7 +417,7 @@ typedef struct CPUARMState { uint64_t c9_pminten; /* perf monitor interrupt enables */ union { /* Memory attribute redirection */ struct { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN uint64_t _unused_mair_0; uint32_t mair1_ns; uint32_t mair0_ns; @@ -1089,7 +1089,7 @@ void aarch64_add_pauth_properties(Object *obj); */ static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN int i; =20 for (i =3D 0; i < nr; ++i) { diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 58f50abca469..38884158aab3 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -71,7 +71,7 @@ static inline int vec_reg_offset(DisasContext *s, int reg= no, { int element_size =3D 1 << size; int offs =3D element * element_size; -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN /* This is complicated slightly because vfp.zregs[n].d[0] is * still the lowest and vfp.zregs[n].d[15] the highest of the * 256 byte vector, even on big endian systems. diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h index 2a3355829068..fb43a2380e21 100644 --- a/target/arm/vec_internal.h +++ b/target/arm/vec_internal.h @@ -29,7 +29,7 @@ * The H1_ macros are used when performing byte arithmetic and then * casting the final pointer to a type of size N. */ -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define H1(x) ((x) ^ 7) #define H1_2(x) ((x) ^ 6) #define H1_4(x) ((x) ^ 4) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e69ab5dd783c..f4faa599a46e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1226,7 +1226,7 @@ typedef struct BNDCSReg { #define BNDCFG_BNDPRESERVE 2ULL #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define ZMM_B(n) _b_ZMMReg[63 - (n)] #define ZMM_W(n) _w_ZMMReg[31 - (n)] #define ZMM_L(n) _l_ZMMReg[15 - (n)] diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 56b1cbd091df..1032d8f8f770 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -35,7 +35,7 @@ union fpr_t { *define FP_ENDIAN_IDX to access the same location * in the fpr_t union regardless of the host endianness */ -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN # define FP_ENDIAN_IDX 1 #else # define FP_ENDIAN_IDX 0 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 8355ed2cf6b6..035885d2f43c 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2637,7 +2637,7 @@ static inline bool lsw_reg_in_range(int start, int nr= egs, int rx) } =20 /* Accessors for FP, VMX and VSX registers */ -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN #define VsrB(i) u8[i] #define VsrSB(i) s8[i] #define VsrH(i) u16[i] diff --git a/target/s390x/tcg/vec.h b/target/s390x/tcg/vec.h index a6e361869b2e..8d095efcfc6f 100644 --- a/target/s390x/tcg/vec.h +++ b/target/s390x/tcg/vec.h @@ -38,7 +38,7 @@ typedef union S390Vector { * W: [ 1][ 0] - [ 3][ 2] * DW: [ 0] - [ 1] */ -#ifndef HOST_WORDS_BIGENDIAN +#if !HOST_BIG_ENDIAN #define H1(x) ((x) ^ 7) #define H2(x) ((x) ^ 3) #define H4(x) ((x) ^ 1) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 5b4a22816ff8..837cb9958ff1 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -494,7 +494,7 @@ typedef struct XtensaConfigList { struct XtensaConfigList *next; } XtensaConfigList; =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN enum { FP_F32_HIGH, FP_F32_LOW, diff --git a/tests/fp/platform.h b/tests/fp/platform.h index c20ba70baa07..6c72ad0cd05b 100644 --- a/tests/fp/platform.h +++ b/tests/fp/platform.h @@ -29,9 +29,9 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE O= F THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "config-host.h" +#include "qemu/compiler.h" =20 -#ifndef HOST_WORDS_BIGENDIAN +#if !HOST_BIG_ENDIAN #define LITTLEENDIAN 1 /* otherwise do not define it */ #endif diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 0e66ebb49717..fd39de984d7c 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -1202,8 +1202,8 @@ void kvm_hwpoison_page_add(ram_addr_t ram_addr) =20 static uint32_t adjust_ioeventfd_endianness(uint32_t val, uint32_t size) { -#if defined(HOST_WORDS_BIGENDIAN) !=3D defined(TARGET_WORDS_BIGENDIAN) - /* The kernel expects ioeventfd values in HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN !=3D defined(TARGET_WORDS_BIGENDIAN) + /* The kernel expects ioeventfd values in HOST_BIG_ENDIAN * endianness, but the memory core hands them in target endianness. * For example, PPC is always treated as big-endian even if running * on KVM and on PPC64LE. Correct here. diff --git a/audio/dbusaudio.c b/audio/dbusaudio.c index f178b47deec1..a3d656d3b017 100644 --- a/audio/dbusaudio.c +++ b/audio/dbusaudio.c @@ -122,7 +122,7 @@ static size_t dbus_put_buffer_out(HWVoiceOut *hw, void = *buf, size_t size) return size; } =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define AUDIO_HOST_BE TRUE #else #define AUDIO_HOST_BE FALSE diff --git a/disas.c b/disas.c index 3dab4482d1a1..2d2565ac5774 100644 --- a/disas.c +++ b/disas.c @@ -144,7 +144,7 @@ static void initialize_debug_host(CPUDebug *s) =20 s->info.read_memory_func =3D host_read_memory; s->info.print_address_func =3D host_print_address; -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN s->info.endian =3D BFD_ENDIAN_BIG; #else s->info.endian =3D BFD_ENDIAN_LITTLE; diff --git a/hw/core/loader.c b/hw/core/loader.c index 19edb928e999..10df03d110fe 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -474,7 +474,7 @@ ssize_t load_elf_ram_sym(const char *filename, ret =3D ELF_LOAD_NOT_ELF; goto fail; } -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN data_order =3D ELFDATA2MSB; #else data_order =3D ELFDATA2LSB; @@ -511,7 +511,7 @@ ssize_t load_elf_ram_sym(const char *filename, =20 static void bswap_uboot_header(uboot_image_header_t *hdr) { -#ifndef HOST_WORDS_BIGENDIAN +#if !HOST_BIG_ENDIAN bswap32s(&hdr->ih_magic); bswap32s(&hdr->ih_hcrc); bswap32s(&hdr->ih_time); diff --git a/hw/display/artist.c b/hw/display/artist.c index 1d877998b9ae..69a8f9eea8ba 100644 --- a/hw/display/artist.c +++ b/hw/display/artist.c @@ -26,7 +26,7 @@ #define TYPE_ARTIST "artist" OBJECT_DECLARE_SIMPLE_TYPE(ARTISTState, ARTIST) =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define ROP8OFF(_i) (3 - (_i)) #else #define ROP8OFF @@ -712,7 +712,7 @@ static void combine_write_reg(hwaddr addr, uint64_t val= , int size, void *out) * FIXME: is there a qemu helper for this? */ =20 -#ifndef HOST_WORDS_BIGENDIAN +#if !HOST_BIG_ENDIAN addr ^=3D 3; #endif =20 @@ -1087,7 +1087,7 @@ static uint64_t combine_read_reg(hwaddr addr, int siz= e, void *in) * FIXME: is there a qemu helper for this? */ =20 -#ifndef HOST_WORDS_BIGENDIAN +#if !HOST_BIG_ENDIAN addr ^=3D 3; #endif =20 diff --git a/hw/display/pxa2xx_lcd.c b/hw/display/pxa2xx_lcd.c index 2887ce496b47..6ccc1ad9d337 100644 --- a/hw/display/pxa2xx_lcd.c +++ b/hw/display/pxa2xx_lcd.c @@ -199,7 +199,7 @@ typedef struct QEMU_PACKED { SKIP_PIXEL(to); \ } while (0) =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN # define SWAP_WORDS 1 #endif =20 diff --git a/hw/display/vga.c b/hw/display/vga.c index 9d1f66af402e..99f88c61cbe7 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -94,19 +94,19 @@ const uint8_t gr_mask[16] =3D { (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \ (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) )) =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define PAT(x) cbswap_32(x) #else #define PAT(x) (x) #endif =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define BIG 1 #else #define BIG 0 #endif =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff) #else #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff) @@ -133,7 +133,7 @@ static const uint32_t mask16[16] =3D { =20 #undef PAT =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define PAT(x) (x) #else #define PAT(x) cbswap_32(x) @@ -1296,7 +1296,7 @@ static void vga_draw_text(VGACommonState *s, int full= _update) if (cx > cx_max) cx_max =3D cx; *ch_attr_ptr =3D ch_attr; -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN ch =3D ch_attr >> 8; cattr =3D ch_attr & 0xff; #else @@ -1477,7 +1477,7 @@ static void vga_draw_graphic(VGACommonState *s, int f= ull_update) vga_draw_line_func *vga_draw_line =3D NULL; bool share_surface, force_shadow =3D false; pixman_format_code_t format; -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN bool byteswap =3D !s->big_endian_fb; #else bool byteswap =3D s->big_endian_fb; diff --git a/hw/display/virtio-gpu-gl.c b/hw/display/virtio-gpu-gl.c index 6cc4313b1af2..0bca8877035e 100644 --- a/hw/display/virtio-gpu-gl.c +++ b/hw/display/virtio-gpu-gl.c @@ -108,7 +108,7 @@ static void virtio_gpu_gl_device_realize(DeviceState *q= dev, Error **errp) { VirtIOGPU *g =3D VIRTIO_GPU(qdev); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN error_setg(errp, "virgl is not supported on bigendian platforms"); return; #endif diff --git a/hw/s390x/event-facility.c b/hw/s390x/event-facility.c index 6fa47b889ca4..faa51aa4c70d 100644 --- a/hw/s390x/event-facility.c +++ b/hw/s390x/event-facility.c @@ -28,7 +28,7 @@ typedef struct SCLPEventsBus { } SCLPEventsBus; =20 /* we need to save 32 bit chunks for compatibility */ -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define RECV_MASK_LOWER 1 #define RECV_MASK_UPPER 0 #else /* little endian host */ diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c index 7b03efccecbb..24ee74837ed2 100644 --- a/hw/virtio/vhost.c +++ b/hw/virtio/vhost.c @@ -989,7 +989,7 @@ static inline bool vhost_needs_vring_endian(VirtIODevic= e *vdev) if (virtio_vdev_has_feature(vdev, VIRTIO_F_VERSION_1)) { return false; } -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN return vdev->device_endian =3D=3D VIRTIO_DEVICE_ENDIAN_LITTLE; #else return vdev->device_endian =3D=3D VIRTIO_DEVICE_ENDIAN_BIG; diff --git a/linux-user/arm/nwfpe/double_cpdo.c b/linux-user/arm/nwfpe/doub= le_cpdo.c index 1cef380852c9..d45ece2e2fe7 100644 --- a/linux-user/arm/nwfpe/double_cpdo.c +++ b/linux-user/arm/nwfpe/double_cpdo.c @@ -150,7 +150,7 @@ unsigned int DoubleCPDO(const unsigned int opcode) case MNF_CODE: { unsigned int *p =3D (unsigned int*)&rFm; -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN p[0] ^=3D 0x80000000; #else p[1] ^=3D 0x80000000; @@ -162,7 +162,7 @@ unsigned int DoubleCPDO(const unsigned int opcode) case ABS_CODE: { unsigned int *p =3D (unsigned int*)&rFm; -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN p[0] &=3D 0x7fffffff; #else p[1] &=3D 0x7fffffff; diff --git a/linux-user/arm/nwfpe/fpa11_cpdt.c b/linux-user/arm/nwfpe/fpa11= _cpdt.c index c32b0c2faac0..fee525937c55 100644 --- a/linux-user/arm/nwfpe/fpa11_cpdt.c +++ b/linux-user/arm/nwfpe/fpa11_cpdt.c @@ -44,7 +44,7 @@ void loadDouble(const unsigned int Fn, target_ulong addr) unsigned int *p; p =3D (unsigned int*)&fpa11->fpreg[Fn].fDouble; fpa11->fType[Fn] =3D typeDouble; -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN /* FIXME - handle failure of get_user() */ get_user_u32(p[0], addr); /* sign & exponent */ get_user_u32(p[1], addr + 4); @@ -147,7 +147,7 @@ void storeDouble(const unsigned int Fn, target_ulong ad= dr) default: val =3D fpa11->fpreg[Fn].fDouble; } /* FIXME - handle put_user() failures */ -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN put_user_u32(p[0], addr); /* msw */ put_user_u32(p[1], addr + 4); /* lsw */ #else diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c index ec0b9c0df3da..2550b8f8c069 100644 --- a/linux-user/ppc/signal.c +++ b/linux-user/ppc/signal.c @@ -215,8 +215,7 @@ static target_ulong get_sigframe(struct target_sigactio= n *ka, return (oldsp - frame_size) & ~0xFUL; } =20 -#if ((defined(TARGET_WORDS_BIGENDIAN) && defined(HOST_WORDS_BIGENDIAN)) ||= \ - (!defined(HOST_WORDS_BIGENDIAN) && !defined(TARGET_WORDS_BIGENDIAN))) +#if defined(TARGET_WORDS_BIGENDIAN) =3D=3D HOST_BIG_ENDIAN #define PPC_VEC_HI 0 #define PPC_VEC_LO 1 #else diff --git a/linux-user/syscall.c b/linux-user/syscall.c index b9b18a7eaffb..4de45ec6222e 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -8152,7 +8152,7 @@ static int is_proc_myself(const char *filename, const= char *entry) return 0; } =20 -#if defined(HOST_WORDS_BIGENDIAN) !=3D defined(TARGET_WORDS_BIGENDIAN) || \ +#if HOST_BIG_ENDIAN !=3D defined(TARGET_WORDS_BIGENDIAN) || \ defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA) static int is_proc(const char *filename, const char *entry) { @@ -8160,7 +8160,7 @@ static int is_proc(const char *filename, const char *= entry) } #endif =20 -#if defined(HOST_WORDS_BIGENDIAN) !=3D defined(TARGET_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN !=3D defined(TARGET_WORDS_BIGENDIAN) static int open_net_route(void *cpu_env, int fd) { FILE *fp; @@ -8246,7 +8246,7 @@ static int do_openat(void *cpu_env, int dirfd, const = char *pathname, int flags, { "stat", open_self_stat, is_proc_myself }, { "auxv", open_self_auxv, is_proc_myself }, { "cmdline", open_self_cmdline, is_proc_myself }, -#if defined(HOST_WORDS_BIGENDIAN) !=3D defined(TARGET_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN !=3D defined(TARGET_WORDS_BIGENDIAN) { "/proc/net/route", open_net_route, is_proc }, #endif #if defined(TARGET_SPARC) || defined(TARGET_HPPA) diff --git a/net/net.c b/net/net.c index f0d14dbfc1f0..9f17ab204422 100644 --- a/net/net.c +++ b/net/net.c @@ -524,7 +524,7 @@ void qemu_set_vnet_hdr_len(NetClientState *nc, int len) =20 int qemu_set_vnet_le(NetClientState *nc, bool is_le) { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN if (!nc || !nc->info->set_vnet_le) { return -ENOSYS; } @@ -537,7 +537,7 @@ int qemu_set_vnet_le(NetClientState *nc, bool is_le) =20 int qemu_set_vnet_be(NetClientState *nc, bool is_be) { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN return 0; #else if (!nc || !nc->info->set_vnet_be) { diff --git a/target/alpha/translate.c b/target/alpha/translate.c index ca78a0faed0f..f04bd01210a5 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -236,7 +236,7 @@ static TCGv dest_fpr(DisasContext *ctx, unsigned reg) static int get_flag_ofs(unsigned shift) { int ofs =3D offsetof(CPUAlphaState, flags); -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN ofs +=3D 3 - (shift / 8); #else ofs +=3D shift / 8; diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c index 28a84c2dbdb6..4c8fd34aecb0 100644 --- a/target/arm/crypto_helper.c +++ b/target/arm/crypto_helper.c @@ -23,7 +23,7 @@ union CRYPTO_STATE { uint64_t l[2]; }; =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define CR_ST_BYTE(state, i) ((state).bytes[(15 - (i)) ^ 8]) #define CR_ST_WORD(state, i) ((state).words[(3 - (i)) ^ 2]) #else diff --git a/target/arm/helper.c b/target/arm/helper.c index b5f80988c900..242d29f90ed9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8617,7 +8617,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, r2->cp =3D 15; } =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN if (r2->fieldoffset) { r2->fieldoffset +=3D sizeof(uint32_t); } diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 71c3ca697173..e8d0d5e69d90 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1011,7 +1011,7 @@ static int kvm_arch_put_fpsimd(CPUState *cs) =20 for (i =3D 0; i < 32; i++) { uint64_t *q =3D aa64_vfp_qreg(env, i); -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN uint64_t fp_val[2] =3D { q[1], q[0] }; reg.addr =3D (uintptr_t)fp_val; #else @@ -1230,7 +1230,7 @@ static int kvm_arch_get_fpsimd(CPUState *cs) if (ret) { return ret; } else { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN uint64_t t; t =3D q[0], q[0] =3D q[1], q[1] =3D t; #endif diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index 338b9189d5b2..bc6c4a54e9d9 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -23,7 +23,7 @@ typedef struct \ { \ type v1; \ } neon_##name; -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define NEON_TYPE2(name, type) \ typedef struct \ { \ diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 07be55b7e1ad..d1ea26f1f774 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -2802,7 +2802,7 @@ static void swap_memmove(void *vd, void *vs, size_t n) uintptr_t o =3D (d | s | n) & 7; size_t i; =20 -#ifndef HOST_WORDS_BIGENDIAN +#if !HOST_BIG_ENDIAN o =3D 0; #endif switch (o) { @@ -2864,7 +2864,7 @@ static void swap_memzero(void *vd, size_t n) return; } =20 -#ifndef HOST_WORDS_BIGENDIAN +#if !HOST_BIG_ENDIAN o =3D 0; #endif switch (o) { diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 33ca1bcfac38..72132a10323b 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -2872,7 +2872,7 @@ static TCGv_i64 load_last_active(DisasContext *s, TCG= v_i32 last, * The final adjustment for the vector register base * is added via constant offset to the load. */ -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN /* Adjust for element ordering. See vec_reg_offset. */ if (esz < 3) { tcg_gen_xori_i32(last, last, 8 - (1 << esz)); @@ -5711,7 +5711,7 @@ static void do_ldrq(DisasContext *s, int zt, int pg, = TCGv_i64 addr, int dtype) * for this load operation. */ TCGv_i64 tmp =3D tcg_temp_new_i64(); -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN poff +=3D 6; #endif tcg_gen_ld16u_i64(tmp, cpu_env, poff); @@ -5790,7 +5790,7 @@ static void do_ldro(DisasContext *s, int zt, int pg, = TCGv_i64 addr, int dtype) * for this load operation. */ TCGv_i64 tmp =3D tcg_temp_new_i64(); -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN poff +=3D 4; #endif tcg_gen_ld32u_i64(tmp, cpu_env, poff); diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 17f796e32a33..6a95a67a69e5 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -93,7 +93,7 @@ uint64_t vfp_expand_imm(int size, uint8_t imm8) static inline long vfp_f16_offset(unsigned reg, bool top) { long offs =3D vfp_reg_offset(false, reg); -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN if (!top) { offs +=3D 2; } diff --git a/target/arm/translate.c b/target/arm/translate.c index bf2196b9e24c..e8dfa71364db 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1158,7 +1158,7 @@ long neon_element_offset(int reg, int element, MemOp = memop) { int element_size =3D 1 << (memop & MO_SIZE); int ofs =3D element * element_size; -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN /* * Calculate the offset assuming fully little-endian, * then XOR to account for the order of the 8-byte units. diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5c0b1eb274aa..0b83ee4d9856 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -566,7 +566,7 @@ static void save_gpr(DisasContext *ctx, unsigned reg, T= CGv_reg t) } } =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN # define HI_OFS 0 # define LO_OFS 4 #else diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 2a94d3374252..5649bba9a88d 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -359,7 +359,7 @@ static void gen_update_cc_op(DisasContext *s) =20 #endif /* !TARGET_X86_64 */ =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN #define REG_B_OFFSET (sizeof(target_ulong) - 1) #define REG_H_OFFSET (sizeof(target_ulong) - 2) #define REG_W_OFFSET (sizeof(target_ulong) - 2) diff --git a/target/mips/tcg/lmmi_helper.c b/target/mips/tcg/lmmi_helper.c index abeb7736aeb2..2c8732525ce3 100644 --- a/target/mips/tcg/lmmi_helper.c +++ b/target/mips/tcg/lmmi_helper.c @@ -37,7 +37,7 @@ typedef union { } LMIValue; =20 /* Some byte ordering issues can be mitigated by XORing in the following. = */ -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN # define BYTE_ORDER_XOR(N) N #else # define BYTE_ORDER_XOR(N) 0 diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 5667b1f0a15c..389c42e4baa3 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -4146,7 +4146,7 @@ void helper_msa_ilvev_b(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->b[8] =3D pws->b[9]; pwd->b[9] =3D pwt->b[9]; pwd->b[10] =3D pws->b[11]; @@ -4190,7 +4190,7 @@ void helper_msa_ilvev_h(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->h[4] =3D pws->h[5]; pwd->h[5] =3D pwt->h[5]; pwd->h[6] =3D pws->h[7]; @@ -4218,7 +4218,7 @@ void helper_msa_ilvev_w(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->w[2] =3D pws->w[3]; pwd->w[3] =3D pwt->w[3]; pwd->w[0] =3D pws->w[1]; @@ -4250,7 +4250,7 @@ void helper_msa_ilvod_b(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->b[7] =3D pwt->b[6]; pwd->b[6] =3D pws->b[6]; pwd->b[5] =3D pwt->b[4]; @@ -4294,7 +4294,7 @@ void helper_msa_ilvod_h(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->h[3] =3D pwt->h[2]; pwd->h[2] =3D pws->h[2]; pwd->h[1] =3D pwt->h[0]; @@ -4322,7 +4322,7 @@ void helper_msa_ilvod_w(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->w[1] =3D pwt->w[0]; pwd->w[0] =3D pws->w[0]; pwd->w[3] =3D pwt->w[2]; @@ -4354,7 +4354,7 @@ void helper_msa_ilvl_b(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->b[7] =3D pwt->b[15]; pwd->b[6] =3D pws->b[15]; pwd->b[5] =3D pwt->b[14]; @@ -4398,7 +4398,7 @@ void helper_msa_ilvl_h(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->h[3] =3D pwt->h[7]; pwd->h[2] =3D pws->h[7]; pwd->h[1] =3D pwt->h[6]; @@ -4426,7 +4426,7 @@ void helper_msa_ilvl_w(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->w[1] =3D pwt->w[3]; pwd->w[0] =3D pws->w[3]; pwd->w[3] =3D pwt->w[2]; @@ -4458,7 +4458,7 @@ void helper_msa_ilvr_b(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->b[8] =3D pws->b[0]; pwd->b[9] =3D pwt->b[0]; pwd->b[10] =3D pws->b[1]; @@ -4502,7 +4502,7 @@ void helper_msa_ilvr_h(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->h[4] =3D pws->h[0]; pwd->h[5] =3D pwt->h[0]; pwd->h[6] =3D pws->h[1]; @@ -4530,7 +4530,7 @@ void helper_msa_ilvr_w(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->w[2] =3D pws->w[0]; pwd->w[3] =3D pwt->w[0]; pwd->w[0] =3D pws->w[1]; @@ -4661,7 +4661,7 @@ void helper_msa_pckev_b(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->b[8] =3D pws->b[9]; pwd->b[10] =3D pws->b[13]; pwd->b[12] =3D pws->b[1]; @@ -4705,7 +4705,7 @@ void helper_msa_pckev_h(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->h[4] =3D pws->h[5]; pwd->h[6] =3D pws->h[1]; pwd->h[0] =3D pwt->h[5]; @@ -4733,7 +4733,7 @@ void helper_msa_pckev_w(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->w[2] =3D pws->w[3]; pwd->w[0] =3D pwt->w[3]; pwd->w[3] =3D pws->w[1]; @@ -4765,7 +4765,7 @@ void helper_msa_pckod_b(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->b[7] =3D pwt->b[6]; pwd->b[5] =3D pwt->b[2]; pwd->b[3] =3D pwt->b[14]; @@ -4810,7 +4810,7 @@ void helper_msa_pckod_h(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->h[3] =3D pwt->h[2]; pwd->h[1] =3D pwt->h[6]; pwd->h[7] =3D pws->h[2]; @@ -4838,7 +4838,7 @@ void helper_msa_pckod_w(CPUMIPSState *env, wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN pwd->w[1] =3D pwt->w[0]; pwd->w[3] =3D pws->w[0]; pwd->w[0] =3D pwt->w[2]; @@ -5926,7 +5926,7 @@ void helper_msa_copy_s_b(CPUMIPSState *env, uint32_t = rd, uint32_t ws, uint32_t n) { n %=3D 16; -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN if (n < 8) { n =3D 8 - n - 1; } else { @@ -5940,7 +5940,7 @@ void helper_msa_copy_s_h(CPUMIPSState *env, uint32_t = rd, uint32_t ws, uint32_t n) { n %=3D 8; -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN if (n < 4) { n =3D 4 - n - 1; } else { @@ -5954,7 +5954,7 @@ void helper_msa_copy_s_w(CPUMIPSState *env, uint32_t = rd, uint32_t ws, uint32_t n) { n %=3D 4; -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN if (n < 2) { n =3D 2 - n - 1; } else { @@ -5975,7 +5975,7 @@ void helper_msa_copy_u_b(CPUMIPSState *env, uint32_t = rd, uint32_t ws, uint32_t n) { n %=3D 16; -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN if (n < 8) { n =3D 8 - n - 1; } else { @@ -5989,7 +5989,7 @@ void helper_msa_copy_u_h(CPUMIPSState *env, uint32_t = rd, uint32_t ws, uint32_t n) { n %=3D 8; -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN if (n < 4) { n =3D 4 - n - 1; } else { @@ -6003,7 +6003,7 @@ void helper_msa_copy_u_w(CPUMIPSState *env, uint32_t = rd, uint32_t ws, uint32_t n) { n %=3D 4; -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN if (n < 2) { n =3D 2 - n - 1; } else { @@ -6019,7 +6019,7 @@ void helper_msa_insert_b(CPUMIPSState *env, uint32_t = wd, wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); target_ulong rs =3D env->active_tc.gpr[rs_num]; n %=3D 16; -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN if (n < 8) { n =3D 8 - n - 1; } else { @@ -6035,7 +6035,7 @@ void helper_msa_insert_h(CPUMIPSState *env, uint32_t = wd, wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); target_ulong rs =3D env->active_tc.gpr[rs_num]; n %=3D 8; -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN if (n < 4) { n =3D 4 - n - 1; } else { @@ -6051,7 +6051,7 @@ void helper_msa_insert_w(CPUMIPSState *env, uint32_t = wd, wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); target_ulong rs =3D env->active_tc.gpr[rs_num]; n %=3D 4; -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN if (n < 2) { n =3D 2 - n - 1; } else { diff --git a/target/ppc/arch_dump.c b/target/ppc/arch_dump.c index 993740897d83..1139cead9fed 100644 --- a/target/ppc/arch_dump.c +++ b/target/ppc/arch_dump.c @@ -161,7 +161,7 @@ static void ppc_write_elf_vmxregset(NoteFuncArg *arg, P= owerPCCPU *cpu) bool needs_byteswap; ppc_avr_t *avr =3D cpu_avr_ptr(&cpu->env, i); =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN needs_byteswap =3D s->dump_info.d_endian =3D=3D ELFDATA2LSB; #else needs_byteswap =3D s->dump_info.d_endian =3D=3D ELFDATA2MSB; diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index d1b12788b215..4e5bcf7a7396 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -424,7 +424,7 @@ uint64_t helper_PEXTD(uint64_t src, uint64_t mask) =20 /*************************************************************************= ****/ /* Altivec extension helpers */ -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN #define VECTOR_FOR_INORDER_I(index, element) \ for (index =3D 0; index < ARRAY_SIZE(r->element); index++) #else @@ -1170,7 +1170,7 @@ void helper_vpermr(CPUPPCState *env, ppc_avr_t *r, pp= c_avr_t *a, ppc_avr_t *b, *r =3D result; } =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN #define VBPERMQ_INDEX(avr, i) ((avr)->u8[(i)]) #define VBPERMD_INDEX(i) (i) #define VBPERMQ_DW(index) (((index) & 0x40) !=3D 0) @@ -1291,7 +1291,7 @@ void helper_vpmsumd(ppc_avr_t *r, ppc_avr_t *a, ppc_a= vr_t *b) } =20 =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN #define PKBIG 1 #else #define PKBIG 0 @@ -1300,7 +1300,7 @@ void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_avr= _t *b) { int i, j; ppc_avr_t result; -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN const ppc_avr_t *x[2] =3D { a, b }; #else const ppc_avr_t *x[2] =3D { b, a }; @@ -1516,7 +1516,7 @@ void helper_vslo(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_= t *b) { int sh =3D (b->VsrB(0xf) >> 3) & 0xf; =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN memmove(&r->u8[0], &a->u8[sh], 16 - sh); memset(&r->u8[16 - sh], 0, sh); #else @@ -1525,7 +1525,7 @@ void helper_vslo(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_= t *b) #endif } =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN #define ELEM_ADDR(VEC, IDX, SIZE) (&(VEC)->u8[IDX]) #else #define ELEM_ADDR(VEC, IDX, SIZE) (&(VEC)->u8[15 - (IDX)] - (SIZE) + 1) @@ -1554,7 +1554,7 @@ VINSX(W, uint32_t) VINSX(D, uint64_t) #undef ELEM_ADDR #undef VINSX -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN #define VEXTDVLX(NAME, SIZE) \ void helper_##NAME(CPUPPCState *env, ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t= *b, \ target_ulong index) = \ @@ -1593,7 +1593,7 @@ VEXTDVLX(VEXTDUHVLX, 2) VEXTDVLX(VEXTDUWVLX, 4) VEXTDVLX(VEXTDDVLX, 8) #undef VEXTDVLX -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN #define VEXTRACT(suffix, element) = \ void helper_vextract##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t inde= x) \ { = \ @@ -1696,7 +1696,7 @@ void helper_vsro(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_= t *b) { int sh =3D (b->VsrB(0xf) >> 3) & 0xf; =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN memmove(&r->u8[sh], &a->u8[0], 16 - sh); memset(&r->u8[0], 0, sh); #else @@ -1813,7 +1813,7 @@ void helper_vsum4ubs(CPUPPCState *env, ppc_avr_t *r, = ppc_avr_t *a, ppc_avr_t *b) } } =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN #define UPKHI 1 #define UPKLO 0 #else @@ -1920,7 +1920,7 @@ VGENERIC_DO(popcntd, u64) =20 #undef VGENERIC_DO =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN #define QW_ONE { .u64 =3D { 0, 1 } } #else #define QW_ONE { .u64 =3D { 1, 0 } } diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index dc93b99189ea..d1f07c4f41d4 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -632,7 +632,7 @@ static int kvm_put_fp(CPUState *cs) uint64_t *fpr =3D cpu_fpr_ptr(&cpu->env, i); uint64_t *vsrl =3D cpu_vsrl_ptr(&cpu->env, i); =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN vsr[0] =3D float64_val(*fpr); vsr[1] =3D *vsrl; #else @@ -710,7 +710,7 @@ static int kvm_get_fp(CPUState *cs) strerror(errno)); return ret; } else { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN *fpr =3D vsr[0]; if (vsx) { *vsrl =3D vsr[1]; diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 39945d9ea585..f1c76a7750ab 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -461,7 +461,7 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env, tar= get_ulong addr, =20 /*************************************************************************= ****/ /* Altivec extension helpers */ -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN #define HI_IDX 0 #define LO_IDX 1 #else diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 3bd4aac9c970..7a6ce0a3bc7d 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -79,7 +79,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ul= ong s1, * Note that vector data is stored in host-endian 64-bit chunks, * so addressing units smaller than that needs a host-endian fixup. */ -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define H1(x) ((x) ^ 7) #define H1_2(x) ((x) ^ 6) #define H1_4(x) ((x) ^ 4) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 46dea733571e..248b1bc58de4 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -263,7 +263,7 @@ static inline int vec_reg_offset(uint8_t reg, uint8_t e= nr, MemOp es) * 16 byte operations to handle it in a special way. */ g_assert(es <=3D MO_64); -#ifndef HOST_WORDS_BIGENDIAN +#if !HOST_BIG_ENDIAN offs ^=3D (8 - bytes); #endif return offs + vec_full_reg_offset(reg); diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index f917e5992dc7..3afdc6975cff 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -42,7 +42,7 @@ target_ulong helper_array8(target_ulong pixel_addr, targe= t_ulong cubesize) GET_FIELD_SP(pixel_addr, 11, 12); } =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define VIS_B64(n) b[7 - (n)] #define VIS_W64(n) w[3 - (n)] #define VIS_SW64(n) sw[3 - (n)] @@ -470,7 +470,7 @@ uint64_t helper_bshuffle(uint64_t gsr, uint64_t src1, u= int64_t src2) uint32_t i, mask, host; =20 /* Set up S such that we can index across all of the bytes. */ -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN s.ll[0] =3D src1; s.ll[1] =3D src2; host =3D 0; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 65e1c94c2d5c..5d48537927b5 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1156,7 +1156,7 @@ void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_= target_long offset) { /* Since arg2 and ret have different types, they cannot be the same temporary */ -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4); #else @@ -1167,7 +1167,7 @@ void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_= target_long offset) =20 void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4); #else diff --git a/tcg/tcg.c b/tcg/tcg.c index aea0bd8100e1..97d85851ccd4 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -51,7 +51,7 @@ #else # define ELF_CLASS ELFCLASS64 #endif -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN # define ELF_DATA ELFDATA2MSB #else # define ELF_DATA ELFDATA2LSB @@ -883,7 +883,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv= _ptr base, TCGTemp *base_ts =3D tcgv_ptr_temp(base); TCGTemp *ts =3D tcg_global_alloc(s); int indirect_reg =3D 0, bigendian =3D 0; -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN bigendian =3D 1; #endif =20 @@ -1541,7 +1541,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int narg= s, TCGTemp **args) } #else if (TCG_TARGET_REG_BITS < 64 && (typemask & 6) =3D=3D dh_typecode_= i64) { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN op->args[pi++] =3D temp_arg(ret + 1); op->args[pi++] =3D temp_arg(ret); #else @@ -1594,7 +1594,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int narg= s, TCGTemp **args) * have to get more complicated to differentiate between * stack arguments and register arguments. */ -#if defined(HOST_WORDS_BIGENDIAN) !=3D defined(TCG_TARGET_STACK_GROWSUP) +#if HOST_BIG_ENDIAN !=3D defined(TCG_TARGET_STACK_GROWSUP) op->args[pi++] =3D temp_arg(args[i] + 1); op->args[pi++] =3D temp_arg(args[i]); #else @@ -3592,7 +3592,7 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TC= GOp *op) /* fall through */ =20 case TEMP_VAL_MEM: -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN endian_fixup =3D itype =3D=3D TCG_TYPE_I32 ? 4 : 8; endian_fixup -=3D 1 << vece; #else @@ -3873,7 +3873,7 @@ static bool tcg_reg_alloc_dup2(TCGContext *s, const T= CGOp *op) if (!itsh->mem_coherent) { temp_sync(s, itsh, s->reserved_regs, 0, 0); } -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN TCGTemp *its =3D itsh; #else TCGTemp *its =3D itsl; diff --git a/tests/qtest/vhost-user-blk-test.c b/tests/qtest/vhost-user-blk= -test.c index 62e670f39be0..659b5050d8af 100644 --- a/tests/qtest/vhost-user-blk-test.c +++ b/tests/qtest/vhost-user-blk-test.c @@ -37,7 +37,7 @@ typedef struct QVirtioBlkReq { uint8_t status; } QVirtioBlkReq; =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN static const bool host_is_big_endian =3D true; #else static const bool host_is_big_endian; /* false */ diff --git a/tests/qtest/virtio-blk-test.c b/tests/qtest/virtio-blk-test.c index 2a236982118f..f22594a1a823 100644 --- a/tests/qtest/virtio-blk-test.c +++ b/tests/qtest/virtio-blk-test.c @@ -33,7 +33,7 @@ typedef struct QVirtioBlkReq { } QVirtioBlkReq; =20 =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN const bool host_is_big_endian =3D true; #else const bool host_is_big_endian; /* false */ diff --git a/ui/vdagent.c b/ui/vdagent.c index 7ea4bc5d9a26..02861edfb13c 100644 --- a/ui/vdagent.c +++ b/ui/vdagent.c @@ -664,7 +664,7 @@ static void vdagent_chr_open(Chardev *chr, VDAgentChardev *vd =3D QEMU_VDAGENT_CHARDEV(chr); ChardevQemuVDAgent *cfg =3D backend->u.qemu_vdagent.data; =20 -#if defined(HOST_WORDS_BIGENDIAN) +#if HOST_BIG_ENDIAN /* * TODO: vdagent protocol is defined to be LE, * so we have to byteswap everything on BE hosts. diff --git a/ui/vnc.c b/ui/vnc.c index 3ccd33dedcc8..2448384d4e64 100644 --- a/ui/vnc.c +++ b/ui/vnc.c @@ -2340,7 +2340,7 @@ static void pixel_format_message (VncState *vs) { vnc_write_u8(vs, vs->client_pf.bits_per_pixel); /* bits-per-pixel */ vnc_write_u8(vs, vs->client_pf.depth); /* depth */ =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN vnc_write_u8(vs, 1); /* big-endian-flag */ #else vnc_write_u8(vs, 0); /* big-endian-flag */ diff --git a/util/bitmap.c b/util/bitmap.c index 1f201393aef1..f81d8057a7e6 100644 --- a/util/bitmap.c +++ b/util/bitmap.c @@ -376,7 +376,7 @@ static void bitmap_to_from_le(unsigned long *dst, { long len =3D BITS_TO_LONGS(nbits); =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN long index; =20 for (index =3D 0; index < len; index++) { diff --git a/util/host-utils.c b/util/host-utils.c index bcc772b8ec95..96d5dc0bed25 100644 --- a/util/host-utils.c +++ b/util/host-utils.c @@ -34,7 +34,7 @@ static inline void mul64(uint64_t *plow, uint64_t *phigh, typedef union { uint64_t ll; struct { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN uint32_t high, low; #else uint32_t low, high; diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx= -impl.c.inc index d5e02fd7f22e..8e655d23b011 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -173,7 +173,7 @@ static void gen_mtvscr(DisasContext *ctx) =20 val =3D tcg_temp_new_i32(); bofs =3D avr_full_offset(rB(ctx->opcode)); -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN bofs +=3D 3 * 4; #endif =20 @@ -1157,7 +1157,7 @@ static void gen_vsplt(DisasContext *ctx, int vece) =20 /* Experimental testing shows that hardware masks the immediate. */ bofs +=3D (uimm << vece) & 15; -#ifndef HOST_WORDS_BIGENDIAN +#if !HOST_BIG_ENDIAN bofs ^=3D 15; bofs &=3D ~((1 << vece) - 1); #endif diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx= -impl.c.inc index 128968b5e7a8..8e4a54e51429 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -1446,7 +1446,7 @@ static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2 = *a) tofs =3D vsr_full_offset(a->xt); bofs =3D vsr_full_offset(a->xb); bofs +=3D a->uim << MO_32; -#ifndef HOST_WORDS_BIG_ENDIAN +#if !HOST_BIG_ENDIAN bofs ^=3D 8 | 4; #endif =20 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 275fded6e43b..04b55e5040ba 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3288,7 +3288,7 @@ static void load_element(TCGv_i64 dest, TCGv_ptr base, /* offset of the idx element with base regsiter r */ static uint32_t endian_ofs(DisasContext *s, int r, int idx) { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew); #else return vreg_ofs(s, r) + (idx << s->sew); @@ -3298,7 +3298,7 @@ static uint32_t endian_ofs(DisasContext *s, int r, in= t idx) /* adjust the index according to the endian */ static void endian_adjust(TCGv_i32 ofs, int sew) { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN tcg_gen_xori_i32(ofs, ofs, 7 >> sew); #endif } diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/transla= te_vx.c.inc index 98eb7710a4a9..b829ce0c7c79 100644 --- a/target/s390x/tcg/translate_vx.c.inc +++ b/target/s390x/tcg/translate_vx.c.inc @@ -175,7 +175,7 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8= _t reg, TCGv_i64 enr, =20 /* convert it to an element offset relative to cpu_env (vec_reg_offset= () */ tcg_gen_shli_i64(tmp, tmp, es); -#ifndef HOST_WORDS_BIGENDIAN +#if !HOST_BIG_ENDIAN tcg_gen_xori_i64(tmp, tmp, 8 - NUM_VEC_ELEMENT_BYTES(es)); #endif tcg_gen_addi_i64(tmp, tmp, vec_full_reg_offset(reg)); diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 077fc5140154..eb38113a70af 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1557,7 +1557,7 @@ static void tcg_out_adr(TCGContext *s, TCGReg rd, con= st void *target) */ static void * const qemu_ld_helpers[MO_SIZE + 1] =3D { [MO_8] =3D helper_ret_ldub_mmu, -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN [MO_16] =3D helper_be_lduw_mmu, [MO_32] =3D helper_be_ldul_mmu, [MO_64] =3D helper_be_ldq_mmu, @@ -1574,7 +1574,7 @@ static void * const qemu_ld_helpers[MO_SIZE + 1] =3D { */ static void * const qemu_st_helpers[MO_SIZE + 1] =3D { [MO_8] =3D helper_ret_stb_mmu, -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN [MO_16] =3D helper_be_stw_mmu, [MO_32] =3D helper_be_stl_mmu, [MO_64] =3D helper_be_stq_mmu, diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index e1ea69669cf7..072488c2a499 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1296,7 +1296,7 @@ static void tcg_out_vldst(TCGContext *s, ARMInsn insn, static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { [MO_UB] =3D helper_ret_ldub_mmu, [MO_SB] =3D helper_ret_ldsb_mmu, -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN [MO_UW] =3D helper_be_lduw_mmu, [MO_UL] =3D helper_be_ldul_mmu, [MO_UQ] =3D helper_be_ldq_mmu, @@ -1316,7 +1316,7 @@ static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D= { */ static void * const qemu_st_helpers[MO_SIZE + 1] =3D { [MO_8] =3D helper_ret_stb_mmu, -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN [MO_16] =3D helper_be_stw_mmu, [MO_32] =3D helper_be_stl_mmu, [MO_64] =3D helper_be_stq_mmu, diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 993149d18a56..bd76f0c97f15 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -26,7 +26,7 @@ =20 #include "../tcg-ldst.c.inc" =20 -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN # define MIPS_BE 1 #else # define MIPS_BE 0 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index dea24f23c4db..4c9031a044b3 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1864,7 +1864,7 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintp= tr_t jmp_rx, i1 =3D ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16); i2 =3D ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo); } -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN pair =3D (uint64_t)i1 << 32 | i2; #else pair =3D (uint64_t)i2 << 32 | i1; @@ -3232,7 +3232,7 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType t= ype, unsigned vece, tcg_out_mem_long(s, 0, LVEBX, out, base, offset); } elt =3D extract32(offset, 0, 4); -#ifndef HOST_WORDS_BIGENDIAN +#if !HOST_BIG_ENDIAN elt ^=3D 15; #endif tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16)); @@ -3245,7 +3245,7 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType t= ype, unsigned vece, tcg_out_mem_long(s, 0, LVEHX, out, base, offset); } elt =3D extract32(offset, 1, 3); -#ifndef HOST_WORDS_BIGENDIAN +#if !HOST_BIG_ENDIAN elt ^=3D 7; #endif tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16)); @@ -3258,7 +3258,7 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType t= ype, unsigned vece, tcg_debug_assert((offset & 3) =3D=3D 0); tcg_out_mem_long(s, 0, LVEWX, out, base, offset); elt =3D extract32(offset, 2, 2); -#ifndef HOST_WORDS_BIGENDIAN +#if !HOST_BIG_ENDIAN elt ^=3D 3; #endif tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16)); @@ -3272,7 +3272,7 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType t= ype, unsigned vece, tcg_out_mem_long(s, 0, LVX, out, base, offset & -16); tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8); elt =3D extract32(offset, 3, 1); -#ifndef HOST_WORDS_BIGENDIAN +#if !HOST_BIG_ENDIAN elt =3D !elt; #endif if (elt) { diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 6409d9c3d54f..81a83e45b156 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -854,7 +854,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { [MO_UB] =3D helper_ret_ldub_mmu, [MO_SB] =3D helper_ret_ldsb_mmu, -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN [MO_UW] =3D helper_be_lduw_mmu, [MO_SW] =3D helper_be_ldsw_mmu, [MO_UL] =3D helper_be_ldul_mmu, @@ -879,7 +879,7 @@ static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { */ static void * const qemu_st_helpers[MO_SIZE + 1] =3D { [MO_8] =3D helper_ret_stb_mmu, -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN [MO_16] =3D helper_be_stw_mmu, [MO_32] =3D helper_be_stl_mmu, [MO_64] =3D helper_be_stq_mmu, --=20 2.35.1.273.ge6ebfd0e8cbb From nobody Tue Sep 9 19:54:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645729329388409.449836048148; Thu, 24 Feb 2022 11:02:09 -0800 (PST) Received: from localhost ([::1]:45772 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nNJNQ-00015L-HT for importer@patchew.org; Thu, 24 Feb 2022 14:02:08 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52892) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNJ18-0001Fz-KS for qemu-devel@nongnu.org; Thu, 24 Feb 2022 13:39:09 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]:33818) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNJ13-0003Sy-G0 for qemu-devel@nongnu.org; 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bh=2z12ta4xtWfGl+Tz2GxV7yMJHecg9zDtt0Vhgl/N1oM=; b=Lr2iyKZ5BJ/28w939xDI+ZfCYMnQ2M2J6Q4pjMycfhRNJBf56pj6A8ypKJyUEZN2iwkuxM vYia3mP6Me322cW2L3H27sEC4pKlqKkX7BAqRlb2r27ooi9hzkSL5A64gXxV3UVFmpbSzX 2qIeVbaGkJa31TxBgAcJTPE5gcPT89I= X-MC-Unique: 00dvP6wgNSu7zFYvBRyqmw-1 From: marcandre.lureau@redhat.com To: qemu-devel@nongnu.org Subject: [PATCH 07/12] Simplify HOST_LONG_BITS Date: Thu, 24 Feb 2022 22:36:56 +0400 Message-Id: <20220224183701.608720-8-marcandre.lureau@redhat.com> In-Reply-To: <20220224183701.608720-1-marcandre.lureau@redhat.com> References: <20220224183701.608720-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=marcandre.lureau@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, f4bug@amsat.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645729330454100001 From: Marc-Andr=C3=A9 Lureau Simplify the macro, not depending on headers defines, but compiler predefined __SIZEOF__POINTER__ only. Available since gcc 4.3 and clang 2.8. Signed-off-by: Marc-Andr=C3=A9 Lureau Acked-by: Richard Henderson --- include/qemu/osdep.h | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 74473867f3f6..cea7303c78a4 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -261,13 +261,7 @@ G_NORETURN extern void QEMU_ERROR("code path is reacha= ble") #endif =20 /* HOST_LONG_BITS is the size of a native pointer in bits. */ -#if UINTPTR_MAX =3D=3D UINT32_MAX -# define HOST_LONG_BITS 32 -#elif UINTPTR_MAX =3D=3D UINT64_MAX -# define HOST_LONG_BITS 64 -#else -# error Unknown pointer size -#endif +#define HOST_LONG_BITS (__SIZEOF_POINTER__ * 8) =20 /* Mac OSX has a bug that incorrectly defines SIZE_MAX with * the wrong type. Our replacement isn't usable in preprocessor --=20 2.35.1.273.ge6ebfd0e8cbb From nobody Tue Sep 9 19:54:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164572917632936.59461180395431; Thu, 24 Feb 2022 10:59:36 -0800 (PST) Received: from localhost ([::1]:40284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nNJKx-0005e0-6k for importer@patchew.org; Thu, 24 Feb 2022 13:59:35 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52858) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNJ16-0001DP-GU for qemu-devel@nongnu.org; Thu, 24 Feb 2022 13:39:06 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]:37103) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNJ12-0003Sv-FR for qemu-devel@nongnu.org; Thu, 24 Feb 2022 13:39:02 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-665-tTbXqoF1MhKg_sMGDjULHg-1; Thu, 24 Feb 2022 13:38:36 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id B244E1006AAA; Thu, 24 Feb 2022 18:38:35 +0000 (UTC) Received: from localhost (unknown [10.39.208.2]) by smtp.corp.redhat.com (Postfix) with ESMTP id C04A31077CA4; Thu, 24 Feb 2022 18:38:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1645727919; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FtNOEdwWKpLqi2UbwE3lGWljXHp3G//CjWttxxkxiCE=; b=RkbATFsbKsaKtzSN+Q2XnYpTXl3DwH4VQS5qq0gxF4gSMe3LSDmUe7sT95SZ/ADls/NNfH 0l0F/tuiObHdbeDRHRLEe5oBRw9hc++fUnFYjegiwsoE91rztVCdnC7YDtBL604ohtqOwU i5MZFb4X1QyTSPy8vECZao7FduzgYIw= X-MC-Unique: tTbXqoF1MhKg_sMGDjULHg-1 From: marcandre.lureau@redhat.com To: qemu-devel@nongnu.org Subject: [PATCH 08/12] Move HOST_LONG_BITS to compiler.h Date: Thu, 24 Feb 2022 22:36:57 +0400 Message-Id: <20220224183701.608720-9-marcandre.lureau@redhat.com> In-Reply-To: <20220224183701.608720-1-marcandre.lureau@redhat.com> References: <20220224183701.608720-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=marcandre.lureau@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, f4bug@amsat.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645729178498100001 From: Marc-Andr=C3=A9 Lureau This will help to make common code independent. Signed-off-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Richard Henderson --- include/qemu/compiler.h | 3 +++ include/qemu/osdep.h | 3 --- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index 8c7da00c56ba..553e49aac2ad 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -9,6 +9,9 @@ =20 #define HOST_BIG_ENDIAN (__BYTE_ORDER__ =3D=3D __ORDER_BIG_ENDIAN__) =20 +/* HOST_LONG_BITS is the size of a native pointer in bits. */ +#define HOST_LONG_BITS (__SIZEOF_POINTER__ * 8) + #if defined __clang_analyzer__ || defined __COVERITY__ #define QEMU_STATIC_ANALYSIS 1 #endif diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index cea7303c78a4..4711aad22803 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -260,9 +260,6 @@ G_NORETURN extern void QEMU_ERROR("code path is reachab= le") #define TIME_MAX TYPE_MAXIMUM(time_t) #endif =20 -/* HOST_LONG_BITS is the size of a native pointer in bits. */ -#define HOST_LONG_BITS (__SIZEOF_POINTER__ * 8) - /* Mac OSX has a bug that incorrectly defines SIZE_MAX with * the wrong type. Our replacement isn't usable in preprocessor * expressions, but it is sufficient for our needs. */ --=20 2.35.1.273.ge6ebfd0e8cbb From nobody Tue Sep 9 19:54:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645729269408613.8403024542537; Thu, 24 Feb 2022 11:01:09 -0800 (PST) Received: from localhost ([::1]:43500 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nNJMS-0007tH-9n for importer@patchew.org; Thu, 24 Feb 2022 14:01:08 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52850) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNJ15-0001Cx-9u for qemu-devel@nongnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1645727926; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ugp1mdgJb26JDdeFglnw+DikYi1b0WF4j+loVws/Ih4=; b=BAJpL/2lLt6JAUcThokPudC3Bxn4INGoAXkumfSsLc6+8R3mKENKUgrf8lkSRyWa5gT1qv CS7UOk3yT2l423Nh9TYWnuiF2HetAexClez0sER+LT/+4DbXMjZEjg6CAR6c/u2tjMIbhG CKKGy/HuRrValf99BlNp41t8ffTzBLM= X-MC-Unique: HVJZw08zOVuBYi6QlsanPw-1 From: marcandre.lureau@redhat.com To: qemu-devel@nongnu.org Subject: [PATCH 09/12] scripts/modinfo-collect: remove unused/dead code Date: Thu, 24 Feb 2022 22:36:58 +0400 Message-Id: <20220224183701.608720-10-marcandre.lureau@redhat.com> In-Reply-To: <20220224183701.608720-1-marcandre.lureau@redhat.com> References: <20220224183701.608720-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; 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bh=1emFxB0SluYSWOJl9b4F0nZ9Kfg6N9LOW46u5twcR7o=; b=aB2qzOHmn51bXqjesJQqS1ujQwIbu7YJN3RmSSwqlcoMf8q41KoYldronMNleHQyyz1SQV 2EC6W/JO2phhJnfQU/upwbBLxjqIMuQ9zwKBLh+GqCA1xgd+bpy7XgOgCd0gsLcSv7QA3J bZ6JSiT58O13FgnfGX82vNjtB+uG5+g= X-MC-Unique: epz1LqJtOb6vb9a9wepNnA-1 From: marcandre.lureau@redhat.com To: qemu-devel@nongnu.org Subject: [PATCH 10/12] util: remove needless includes Date: Thu, 24 Feb 2022 22:36:59 +0400 Message-Id: <20220224183701.608720-11-marcandre.lureau@redhat.com> In-Reply-To: <20220224183701.608720-1-marcandre.lureau@redhat.com> References: <20220224183701.608720-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=marcandre.lureau@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, f4bug@amsat.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645729451906100001 From: Marc-Andr=C3=A9 Lureau Signed-off-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Richard Henderson --- util/cutils.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/util/cutils.c b/util/cutils.c index c9b91e7535a8..53346138c970 100644 --- a/util/cutils.c +++ b/util/cutils.c @@ -27,8 +27,6 @@ #include =20 #include "qemu-common.h" -#include "qemu/sockets.h" -#include "qemu/iov.h" #include "net/net.h" #include "qemu/ctype.h" #include "qemu/cutils.h" --=20 2.35.1.273.ge6ebfd0e8cbb From nobody Tue Sep 9 19:54:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=chVrM/uoMm3YftdNnPXnjTWF2hktiMoGMxHY4FmM7W4=; b=XUMX4nJZV6FcZP/cfeExf0ii1AxPxr9M3LwNzgEFPM9lEuKQP0VEykqIL5qbLlvJkZNMkl gXEElzNg3t4qYwLqH+n385P8jHl3U4+NSuvd7qXjn7aJp2bReu3zSkaJbxwkJ9WmLRTmtT Fh388/WIrxIx8tc5m3VhwqIB0lwRkbY= X-MC-Unique: XncdzWMrNgO_TQgVA3cjvQ-1 From: marcandre.lureau@redhat.com To: qemu-devel@nongnu.org Subject: [PATCH 11/12] util: remove the net/net.h dependency Date: Thu, 24 Feb 2022 22:37:00 +0400 Message-Id: <20220224183701.608720-12-marcandre.lureau@redhat.com> In-Reply-To: <20220224183701.608720-1-marcandre.lureau@redhat.com> References: <20220224183701.608720-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=marcandre.lureau@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Signed-off-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- include/qemu-common.h | 1 - net/announce.c | 13 +++++++++++++ util/cutils.c | 14 -------------- 3 files changed, 13 insertions(+), 15 deletions(-) diff --git a/include/qemu-common.h b/include/qemu-common.h index 79977cb3ec43..e702c5325674 100644 --- a/include/qemu-common.h +++ b/include/qemu-common.h @@ -108,7 +108,6 @@ void qemu_hexdump(FILE *fp, const char *prefix, */ int parse_debug_env(const char *name, int max, int initial); =20 -const char *qemu_ether_ntoa(const MACAddr *mac); void page_size_init(void); =20 /* returns non-zero if dump is in progress, otherwise zero is diff --git a/net/announce.c b/net/announce.c index 26f057f5ee47..3b9e2f1f14e8 100644 --- a/net/announce.c +++ b/net/announce.c @@ -120,6 +120,19 @@ static int announce_self_create(uint8_t *buf, return 60; /* len (FCS will be added by hardware) */ } =20 +/* + * Helper to print ethernet mac address + */ +static const char *qemu_ether_ntoa(const MACAddr *mac) +{ + static char ret[18]; + + snprintf(ret, sizeof(ret), "%02x:%02x:%02x:%02x:%02x:%02x", + mac->a[0], mac->a[1], mac->a[2], mac->a[3], mac->a[4], mac->a= [5]); + + return ret; +} + static void qemu_announce_self_iter(NICState *nic, void *opaque) { AnnounceTimer *timer =3D opaque; diff --git a/util/cutils.c b/util/cutils.c index 53346138c970..0d475ec4cddd 100644 --- a/util/cutils.c +++ b/util/cutils.c @@ -27,7 +27,6 @@ #include =20 #include "qemu-common.h" -#include "net/net.h" #include "qemu/ctype.h" #include "qemu/cutils.h" #include "qemu/error-report.h" @@ -936,19 +935,6 @@ int parse_debug_env(const char *name, int max, int ini= tial) return debug; } =20 -/* - * Helper to print ethernet mac address - */ -const char *qemu_ether_ntoa(const MACAddr *mac) -{ - static char ret[18]; - - snprintf(ret, sizeof(ret), "%02x:%02x:%02x:%02x:%02x:%02x", - mac->a[0], mac->a[1], mac->a[2], mac->a[3], mac->a[4], mac->a= [5]); - - return ret; -} - /* * Return human readable string for size @val. * @val can be anything that uint64_t allows (no more than "16 EiB"). --=20 2.35.1.273.ge6ebfd0e8cbb From nobody Tue Sep 9 19:54:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=NUyJW6adbkbq153SfXB6MqDKeNgik9NeE7s8tfuxU6U=; b=P/AnceoL7s+u8NO8i1QM6gk9rxMtwwAafxk/2y3ASEicfJs4Ve3wIIorFI6rlnh2NZ/Bv4 NHBtWP2O2IMqAbBJaTdId7eO9/jEzwzDt5ZSp/dl/9osfHmZZvCLJkfBmwg6bc/+TTlgOn aN4PNh+PhwJe/ZAzpUPzkTB6lZiYyW4= X-MC-Unique: EWcrXruoNGibqx7SGz65pQ-1 From: marcandre.lureau@redhat.com To: qemu-devel@nongnu.org Subject: [PATCH 12/12] qapi: remove needless include Date: Thu, 24 Feb 2022 22:37:01 +0400 Message-Id: <20220224183701.608720-13-marcandre.lureau@redhat.com> In-Reply-To: <20220224183701.608720-1-marcandre.lureau@redhat.com> References: <20220224183701.608720-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=marcandre.lureau@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, f4bug@amsat.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645730186747100003 From: Marc-Andr=C3=A9 Lureau Signed-off-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Richard Henderson --- qapi/qmp-dispatch.c | 1 - 1 file changed, 1 deletion(-) diff --git a/qapi/qmp-dispatch.c b/qapi/qmp-dispatch.c index d378bccac73b..0990873ec8ec 100644 --- a/qapi/qmp-dispatch.c +++ b/qapi/qmp-dispatch.c @@ -21,7 +21,6 @@ #include "qapi/qmp/qjson.h" #include "qapi/qobject-input-visitor.h" #include "qapi/qobject-output-visitor.h" -#include "sysemu/runstate.h" #include "qapi/qmp/qbool.h" #include "qemu/coroutine.h" #include "qemu/main-loop.h" --=20 2.35.1.273.ge6ebfd0e8cbb