From nobody Tue Feb 10 20:57:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645705248026969.4422316331135; Thu, 24 Feb 2022 04:20:48 -0800 (PST) Received: from localhost ([::1]:38594 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nND70-0005gq-WE for importer@patchew.org; Thu, 24 Feb 2022 07:20:47 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39288) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNCnb-0001HT-QY for qemu-devel@nongnu.org; Thu, 24 Feb 2022 07:00:43 -0500 Received: from [2001:41c9:1:41f::167] (port=45490 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNCnU-000061-KU for qemu-devel@nongnu.org; Thu, 24 Feb 2022 07:00:43 -0500 Received: from [2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe] (helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nNCmp-0003GS-6e; Thu, 24 Feb 2022 11:59:59 +0000 From: Mark Cave-Ayland To: laurent@vivier.eu, qemu-devel@nongnu.org Date: Thu, 24 Feb 2022 11:59:51 +0000 Message-Id: <20220224115956.29997-8-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220224115956.29997-1-mark.cave-ayland@ilande.co.uk> References: <20220224115956.29997-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 07/12] mos6522: add register names to register read/write trace events X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) X-Host-Lookup-Failed: Reverse DNS lookup failed for 2001:41c9:1:41f::167 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645705250445100004 Content-Type: text/plain; charset="utf-8" This helps to follow how the guest is programming the mos6522 when debuggin= g. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/mos6522.c | 10 ++++++++-- hw/misc/trace-events | 4 ++-- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 093cc83dcf..aaae195d63 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -36,6 +36,12 @@ #include "qemu/module.h" #include "trace.h" =20 + +static const char *mos6522_reg_names[16] =3D { + "ORB", "ORA", "DDRB", "DDRA", "T1CL", "T1CH", "T1LL", "T1LH", + "T2CL", "T2CH", "SR", "ACR", "PCR", "IFR", "IER", "ANH" +}; + /* XXX: implement all timer modes */ =20 static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti, @@ -310,7 +316,7 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsign= ed size) } =20 if (addr !=3D VIA_REG_IFR || val !=3D 0) { - trace_mos6522_read(addr, val); + trace_mos6522_read(addr, mos6522_reg_names[addr], val); } =20 return val; @@ -321,7 +327,7 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t = val, unsigned size) MOS6522State *s =3D opaque; MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(s); =20 - trace_mos6522_write(addr, val); + trace_mos6522_write(addr, mos6522_reg_names[addr], val); =20 switch (addr) { case VIA_REG_B: diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 1c373dd0a4..c1ea57de31 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -95,8 +95,8 @@ imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%= 08" PRIx64 "value 0x%08 mos6522_set_counter(int index, unsigned int val) "T%d.counter=3D%d" mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch= =3D%d counter=3D0x%"PRId64 " delta_next=3D0x%"PRId64 mos6522_set_sr_int(void) "set sr_int" -mos6522_write(uint64_t addr, uint64_t val) "reg=3D0x%"PRIx64 " val=3D0x%"P= RIx64 -mos6522_read(uint64_t addr, unsigned val) "reg=3D0x%"PRIx64 " val=3D0x%x" +mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=3D0x%"PR= Ix64 " [%s] val=3D0x%"PRIx64 +mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=3D0x%"PRI= x64 " [%s] val=3D0x%x" =20 # npcm7xx_clk.c npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 = " value: 0x%08" PRIx32 --=20 2.20.1