From nobody Tue Feb 10 17:45:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645704712706579.1987155032484; Thu, 24 Feb 2022 04:11:52 -0800 (PST) Received: from localhost ([::1]:47948 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nNCyN-0000c1-8N for importer@patchew.org; Thu, 24 Feb 2022 07:11:51 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39270) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNCnY-0001BT-3n for qemu-devel@nongnu.org; Thu, 24 Feb 2022 07:00:40 -0500 Received: from [2001:41c9:1:41f::167] (port=45472 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNCnR-000053-HS for qemu-devel@nongnu.org; Thu, 24 Feb 2022 07:00:39 -0500 Received: from [2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe] (helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nNCmd-0003GS-4S; Thu, 24 Feb 2022 11:59:47 +0000 From: Mark Cave-Ayland To: laurent@vivier.eu, qemu-devel@nongnu.org Date: Thu, 24 Feb 2022 11:59:48 +0000 Message-Id: <20220224115956.29997-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220224115956.29997-1-mark.cave-ayland@ilande.co.uk> References: <20220224115956.29997-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 04/12] mos6522: switch over to use qdev gpios for IRQs X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) X-Host-Lookup-Failed: Reverse DNS lookup failed for 2001:41c9:1:41f::167 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645704714883100001 Content-Type: text/plain; charset="utf-8" For historical reasons each mos6522 instance implements its own setting and update of the IFR flag bits using methods exposed by MOS6522DeviceClass. As of today this is no longer required, and it is now possible to implement the mos6522 IRQs as standard qdev gpios. Switch over to use qdev gpios for the mos6522 device and update all instanc= es accordingly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell Reviewed-by: Laurent Vivier --- hw/misc/mac_via.c | 56 +++++++-------------------------------- hw/misc/macio/cuda.c | 5 ++-- hw/misc/macio/pmu.c | 4 +-- hw/misc/mos6522.c | 15 +++++++++++ include/hw/misc/mac_via.h | 5 ---- include/hw/misc/mos6522.h | 2 ++ 6 files changed, 31 insertions(+), 56 deletions(-) diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index 71b74c3372..80eb433044 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -325,10 +325,9 @@ static void via1_sixty_hz(void *opaque) { MOS6522Q800VIA1State *v1s =3D opaque; MOS6522State *s =3D MOS6522(v1s); - MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(s); + qemu_irq irq =3D qdev_get_gpio_in(DEVICE(s), VIA1_IRQ_60HZ_BIT); =20 - s->ifr |=3D VIA1_IRQ_60HZ; - mdc->update_irq(s); + qemu_set_irq(irq, 1); =20 via1_sixty_hz_update(v1s); } @@ -337,44 +336,13 @@ static void via1_one_second(void *opaque) { MOS6522Q800VIA1State *v1s =3D opaque; MOS6522State *s =3D MOS6522(v1s); - MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(s); + qemu_irq irq =3D qdev_get_gpio_in(DEVICE(s), VIA1_IRQ_ONE_SECOND_BIT); =20 - s->ifr |=3D VIA1_IRQ_ONE_SECOND; - mdc->update_irq(s); + qemu_set_irq(irq, 1); =20 via1_one_second_update(v1s); } =20 -static void via1_irq_request(void *opaque, int irq, int level) -{ - MOS6522Q800VIA1State *v1s =3D opaque; - MOS6522State *s =3D MOS6522(v1s); - MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(s); - - if (level) { - s->ifr |=3D 1 << irq; - } else { - s->ifr &=3D ~(1 << irq); - } - - mdc->update_irq(s); -} - -static void via2_irq_request(void *opaque, int irq, int level) -{ - MOS6522Q800VIA2State *v2s =3D opaque; - MOS6522State *s =3D MOS6522(v2s); - MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(s); - - if (level) { - s->ifr |=3D 1 << irq; - } else { - s->ifr &=3D ~(1 << irq); - } - - mdc->update_irq(s); -} - =20 static void pram_update(MOS6522Q800VIA1State *v1s) { @@ -1061,8 +1029,6 @@ static void mos6522_q800_via1_init(Object *obj) qbus_init((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus), TYPE_ADB_BUS, DEVICE(v1s), "adb.0"); =20 - qdev_init_gpio_in(DEVICE(obj), via1_irq_request, VIA1_IRQ_NB); - /* A/UX mode */ qdev_init_gpio_out(DEVICE(obj), &v1s->auxmode_irq, 1); } @@ -1150,22 +1116,20 @@ static void mos6522_q800_via2_reset(DeviceState *de= v) ms->a =3D 0x7f; } =20 -static void via2_nubus_irq_request(void *opaque, int irq, int level) +static void via2_nubus_irq_request(void *opaque, int n, int level) { MOS6522Q800VIA2State *v2s =3D opaque; MOS6522State *s =3D MOS6522(v2s); - MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(s); + qemu_irq irq =3D qdev_get_gpio_in(DEVICE(s), VIA2_IRQ_NUBUS_BIT); =20 if (level) { /* Port A nubus IRQ inputs are active LOW */ - s->a &=3D ~(1 << irq); - s->ifr |=3D 1 << VIA2_IRQ_NUBUS_BIT; + s->a &=3D ~(1 << n); } else { - s->a |=3D (1 << irq); - s->ifr &=3D ~(1 << VIA2_IRQ_NUBUS_BIT); + s->a |=3D (1 << n); } =20 - mdc->update_irq(s); + qemu_set_irq(irq, level); } =20 static void mos6522_q800_via2_init(Object *obj) @@ -1177,8 +1141,6 @@ static void mos6522_q800_via2_init(Object *obj) "via2", VIA_SIZE); sysbus_init_mmio(sbd, &v2s->via_mem); =20 - qdev_init_gpio_in(DEVICE(obj), via2_irq_request, VIA2_IRQ_NB); - qdev_init_gpio_in_named(DEVICE(obj), via2_nubus_irq_request, "nubus-ir= q", VIA2_NUBUS_IRQ_NB); } diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 233daf1405..693fc82e05 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -24,6 +24,7 @@ */ =20 #include "qemu/osdep.h" +#include "hw/irq.h" #include "hw/ppc/mac.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -96,9 +97,9 @@ static void cuda_set_sr_int(void *opaque) CUDAState *s =3D opaque; MOS6522CUDAState *mcs =3D &s->mos6522_cuda; MOS6522State *ms =3D MOS6522(mcs); - MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(ms); + qemu_irq irq =3D qdev_get_gpio_in(DEVICE(ms), SR_INT_BIT); =20 - mdc->set_sr_int(ms); + qemu_set_irq(irq, 1); } =20 static void cuda_delay_set_sr_int(CUDAState *s) diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c index 76c608ee19..b210068ab7 100644 --- a/hw/misc/macio/pmu.c +++ b/hw/misc/macio/pmu.c @@ -75,9 +75,9 @@ static void via_set_sr_int(void *opaque) PMUState *s =3D opaque; MOS6522PMUState *mps =3D MOS6522_PMU(&s->mos6522_pmu); MOS6522State *ms =3D MOS6522(mps); - MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(ms); + qemu_irq irq =3D qdev_get_gpio_in(DEVICE(ms), SR_INT_BIT); =20 - mdc->set_sr_int(ms); + qemu_set_irq(irq, 1); } =20 static void pmu_update_extirq(PMUState *s) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 1c57332b40..6be6853dc2 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -52,6 +52,19 @@ static void mos6522_update_irq(MOS6522State *s) } } =20 +static void mos6522_set_irq(void *opaque, int n, int level) +{ + MOS6522State *s =3D MOS6522(opaque); + + if (level) { + s->ifr |=3D 1 << n; + } else { + s->ifr &=3D ~(1 << n); + } + + mos6522_update_irq(s); +} + static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti) { MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(s); @@ -488,6 +501,8 @@ static void mos6522_init(Object *obj) =20 s->timers[0].timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1= , s); s->timers[1].timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2= , s); + + qdev_init_gpio_in(DEVICE(obj), mos6522_set_irq, VIA_NUM_INTS); } =20 static void mos6522_finalize(Object *obj) diff --git a/include/hw/misc/mac_via.h b/include/hw/misc/mac_via.h index 0af346366e..5fe7a7f592 100644 --- a/include/hw/misc/mac_via.h +++ b/include/hw/misc/mac_via.h @@ -24,8 +24,6 @@ #define VIA1_IRQ_ADB_DATA_BIT CB2_INT_BIT #define VIA1_IRQ_ADB_CLOCK_BIT CB1_INT_BIT =20 -#define VIA1_IRQ_NB 8 - #define VIA1_IRQ_ONE_SECOND BIT(VIA1_IRQ_ONE_SECOND_BIT) #define VIA1_IRQ_60HZ BIT(VIA1_IRQ_60HZ_BIT) #define VIA1_IRQ_ADB_READY BIT(VIA1_IRQ_ADB_READY_BIT) @@ -42,7 +40,6 @@ struct MOS6522Q800VIA1State { =20 MemoryRegion via_mem; =20 - qemu_irq irqs[VIA1_IRQ_NB]; qemu_irq auxmode_irq; uint8_t last_b; =20 @@ -85,8 +82,6 @@ struct MOS6522Q800VIA1State { #define VIA2_IRQ_SCSI_BIT CB2_INT_BIT #define VIA2_IRQ_ASC_BIT CB1_INT_BIT =20 -#define VIA2_IRQ_NB 8 - #define VIA2_IRQ_SCSI_DATA BIT(VIA2_IRQ_SCSI_DATA_BIT) #define VIA2_IRQ_NUBUS BIT(VIA2_IRQ_NUBUS_BIT) #define VIA2_IRQ_UNUSED BIT(VIA2_IRQ_SCSI_BIT) diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h index be5c90d24d..f38ae2b0f0 100644 --- a/include/hw/misc/mos6522.h +++ b/include/hw/misc/mos6522.h @@ -57,6 +57,8 @@ #define T2_INT BIT(T2_INT_BIT) #define T1_INT BIT(T1_INT_BIT) =20 +#define VIA_NUM_INTS 5 + /* Bits in ACR */ #define T1MODE 0xc0 /* Timer 1 mode */ #define T1MODE_CONT 0x40 /* continuous interrupts */ --=20 2.20.1