From nobody Tue Feb 10 20:49:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645705235610656.9121105916081; Thu, 24 Feb 2022 04:20:35 -0800 (PST) Received: from localhost ([::1]:38384 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nND6o-0005YL-F0 for importer@patchew.org; Thu, 24 Feb 2022 07:20:34 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39392) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNCnu-0001f2-C2 for qemu-devel@nongnu.org; Thu, 24 Feb 2022 07:01:02 -0500 Received: from [2001:41c9:1:41f::167] (port=45518 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNCnq-0000B1-IF for qemu-devel@nongnu.org; Thu, 24 Feb 2022 07:01:02 -0500 Received: from [2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe] (helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nNCn2-0003GS-Ty; Thu, 24 Feb 2022 12:00:09 +0000 From: Mark Cave-Ayland To: laurent@vivier.eu, qemu-devel@nongnu.org Date: Thu, 24 Feb 2022 11:59:56 +0000 Message-Id: <20220224115956.29997-13-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220224115956.29997-1-mark.cave-ayland@ilande.co.uk> References: <20220224115956.29997-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 12/12] macio/pmu.c: remove redundant code X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) X-Host-Lookup-Failed: Reverse DNS lookup failed for 2001:41c9:1:41f::167 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645705236119100001 Content-Type: text/plain; charset="utf-8" Now that the logic related to edge-triggered interrupts is all contained wi= thin the mos6522 device the redundant implementation for the mac99 PMU device can be removed. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier --- hw/misc/macio/pmu.c | 33 --------------------------------- include/hw/misc/macio/pmu.h | 2 -- 2 files changed, 35 deletions(-) diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c index 5b1ec100e2..336502a84b 100644 --- a/hw/misc/macio/pmu.c +++ b/hw/misc/macio/pmu.c @@ -57,19 +57,6 @@ =20 #define VIA_TIMER_FREQ (4700000 / 6) =20 -static void via_update_irq(PMUState *s) -{ - MOS6522PMUState *mps =3D MOS6522_PMU(&s->mos6522_pmu); - MOS6522State *ms =3D MOS6522(mps); - - bool new_state =3D !!(ms->ifr & ms->ier & (SR_INT | T1_INT | T2_INT)); - - if (new_state !=3D s->via_irq_state) { - s->via_irq_state =3D new_state; - qemu_set_irq(s->via_irq, new_state); - } -} - static void via_set_sr_int(void *opaque) { PMUState *s =3D opaque; @@ -808,28 +795,9 @@ static void mos6522_pmu_portB_write(MOS6522State *s) MOS6522PMUState *mps =3D container_of(s, MOS6522PMUState, parent_obj); PMUState *ps =3D container_of(mps, PMUState, mos6522_pmu); =20 - if ((s->pcr & 0xe0) =3D=3D 0x20 || (s->pcr & 0xe0) =3D=3D 0x60) { - s->ifr &=3D ~CB2_INT; - } - s->ifr &=3D ~CB1_INT; - - via_update_irq(ps); pmu_update(ps); } =20 -static void mos6522_pmu_portA_write(MOS6522State *s) -{ - MOS6522PMUState *mps =3D container_of(s, MOS6522PMUState, parent_obj); - PMUState *ps =3D container_of(mps, PMUState, mos6522_pmu); - - if ((s->pcr & 0x0e) =3D=3D 0x02 || (s->pcr & 0x0e) =3D=3D 0x06) { - s->ifr &=3D ~CA2_INT; - } - s->ifr &=3D ~CA1_INT; - - via_update_irq(ps); -} - static void mos6522_pmu_reset(DeviceState *dev) { MOS6522State *ms =3D MOS6522(dev); @@ -853,7 +821,6 @@ static void mos6522_pmu_class_init(ObjectClass *oc, voi= d *data) device_class_set_parent_reset(dc, mos6522_pmu_reset, &mdc->parent_reset); mdc->portB_write =3D mos6522_pmu_portB_write; - mdc->portA_write =3D mos6522_pmu_portA_write; } =20 static const TypeInfo mos6522_pmu_type_info =3D { diff --git a/include/hw/misc/macio/pmu.h b/include/hw/misc/macio/pmu.h index 78237d99a2..00fcdd23f5 100644 --- a/include/hw/misc/macio/pmu.h +++ b/include/hw/misc/macio/pmu.h @@ -193,8 +193,6 @@ struct PMUState { =20 MemoryRegion mem; uint64_t frequency; - qemu_irq via_irq; - bool via_irq_state; =20 /* PMU state */ MOS6522PMUState mos6522_pmu; --=20 2.20.1