From nobody Tue May 14 12:49:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1645539523; cv=none; d=zohomail.com; s=zohoarc; b=FOMcuQSOJGZlNj6xlbD/d6q6Og6x6J1yaIQJR+7b7DNXQPM1qfUHEz/BMh1wPTtyAKNQO7K0l8ASzJWLZJFFfcIH9eQJ4PKk+n8XUEp4ly2UOeABfFR8vOLVzzMXKm1BaGJnAaMJcsNabWdHQZEH9pgQz3qPbCu9lgzX0HhHuzE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1645539523; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=vdgZCx+68k2wadQdVInNwZAK+nKhEJDGULktEsW8qHs=; b=jumTvgJXmA2HHtx4aEz4oSkf9ggowAzmDMY8N9jperksZf9cwnvQ3q32w7F5epjngFNlTLuqr5l9+kH12Mt01YjQ184rDskpPga31r0+VCwLnm77rh8CD7B45sV1xtLiydUe2m+YKooL5soLX5rhYmMli1M/pgl2l9D/drVB5pk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645539523128930.9458352743532; Tue, 22 Feb 2022 06:18:43 -0800 (PST) Received: from localhost ([::1]:50162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nMW00-0006hT-19 for importer@patchew.org; Tue, 22 Feb 2022 09:18:40 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36010) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nMVtC-000834-EX for qemu-devel@nongnu.org; Tue, 22 Feb 2022 09:11:38 -0500 Received: from szxga02-in.huawei.com ([45.249.212.188]:5106) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nMVt5-0008OD-El for qemu-devel@nongnu.org; Tue, 22 Feb 2022 09:11:38 -0500 Received: from dggpeml500023.china.huawei.com (unknown [172.30.72.56]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4K31JK6Q0wz9srS; Tue, 22 Feb 2022 22:09:37 +0800 (CST) Received: from dggpeml100016.china.huawei.com (7.185.36.216) by dggpeml500023.china.huawei.com (7.185.36.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.21; Tue, 22 Feb 2022 22:11:20 +0800 Received: from DESKTOP-27KDQMV.china.huawei.com (10.174.148.223) by dggpeml100016.china.huawei.com (7.185.36.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.21; Tue, 22 Feb 2022 22:11:20 +0800 To: CC: , , , , , Longpeng Subject: [PATCH resend 1/2] kvm-irqchip: introduce new API to support route change Date: Tue, 22 Feb 2022 22:11:15 +0800 Message-ID: <20220222141116.2091-2-longpeng2@huawei.com> X-Mailer: git-send-email 2.25.0.windows.1 In-Reply-To: <20220222141116.2091-1-longpeng2@huawei.com> References: <20220222141116.2091-1-longpeng2@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.148.223] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggpeml100016.china.huawei.com (7.185.36.216) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.188; envelope-from=longpeng2@huawei.com; helo=szxga02-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: "Longpeng(Mike)" From: "Longpeng(Mike)" via X-ZM-MESSAGEID: 1645539524559100001 Content-Type: text/plain; charset="utf-8" From: Longpeng Paolo suggested adding the new API to support route changes [1]. We should = invoke kvm_irqchip_begin_route_changes() before changing the routes, increasing the KVMRouteChange.changes if the routes are changed, and commit the changes at= last. [1] https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg02898.html Signed-off-by: Longpeng --- include/sysemu/kvm.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 6eb39a088b..6f8a43dea4 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -224,6 +224,11 @@ DECLARE_INSTANCE_CHECKER(KVMState, KVM_STATE, extern KVMState *kvm_state; typedef struct Notifier Notifier; =20 +typedef struct KVMRouteChange { + KVMState *s; + int changes; +} KVMRouteChange; + /* external API */ =20 bool kvm_has_free_slot(MachineState *ms); @@ -494,6 +499,20 @@ int kvm_irqchip_add_msi_route(KVMState *s, int vector,= PCIDevice *dev); int kvm_irqchip_update_msi_route(KVMState *s, int virq, MSIMessage msg, PCIDevice *dev); void kvm_irqchip_commit_routes(KVMState *s); + +static inline KVMRouteChange kvm_irqchip_begin_route_changes(KVMState *s) +{ + return (KVMRouteChange) { .s =3D s, .changes =3D 0 }; +} + +static inline void kvm_irqchip_commit_route_changes(KVMRouteChange *c) +{ + if (c->changes) { + kvm_irqchip_commit_routes(c->s); + c->changes =3D 0; + } +} + void kvm_irqchip_release_virq(KVMState *s, int virq); =20 int kvm_irqchip_add_adapter_route(KVMState *s, AdapterInfo *adapter); --=20 2.23.0 From nobody Tue May 14 12:49:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1645539653; cv=none; d=zohomail.com; s=zohoarc; b=XrQ/H+8WHeqoJCCanQTPh2WU9rRBLBtahc65zsbYs2J+cUPHu5Ksg3k2RnDwp2lSLGpjkiFIGq+bvdZtFrP1rN9buP4yuRpbFnplgLhBc/QjJohNPf7AYCx/752SGac5KJYbY2Ta3NkM0MtJOO3D7M+S6wlsiVdkguLQutzTjc8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1645539653; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; 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Tue, 22 Feb 2022 09:11:42 -0500 Received: from szxga03-in.huawei.com ([45.249.212.189]:4183) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nMVt5-0008OW-El for qemu-devel@nongnu.org; Tue, 22 Feb 2022 09:11:41 -0500 Received: from dggpeml500026.china.huawei.com (unknown [172.30.72.55]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4K31GM31Gpz9sBv; Tue, 22 Feb 2022 22:07:55 +0800 (CST) Received: from dggpeml100016.china.huawei.com (7.185.36.216) by dggpeml500026.china.huawei.com (7.185.36.106) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.21; Tue, 22 Feb 2022 22:11:21 +0800 Received: from DESKTOP-27KDQMV.china.huawei.com (10.174.148.223) by dggpeml100016.china.huawei.com (7.185.36.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.21; Tue, 22 Feb 2022 22:11:20 +0800 To: CC: , , , , , Longpeng Subject: [PATCH resend 2/2] kvm/msi: do explicit commit when adding msi routes Date: Tue, 22 Feb 2022 22:11:16 +0800 Message-ID: <20220222141116.2091-3-longpeng2@huawei.com> X-Mailer: git-send-email 2.25.0.windows.1 In-Reply-To: <20220222141116.2091-1-longpeng2@huawei.com> References: <20220222141116.2091-1-longpeng2@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.148.223] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggpeml100016.china.huawei.com (7.185.36.216) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.189; envelope-from=longpeng2@huawei.com; helo=szxga03-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: "Longpeng(Mike)" From: "Longpeng(Mike)" via X-ZM-MESSAGEID: 1645539655647100001 Content-Type: text/plain; charset="utf-8" From: Longpeng We invoke the kvm_irqchip_commit_routes() for each addition to MSI route table, which is not efficient if we are adding lots of routes in some cases. This patch lets callers invoke the kvm_irqchip_commit_routes(), so the callers can decide how to optimize. [1] https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg00967.html Signed-off-by: Longpeng --- accel/kvm/kvm-all.c | 7 ++++--- accel/stubs/kvm-stub.c | 2 +- hw/misc/ivshmem.c | 5 ++++- hw/vfio/pci.c | 5 ++++- hw/virtio/virtio-pci.c | 4 +++- include/sysemu/kvm.h | 4 ++-- target/i386/kvm/kvm.c | 4 +++- 7 files changed, 21 insertions(+), 10 deletions(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 0e66ebb497..27864dfaea 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -1961,10 +1961,11 @@ int kvm_irqchip_send_msi(KVMState *s, MSIMessage ms= g) return kvm_set_irq(s, route->kroute.gsi, 1); } =20 -int kvm_irqchip_add_msi_route(KVMState *s, int vector, PCIDevice *dev) +int kvm_irqchip_add_msi_route(KVMRouteChange *c, int vector, PCIDevice *de= v) { struct kvm_irq_routing_entry kroute =3D {}; int virq; + KVMState *s =3D c->s; MSIMessage msg =3D {0, 0}; =20 if (pci_available && dev) { @@ -2004,7 +2005,7 @@ int kvm_irqchip_add_msi_route(KVMState *s, int vector= , PCIDevice *dev) =20 kvm_add_routing_entry(s, &kroute); kvm_arch_add_msi_route_post(&kroute, vector, dev); - kvm_irqchip_commit_routes(s); + c->changes++; =20 return virq; } @@ -2162,7 +2163,7 @@ int kvm_irqchip_send_msi(KVMState *s, MSIMessage msg) abort(); } =20 -int kvm_irqchip_add_msi_route(KVMState *s, int vector, PCIDevice *dev) +int kvm_irqchip_add_msi_route(KVMRouteChange *c, int vector, PCIDevice *de= v) { return -ENOSYS; } diff --git a/accel/stubs/kvm-stub.c b/accel/stubs/kvm-stub.c index 5319573e00..ae6e8e9aa7 100644 --- a/accel/stubs/kvm-stub.c +++ b/accel/stubs/kvm-stub.c @@ -81,7 +81,7 @@ int kvm_on_sigbus(int code, void *addr) } =20 #ifndef CONFIG_USER_ONLY -int kvm_irqchip_add_msi_route(KVMState *s, int vector, PCIDevice *dev) +int kvm_irqchip_add_msi_route(KVMRouteChange *c, int vector, PCIDevice *de= v) { return -ENOSYS; } diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c index 299837e5c1..2307f4a513 100644 --- a/hw/misc/ivshmem.c +++ b/hw/misc/ivshmem.c @@ -424,16 +424,19 @@ static void ivshmem_add_kvm_msi_virq(IVShmemState *s,= int vector, Error **errp) { PCIDevice *pdev =3D PCI_DEVICE(s); + KVMRouteChange c; int ret; =20 IVSHMEM_DPRINTF("ivshmem_add_kvm_msi_virq vector:%d\n", vector); assert(!s->msi_vectors[vector].pdev); =20 - ret =3D kvm_irqchip_add_msi_route(kvm_state, vector, pdev); + c =3D kvm_irqchip_begin_route_changes(kvm_state); + ret =3D kvm_irqchip_add_msi_route(&c, vector, pdev); if (ret < 0) { error_setg(errp, "kvm_irqchip_add_msi_route failed"); return; } + kvm_irqchip_commit_route_changes(&c); =20 s->msi_vectors[vector].virq =3D ret; s->msi_vectors[vector].pdev =3D pdev; diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 7b45353ce2..d07a4e99b1 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -412,6 +412,7 @@ static int vfio_enable_vectors(VFIOPCIDevice *vdev, boo= l msix) static void vfio_add_kvm_msi_virq(VFIOPCIDevice *vdev, VFIOMSIVector *vect= or, int vector_n, bool msix) { + KVMRouteChange c; int virq; =20 if ((msix && vdev->no_kvm_msix) || (!msix && vdev->no_kvm_msi)) { @@ -422,11 +423,13 @@ static void vfio_add_kvm_msi_virq(VFIOPCIDevice *vdev= , VFIOMSIVector *vector, return; } =20 - virq =3D kvm_irqchip_add_msi_route(kvm_state, vector_n, &vdev->pdev); + c =3D kvm_irqchip_begin_route_changes(kvm_state); + virq =3D kvm_irqchip_add_msi_route(&c, vector_n, &vdev->pdev); if (virq < 0) { event_notifier_cleanup(&vector->kvm_interrupt); return; } + kvm_irqchip_commit_route_changes(&c); =20 if (kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &vector->kvm_interru= pt, NULL, virq) < 0) { diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 373e26d7c3..80d8c2ea11 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -758,10 +758,12 @@ static int kvm_virtio_pci_vq_vector_use(VirtIOPCIProx= y *proxy, int ret; =20 if (irqfd->users =3D=3D 0) { - ret =3D kvm_irqchip_add_msi_route(kvm_state, vector, &proxy->pci_d= ev); + KVMRouteChange c =3D kvm_irqchip_begin_route_changes(kvm_state); + ret =3D kvm_irqchip_add_msi_route(&c, vector, &proxy->pci_dev); if (ret < 0) { return ret; } + kvm_irqchip_commit_route_changes(&c); irqfd->virq =3D ret; } irqfd->users++; diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 6f8a43dea4..097b3c79d5 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -486,7 +486,7 @@ void kvm_init_cpu_signals(CPUState *cpu); =20 /** * kvm_irqchip_add_msi_route - Add MSI route for specific vector - * @s: KVM state + * @c: KVMRouteChange instance. * @vector: which vector to add. This can be either MSI/MSIX * vector. The function will automatically detect whether * MSI/MSIX is enabled, and fetch corresponding MSI @@ -495,7 +495,7 @@ void kvm_init_cpu_signals(CPUState *cpu); * as @NULL, an empty MSI message will be inited. * @return: virq (>=3D0) when success, errno (<0) when failed. */ -int kvm_irqchip_add_msi_route(KVMState *s, int vector, PCIDevice *dev); +int kvm_irqchip_add_msi_route(KVMRouteChange *c, int vector, PCIDevice *de= v); int kvm_irqchip_update_msi_route(KVMState *s, int virq, MSIMessage msg, PCIDevice *dev); void kvm_irqchip_commit_routes(KVMState *s); diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 2c8feb4a6f..cfef36a14e 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4939,16 +4939,18 @@ void kvm_arch_init_irq_routing(KVMState *s) kvm_gsi_routing_allowed =3D true; =20 if (kvm_irqchip_is_split()) { + KVMRouteChange c =3D kvm_irqchip_begin_route_changes(s); int i; =20 /* If the ioapic is in QEMU and the lapics are in KVM, reserve MSI routes for signaling interrupts to the local apics. */ for (i =3D 0; i < IOAPIC_NUM_PINS; i++) { - if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) { + if (kvm_irqchip_add_msi_route(&c, 0, NULL) < 0) { error_report("Could not enable split IRQ mode."); exit(1); } } + kvm_irqchip_commit_route_changes(&c); } } =20 --=20 2.23.0