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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id r38sm2315588otv.72.2022.02.18.16.25.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 16:25:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PQUR9g32PcNWM1dcLFOOQE2tEhDkQc2466/0oXZlsAw=; b=z9NxNhe/lNhXxE98BIVndjKC8flAkdyyEFGU8V9WqyqYVHL3BjPy2ug+8q2/4wut8A pTdfAM4xfMfCQuX50bSNUpUbmGO+odEqm9BxvU0bwPuxYp5jNDKhWqCel/wH1GSewywD 54hrD3jMjMZwQpiB63olxq2cjXVF4I33MIurNgOEubDLfnOxDa8ZAlPsZrRkMKHiqG1+ uC14dCTjEkFup11NOOMU2ZJxxTJRklEWQdZyT66wnX6wuMrXsh/TDWHrd7HrxncshGuq 5qk9ZwG3tcEvAT2cxxR56xVfzLEj2uQdLr/m/9300nViFOmEIiBpDcrxX0ScPy+UjsCD yK0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PQUR9g32PcNWM1dcLFOOQE2tEhDkQc2466/0oXZlsAw=; b=Fi9xzxjdgBSK9cTKSAgV/PJRRPG6F6TqUFexu2Dtdf7KYMw7vC3HItPr0JXePYoZ/7 4SkFok28F6RfUJExhUH+lov1WlaJ9fCXRUuDacqKe3W/xIkg5kKhc36RsnR4p0l7n+lU bb2ggVsn/EeQgbIFQcjnG5+dtRAAOBMICWDe80mlWhOnXYpn9Z8Njfn48a/WVvqFzx+5 MEZQPTLyzNAnk8i2N442sCwqLUYgGIUzbfIdhvEgCbq51sU9qVX4BqV9RMPngQGPrrAr blhgiu3LTqXsvdjMJsiArEmkBzoTsYZzkW4S8D6Jrq5K/NMulPoPx6YqdP/TuUlysrR8 ytvg== X-Gm-Message-State: AOAM533O9hCZsxavKTlLsn5bsGwZ/JbsIdRFW7noBlsCHQmRUIbjBqze Zzjlk38gTJ5hWrFSvayItuIrKURbE3HvLx9A X-Google-Smtp-Source: ABdhPJxkAakpFmU1uzX/fczTXu2PSQgbfyqeELp+ukyffrN5OUL6F5h6IGwzj9qo0AMxxvDTBEmVYw== X-Received: by 2002:a05:6870:1314:b0:d1:4902:c2ef with SMTP id 20-20020a056870131400b000d14902c2efmr5137012oab.191.1645230343711; Fri, 18 Feb 2022 16:25:43 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v5 07/12] target/riscv: Support mcycle/minstret write operation Date: Fri, 18 Feb 2022 16:25:13 -0800 Message-Id: <20220219002518.1936806-8-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220219002518.1936806-1-atishp@rivosinc.com> References: <20220219002518.1936806-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::c33 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c33; envelope-from=atishp@rivosinc.com; helo=mail-oo1-xc33.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645230933715100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Support mcycle/minstret through generic counter infrastructure. Signed-off-by: Atish Patra Signed-off-by: Atish Patra Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 23 +++++-- target/riscv/csr.c | 145 +++++++++++++++++++++++++++------------ target/riscv/machine.c | 25 ++++++- target/riscv/meson.build | 1 + target/riscv/pmu.c | 32 +++++++++ target/riscv/pmu.h | 28 ++++++++ 6 files changed, 201 insertions(+), 53 deletions(-) create mode 100644 target/riscv/pmu.c create mode 100644 target/riscv/pmu.h diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cce5c3538c89..68522acda4d2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -109,7 +109,7 @@ typedef struct CPURISCVState CPURISCVState; #endif =20 #define RV_VLEN_MAX 1024 -#define RV_MAX_MHPMEVENTS 29 +#define RV_MAX_MHPMEVENTS 32 #define RV_MAX_MHPMCOUNTERS 32 =20 FIELD(VTYPE, VLMUL, 0, 3) @@ -119,6 +119,18 @@ FIELD(VTYPE, VMA, 7, 1) FIELD(VTYPE, VEDIV, 8, 2) FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) =20 +typedef struct PMUCTRState { + /* Current value of a counter */ + target_ulong mhpmcounter_val; + /* Current value of a counter in RV32*/ + target_ulong mhpmcounterh_val; + /* Snapshot values of counter */ + target_ulong mhpmcounter_prev; + /* Snapshort value of a counter in RV32 */ + target_ulong mhpmcounterh_prev; + bool started; +} PMUCTRState; + struct CPURISCVState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ @@ -263,13 +275,10 @@ struct CPURISCVState { =20 target_ulong mcountinhibit; =20 - /* PMU counter configured values */ - target_ulong mhpmcounter_val[RV_MAX_MHPMCOUNTERS]; - - /* for RV32 */ - target_ulong mhpmcounterh_val[RV_MAX_MHPMCOUNTERS]; + /* PMU counter state */ + PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; =20 - /* PMU event selector configured values */ + /* PMU event selector configured values. First three are unused*/ target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; =20 target_ulong sscratch; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index dbb723a3307b..dc4d258205b3 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" +#include "pmu.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" =20 @@ -539,39 +540,33 @@ static int write_vcsr(CPURISCVState *env, int csrno, = target_ulong val) } =20 /* User Timers and Counters */ -static RISCVException read_instret(CPURISCVState *env, int csrno, - target_ulong *val) +static target_ulong get_icount_ticks(bool rv32) { + int64_t val; + target_ulong result; + #if !defined(CONFIG_USER_ONLY) if (icount_enabled()) { - *val =3D icount_get(); + val =3D icount_get(); } else { - *val =3D cpu_get_host_ticks(); + val =3D cpu_get_host_ticks(); } #else - *val =3D cpu_get_host_ticks(); + val =3D cpu_get_host_ticks(); #endif - return RISCV_EXCP_NONE; -} =20 -static RISCVException read_instreth(CPURISCVState *env, int csrno, - target_ulong *val) -{ -#if !defined(CONFIG_USER_ONLY) - if (icount_enabled()) { - *val =3D icount_get() >> 32; + if (rv32) { + result =3D val >> 32; } else { - *val =3D cpu_get_host_ticks() >> 32; + result =3D val; } -#else - *val =3D cpu_get_host_ticks() >> 32; -#endif - return RISCV_EXCP_NONE; + + return result; } =20 static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) { - int evt_index =3D csrno - CSR_MHPMEVENT3; + int evt_index =3D csrno - CSR_MCOUNTINHIBIT; =20 *val =3D env->mhpmevent_val[evt_index]; =20 @@ -580,7 +575,7 @@ static int read_mhpmevent(CPURISCVState *env, int csrno= , target_ulong *val) =20 static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val) { - int evt_index =3D csrno - CSR_MHPMEVENT3; + int evt_index =3D csrno - CSR_MCOUNTINHIBIT; =20 env->mhpmevent_val[evt_index] =3D val; =20 @@ -589,52 +584,102 @@ static int write_mhpmevent(CPURISCVState *env, int c= srno, target_ulong val) =20 static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong v= al) { - int ctr_index =3D csrno - CSR_MHPMCOUNTER3 + 3; + int ctr_idx =3D csrno - CSR_MCYCLE; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; =20 - env->mhpmcounter_val[ctr_index] =3D val; + counter->mhpmcounter_val =3D val; + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + counter->mhpmcounter_prev =3D get_icount_ticks(false); + } else { + /* Other counters can keep incrementing from the given value */ + counter->mhpmcounter_prev =3D val; + } =20 return RISCV_EXCP_NONE; } =20 static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong = val) { - int ctr_index =3D csrno - CSR_MHPMCOUNTER3H + 3; + int ctr_idx =3D csrno - CSR_MCYCLEH; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; =20 - env->mhpmcounterh_val[ctr_index] =3D val; + counter->mhpmcounterh_val =3D val; + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + counter->mhpmcounterh_prev =3D get_icount_ticks(true); + } else { + counter->mhpmcounterh_prev =3D val; + } + + return RISCV_EXCP_NONE; +} + +static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong = *val, + bool upper_half, uint32_t ctr_idx) +{ + PMUCTRState counter =3D env->pmu_ctrs[ctr_idx]; + target_ulong ctr_prev =3D upper_half ? counter.mhpmcounterh_prev : + counter.mhpmcounter_prev; + target_ulong ctr_val =3D upper_half ? counter.mhpmcounterh_val : + counter.mhpmcounter_val; + + if (get_field(env->mcountinhibit, BIT(ctr_idx))) { + /** + * Counter should not increment if inhibit bit is set. We can't re= ally + * stop the icount counting. Just return the counter value written= by + * the supervisor to indicate that counter was not incremented. + */ + if (!counter.started) { + *val =3D ctr_val; + return RISCV_EXCP_NONE; + } else { + /* Mark that the counter has been stopped */ + counter.started =3D false; + } + } + + + /** + * The kernel computes the perf delta by subtracting the current value= from + * the value it initialized previously (ctr_val). + */ + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + *val =3D get_icount_ticks(upper_half) - ctr_prev + ctr_val; + } else { + *val =3D ctr_val; + } =20 return RISCV_EXCP_NONE; } =20 static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *va= l) { - int ctr_index; + uint16_t ctr_index; =20 if (env->priv =3D=3D PRV_M) { - ctr_index =3D csrno - CSR_MHPMCOUNTER3 + 3; + ctr_index =3D csrno - CSR_MCYCLE; } else { - ctr_index =3D csrno - CSR_HPMCOUNTER3 + 3; + ctr_index =3D csrno - CSR_CYCLE; } - *val =3D env->mhpmcounter_val[ctr_index]; =20 - return RISCV_EXCP_NONE; + return riscv_pmu_read_ctr(env, val, false, ctr_index); } =20 static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *v= al) { - int ctr_index; + uint16_t ctr_index; =20 if (env->priv =3D=3D PRV_M) { - ctr_index =3D csrno - CSR_MHPMCOUNTER3H + 3; + ctr_index =3D csrno - CSR_MCYCLEH; } else { - ctr_index =3D csrno - CSR_HPMCOUNTER3H + 3; + ctr_index =3D csrno - CSR_CYCLEH; } =20 - *val =3D env->mhpmcounterh_val[ctr_index]; - - return RISCV_EXCP_NONE; + return riscv_pmu_read_ctr(env, val, true, ctr_index); } =20 - #if defined(CONFIG_USER_ONLY) static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) @@ -1468,11 +1513,23 @@ static RISCVException read_mcountinhibit(CPURISCVSt= ate *env, int csrno, static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno, target_ulong val) { + int cidx; + PMUCTRState *counter; + if (env->priv_ver < PRIV_VERSION_1_11_0) { return RISCV_EXCP_ILLEGAL_INST; } =20 env->mcountinhibit =3D val; + + /* Check if any other counter is also monitoring cycles/instructions */ + for (cidx =3D 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) { + if (!get_field(env->mcountinhibit, BIT(cidx))) { + counter =3D &env->pmu_ctrs[cidx]; + counter->started =3D true; + } + } + return RISCV_EXCP_NONE; } =20 @@ -3347,10 +3404,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_VLENB] =3D { "vlenb", vs, read_vlenb, .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, /* User Timers and Counters */ - [CSR_CYCLE] =3D { "cycle", ctr, read_instret }, - [CSR_INSTRET] =3D { "instret", ctr, read_instret }, - [CSR_CYCLEH] =3D { "cycleh", ctr32, read_instreth }, - [CSR_INSTRETH] =3D { "instreth", ctr32, read_instreth }, + [CSR_CYCLE] =3D { "cycle", ctr, read_hpmcounter }, + [CSR_INSTRET] =3D { "instret", ctr, read_hpmcounter }, + [CSR_CYCLEH] =3D { "cycleh", ctr32, read_hpmcounterh }, + [CSR_INSTRETH] =3D { "instreth", ctr32, read_hpmcounterh }, =20 /* * In privileged mode, the monitor will have to emulate TIME CSRs only= if @@ -3361,10 +3418,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 #if !defined(CONFIG_USER_ONLY) /* Machine Timers and Counters */ - [CSR_MCYCLE] =3D { "mcycle", any, read_instret }, - [CSR_MINSTRET] =3D { "minstret", any, read_instret }, - [CSR_MCYCLEH] =3D { "mcycleh", any32, read_instreth }, - [CSR_MINSTRETH] =3D { "minstreth", any32, read_instreth }, + [CSR_MCYCLE] =3D { "mcycle", any, read_hpmcounter, write_mhpmc= ounter}, + [CSR_MINSTRET] =3D { "minstret", any, read_hpmcounter, write_mhpmc= ounter}, + [CSR_MCYCLEH] =3D { "mcycleh", any32, read_hpmcounterh, write_mhpm= counterh}, + [CSR_MINSTRETH] =3D { "minstreth", any32, read_hpmcounterh, write_mhpm= counterh}, =20 /* Machine Information Registers */ [CSR_MVENDORID] =3D { "mvendorid", any, read_zero }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 042d655ce3ef..1f2186935666 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -248,7 +248,28 @@ static const VMStateDescription vmstate_envcfg =3D { VMSTATE_UINT64(env.menvcfg, RISCVCPU), VMSTATE_UINTTL(env.senvcfg, RISCVCPU), VMSTATE_UINT64(env.henvcfg, RISCVCPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool pmu_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; =20 + return cpu->cfg.pmu_num; +} + +static const VMStateDescription vmstate_pmu_ctr_state =3D { + .name =3D "cpu/pmu", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pmu_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState), + VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState), + VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState), + VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState), + VMSTATE_BOOL(started, PMUCTRState), VMSTATE_END_OF_LIST() } }; @@ -300,8 +321,8 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINTTL(env.mcounteren, RISCVCPU), VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), - VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU, RV_MAX_MHPMCOU= NTERS), - VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU, RV_MAX_MHPMCO= UNTERS), + VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, = 0, + vmstate_pmu_ctr_state, PMUCTRState), VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENT= S), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 91f0ac32ff3d..b41967b8c54a 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -27,6 +27,7 @@ riscv_softmmu_ss =3D ss.source_set() riscv_softmmu_ss.add(files( 'arch_dump.c', 'pmp.c', + 'pmu.c', 'monitor.c', 'machine.c' )) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c new file mode 100644 index 000000000000..000fe8da45ef --- /dev/null +++ b/target/riscv/pmu.c @@ -0,0 +1,32 @@ +/* + * RISC-V PMU file. + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "pmu.h" + +bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, + uint32_t target_ctr) +{ + return (target_ctr =3D=3D 0) ? true : false; +} + +bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr) +{ + return (target_ctr =3D=3D 2) ? true : false; +} diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h new file mode 100644 index 000000000000..58a5bc3a4089 --- /dev/null +++ b/target/riscv/pmu.h @@ -0,0 +1,28 @@ +/* + * RISC-V PMU header file. + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "cpu.h" +#include "qemu/main-loop.h" +#include "exec/exec-all.h" + +bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, + uint32_t target_ctr); +bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, + uint32_t target_ctr); --=20 2.30.2