From nobody Mon May 20 18:24:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645217143033596.2283992562704; Fri, 18 Feb 2022 12:45:43 -0800 (PST) Received: from localhost ([::1]:44188 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nLA8L-00074z-WD for importer@patchew.org; Fri, 18 Feb 2022 15:45:42 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58628) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nLA5q-00058t-Iw; Fri, 18 Feb 2022 15:43:06 -0500 Received: from [2a00:1450:4864:20::434] (port=41772 helo=mail-wr1-x434.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nLA5o-000063-Qi; Fri, 18 Feb 2022 15:43:06 -0500 Received: by mail-wr1-x434.google.com with SMTP id k1so16438484wrd.8; Fri, 18 Feb 2022 12:43:04 -0800 (PST) Received: from liavpc.localdomain ([2a10:800a:bb8:1:6510:42ac:bb55:9590]) by smtp.gmail.com with ESMTPSA id n19-20020a05600c4f9300b0037c06fe68casm377432wmq.44.2022.02.18.12.43.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Feb 2022 12:43:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HDIlYI/W0faEv1G28vO/TmPpURrrx1fyNxxtqZhHZ0s=; b=YcDWoavDqqpw4MrvzMj8shl/nCPDeSglPmbeW9IcLmEpqUNKSfK0qnuHgxmFi9jkWW nFNfl45yqo0qUiMVZRI9/ajM/DN+d8fZWnsPrXHyrZUiNjZtiJ+M96TwG24Ha2NPOesR Xx3i8wuwrLeab1MxeMz9qkXcP5WCS1YhRuXf2mxUEfkxxqkoLVpkvOxz7pCshEd8CtSa 7mAipYmbJndIhxnJMfWd8nsoJIs9m9U5oDSfppBdwHSKEwUnEKueCdYtIBJS5jHvFJU7 u0AptFGBXRmAsSv7piNBK/2VKn0oWn1nneN+pgUuUiRJ/i1ro+Gi40VwrjTnNt7s08q6 dcHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HDIlYI/W0faEv1G28vO/TmPpURrrx1fyNxxtqZhHZ0s=; b=s6h9PS4YU2TtjvOtIVapXgmcnKCw5F/GnIpoxTzTX5ekumoAEzsDXQb7svKjcm9TDb yCilAR2dZEhCMjmMRe/uV2goTbH7lEChBYrxbb2UVDGGSln15dNHWo8ZJKN4COrbCI6K PvYdvNP5ajB9F3hkvvE5UlIUBPvQaX0x3jg/XoA+dkeyuAcGrJsQGtxTq5S5hz8t5UIv 4qYwOEAxRCKWX06MCGq6fhLzFqRcgKKElyAmgDVA+l+7O4AE3ZlBnB6V4lH11RUCFsCA WkkuSRrctsogboGhwvUV9EHyeQNI2iPKXgTGDFwTy6Uw6HM5UpIDvV6uOq/HIFsoTfvf NZcA== X-Gm-Message-State: AOAM530tbJ28TDZ3Z+/im8FPzsi0zEpGybs5YL4O4zAyhmyHU8GB6sOl 88RffM2w+PrIua3SxSt5z2Lu6NlTcKw= X-Google-Smtp-Source: ABdhPJxAV6cnIPJT/KDg3MZKT8/ZzcI+ZgN/1mdWoj7POwngrz4MwHxJyMw3CKqBaoH9ta2rJQu5xA== X-Received: by 2002:a05:6000:1081:b0:1e3:16d0:1c47 with SMTP id y1-20020a056000108100b001e316d01c47mr7408654wrw.19.1645216982679; Fri, 18 Feb 2022 12:43:02 -0800 (PST) From: Liav Albani To: qemu-devel@nongnu.org Subject: [PATCH v2 1/2] hw/ide: split bmdma read and write functions from piix.c Date: Fri, 18 Feb 2022 22:41:54 +0200 Message-Id: <20220218204155.236611-2-liavalb@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220218204155.236611-1-liavalb@gmail.com> References: <20220218204155.236611-1-liavalb@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::434 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=liavalb@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jsnow@redhat.com, Liav Albani , qemu-block@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645217144679100001 Content-Type: text/plain; charset="utf-8" This is a preparation before implementing another PCI IDE controller that relies on these functions, so these can be shared between both implementations. Signed-off-by: Liav Albani --- hw/ide/bmdma.c | 84 ++++++++++++++++++++++++++++++++++++++++++ hw/ide/meson.build | 2 +- hw/ide/piix.c | 51 ++----------------------- include/hw/ide/bmdma.h | 34 +++++++++++++++++ 4 files changed, 122 insertions(+), 49 deletions(-) create mode 100644 hw/ide/bmdma.c create mode 100644 include/hw/ide/bmdma.h diff --git a/hw/ide/bmdma.c b/hw/ide/bmdma.c new file mode 100644 index 0000000000..d12ed730dd --- /dev/null +++ b/hw/ide/bmdma.c @@ -0,0 +1,84 @@ +/* + * QEMU IDE Emulation: Intel PCI Bus master IDE support for PIIX3/4 and IC= H6/7. + * + * Copyright (c) 2003 Fabrice Bellard + * Copyright (c) 2006 Openedhand Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/pci/pci.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "sysemu/block-backend.h" +#include "sysemu/blockdev.h" +#include "sysemu/dma.h" + +#include "hw/ide/bmdma.h" +#include "hw/ide/pci.h" +#include "trace.h" + +uint64_t intel_ide_bmdma_read(void *opaque, hwaddr addr, unsigned size) +{ + BMDMAState *bm =3D opaque; + uint32_t val; + + if (size !=3D 1) { + return ((uint64_t)1 << (size * 8)) - 1; + } + + switch (addr & 3) { + case 0: + val =3D bm->cmd; + break; + case 2: + val =3D bm->status; + break; + default: + val =3D 0xff; + break; + } + + trace_bmdma_read(addr, val); + return val; +} + +void intel_ide_bmdma_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + BMDMAState *bm =3D opaque; + + if (size !=3D 1) { + return; + } + + trace_bmdma_write(addr, val); + + switch (addr & 3) { + case 0: + bmdma_cmd_writeb(bm, val); + break; + case 2: + uint8_t cur_val =3D bm->status; + bm->status =3D (val & 0x60) | (cur_val & 1) | (cur_val & ~val & 0x= 06); + break; + } +} diff --git a/hw/ide/meson.build b/hw/ide/meson.build index ddcb3b28d2..38f9ae7178 100644 --- a/hw/ide/meson.build +++ b/hw/ide/meson.build @@ -7,7 +7,7 @@ softmmu_ss.add(when: 'CONFIG_IDE_ISA', if_true: files('isa.= c', 'ioport.c')) softmmu_ss.add(when: 'CONFIG_IDE_MACIO', if_true: files('macio.c')) softmmu_ss.add(when: 'CONFIG_IDE_MMIO', if_true: files('mmio.c')) softmmu_ss.add(when: 'CONFIG_IDE_PCI', if_true: files('pci.c')) -softmmu_ss.add(when: 'CONFIG_IDE_PIIX', if_true: files('piix.c', 'ioport.c= ')) +softmmu_ss.add(when: 'CONFIG_IDE_PIIX', if_true: files('piix.c', 'ioport.c= ', 'bmdma.c')) softmmu_ss.add(when: 'CONFIG_IDE_QDEV', if_true: files('qdev.c')) softmmu_ss.add(when: 'CONFIG_IDE_SII3112', if_true: files('sii3112.c')) softmmu_ss.add(when: 'CONFIG_IDE_VIA', if_true: files('via.c')) diff --git a/hw/ide/piix.c b/hw/ide/piix.c index ce89fd0aa3..8f94809eee 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -33,57 +33,12 @@ #include "sysemu/dma.h" =20 #include "hw/ide/pci.h" +#include "hw/ide/bmdma.h" #include "trace.h" =20 -static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size) -{ - BMDMAState *bm =3D opaque; - uint32_t val; - - if (size !=3D 1) { - return ((uint64_t)1 << (size * 8)) - 1; - } - - switch(addr & 3) { - case 0: - val =3D bm->cmd; - break; - case 2: - val =3D bm->status; - break; - default: - val =3D 0xff; - break; - } - - trace_bmdma_read(addr, val); - return val; -} - -static void bmdma_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - BMDMAState *bm =3D opaque; - - if (size !=3D 1) { - return; - } - - trace_bmdma_write(addr, val); - - switch(addr & 3) { - case 0: - bmdma_cmd_writeb(bm, val); - break; - case 2: - bm->status =3D (val & 0x60) | (bm->status & 1) | (bm->status & ~va= l & 0x06); - break; - } -} - static const MemoryRegionOps piix_bmdma_ops =3D { - .read =3D bmdma_read, - .write =3D bmdma_write, + .read =3D intel_ide_bmdma_read, + .write =3D intel_ide_bmdma_write, }; =20 static void bmdma_setup_bar(PCIIDEState *d) diff --git a/include/hw/ide/bmdma.h b/include/hw/ide/bmdma.h new file mode 100644 index 0000000000..ce76d395f5 --- /dev/null +++ b/include/hw/ide/bmdma.h @@ -0,0 +1,34 @@ +/* + * QEMU IDE Emulation: Intel PCI Bus master IDE support for PIIX3/4 and IC= H6/7. + * + * Copyright (c) 2022 Liav Albani + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_IDE_BMDMA_H +#define HW_IDE_BMDMA_H + +#include "hw/ide/internal.h" + +uint64_t intel_ide_bmdma_read(void *opaque, hwaddr addr, unsigned size); +void intel_ide_bmdma_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size); + +#endif --=20 2.35.1 From nobody Mon May 20 18:24:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645217262100777.2833207400895; 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Fri, 18 Feb 2022 12:43:21 -0800 (PST) From: Liav Albani To: qemu-devel@nongnu.org Subject: [PATCH v2 2/2] hw/ide: add ich6 ide controller device emulation Date: Fri, 18 Feb 2022 22:41:55 +0200 Message-Id: <20220218204155.236611-3-liavalb@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220218204155.236611-1-liavalb@gmail.com> References: <20220218204155.236611-1-liavalb@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::431 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=liavalb@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jsnow@redhat.com, Liav Albani , qemu-block@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645217263502100001 Content-Type: text/plain; charset="utf-8" This type of IDE controller has support for relocating the IO ports and doesn't use IRQ 14 and 15 but one allocated PCI IRQ for the controller. There's no x86 chipset in QEMU that will try to attach this device by default. It is considered a legacy-free device in the aspect of PCI bus resource management as the guest OS can relocate the IO ports as it sees fit to its needs. However, this is still a legacy device that belongs to chipsets from late 2000s. Signed-off-by: Liav Albani --- hw/i386/Kconfig | 2 + hw/ide/Kconfig | 5 + hw/ide/ich6.c | 204 +++++++++++++++++++++++++++++++++++++++ hw/ide/meson.build | 1 + include/hw/ide/pci.h | 1 + include/hw/pci/pci_ids.h | 1 + 6 files changed, 214 insertions(+) create mode 100644 hw/ide/ich6.c diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index d22ac4a4b9..a18de2d962 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -75,6 +75,7 @@ config I440FX select PCI_I440FX select PIIX3 select IDE_PIIX + select IDE_ICH6 select DIMM select SMBIOS select FW_CFG_DMA @@ -101,6 +102,7 @@ config Q35 select PCI_EXPRESS_Q35 select LPC_ICH9 select AHCI_ICH9 + select IDE_ICH6 select DIMM select SMBIOS select FW_CFG_DMA diff --git a/hw/ide/Kconfig b/hw/ide/Kconfig index dd85fa3619..63304325a5 100644 --- a/hw/ide/Kconfig +++ b/hw/ide/Kconfig @@ -38,6 +38,11 @@ config IDE_VIA select IDE_PCI select IDE_QDEV =20 +config IDE_ICH6 + bool + select IDE_PCI + select IDE_QDEV + config MICRODRIVE bool select IDE_QDEV diff --git a/hw/ide/ich6.c b/hw/ide/ich6.c new file mode 100644 index 0000000000..8f46d3fce2 --- /dev/null +++ b/hw/ide/ich6.c @@ -0,0 +1,204 @@ +/* + * QEMU IDE Emulation: PCI ICH6/ICH7 IDE support. + * + * Copyright (c) 2022 Liav Albani + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/pci/pci.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "sysemu/block-backend.h" +#include "sysemu/blockdev.h" +#include "sysemu/dma.h" + +#include "hw/ide/pci.h" +#include "hw/ide/bmdma.h" +#include "trace.h" + +static const MemoryRegionOps ich6_bmdma_ops =3D { + .read =3D intel_ide_bmdma_read, + .write =3D intel_ide_bmdma_write, +}; + +static void bmdma_setup_bar(PCIIDEState *d) +{ + int i; + + memory_region_init(&d->bmdma_bar, OBJECT(d), "ich6-bmdma-container", 1= 6); + for (i =3D 0; i < 2; i++) { + BMDMAState *bm =3D &d->bmdma[i]; + + memory_region_init_io(&bm->extra_io, OBJECT(d), &ich6_bmdma_ops, b= m, + "ich6-bmdma", 4); + memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); + memory_region_init_io(&bm->addr_ioport, OBJECT(d), + &bmdma_addr_ioport_ops, bm, "bmdma", 4); + memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_io= port); + } +} + +static void ich6_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t va= l, + int l) +{ + uint32_t i; + + pci_default_write_config(d, addr, val, l); + + for (i =3D addr; i < addr + l; i++) { + switch (i) { + case 0x40: + pci_default_write_config(d, i, 0x8000, 2); + continue; + case 0x42: + pci_default_write_config(d, i, 0x8000, 2); + continue; + } + } +} + +static void ich6_ide_reset(DeviceState *dev) +{ + PCIIDEState *d =3D PCI_IDE(dev); + PCIDevice *pd =3D PCI_DEVICE(d); + uint8_t *pci_conf =3D pd->config; + int i; + + for (i =3D 0; i < 2; i++) { + ide_bus_reset(&d->bus[i]); + } + + /* TODO: this is the default. do not override. */ + pci_conf[PCI_COMMAND] =3D 0x00; + /* TODO: this is the default. do not override. */ + pci_conf[PCI_COMMAND + 1] =3D 0x00; + /* TODO: use pci_set_word */ + pci_conf[PCI_STATUS] =3D PCI_STATUS_FAST_BACK; + pci_conf[PCI_STATUS + 1] =3D PCI_STATUS_DEVSEL_MEDIUM >> 8; + pci_conf[0x20] =3D 0x01; /* BMIBA: 20-23h */ +} + +static int pci_ich6_init_ports(PCIIDEState *d) +{ + int i; + + for (i =3D 0; i < 2; i++) { + ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); + ide_init2(&d->bus[i], d->native_irq); + + bmdma_init(&d->bus[i], &d->bmdma[i], d); + d->bmdma[i].bus =3D &d->bus[i]; + ide_register_restart_cb(&d->bus[i]); + } + + return 0; +} + +static void pci_ich6_ide_realize(PCIDevice *dev, Error **errp) +{ + PCIIDEState *d =3D PCI_IDE(dev); + uint8_t *pci_conf =3D dev->config; + int rc; + + pci_conf[PCI_INTERRUPT_PIN] =3D 1; /* interrupt pin A */ + + /* PCI native mode-only controller, supports bus mastering */ + pci_conf[PCI_CLASS_PROG] =3D 0x85; + + bmdma_setup_bar(d); + pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); + + d->native_irq =3D pci_allocate_irq(&d->parent_obj); + /* Address Map Register - Non Combined Mode, MAP.USCC =3D 0 */ + pci_conf[0x90] =3D 0; + + /* IDE Decode enabled by default */ + pci_set_long(pci_conf + 0x40, 0x80008000); + + /* IDE Timing control - Disable UDMA controls */ + pci_set_long(pci_conf + 0x48, 0x00000000); + + vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d); + + memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops, + &d->bus[0], "ich6-ide0-data", 8); + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]); + + memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops, + &d->bus[0], "ich6-ide0-cmd", 4); + pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]); + + memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops, + &d->bus[1], "ich6-ide1-data", 8); + pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]); + + memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops, + &d->bus[1], "ich6-ide1-cmd", 4); + pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]); + + rc =3D pci_ich6_init_ports(d); + if (rc) { + error_setg_errno(errp, -rc, "Failed to realize %s", + object_get_typename(OBJECT(dev))); + } +} + +static void pci_ich6_ide_exitfn(PCIDevice *dev) +{ + PCIIDEState *d =3D PCI_IDE(dev); + unsigned i; + + for (i =3D 0; i < 2; ++i) { + memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); + memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_iopor= t); + } +} + +static void ich6_ide_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + dc->reset =3D ich6_ide_reset; + k->realize =3D pci_ich6_ide_realize; + k->exit =3D pci_ich6_ide_exitfn; + k->vendor_id =3D PCI_VENDOR_ID_INTEL; + k->device_id =3D PCI_DEVICE_ID_INTEL_82801GB; + k->class_id =3D PCI_CLASS_STORAGE_IDE; + k->config_read =3D pci_default_read_config; + k->config_write =3D ich6_pci_config_write; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); + dc->hotpluggable =3D false; +} + +static const TypeInfo ich6_ide_info =3D { + .name =3D "ich6-ide", + .parent =3D TYPE_PCI_IDE, + .class_init =3D ich6_ide_class_init, +}; + +static void ich6_ide_register_types(void) +{ + type_register_static(&ich6_ide_info); +} + +type_init(ich6_ide_register_types) diff --git a/hw/ide/meson.build b/hw/ide/meson.build index 38f9ae7178..6899e082db 100644 --- a/hw/ide/meson.build +++ b/hw/ide/meson.build @@ -1,5 +1,6 @@ softmmu_ss.add(when: 'CONFIG_AHCI', if_true: files('ahci.c')) softmmu_ss.add(when: 'CONFIG_AHCI_ICH9', if_true: files('ich.c')) +softmmu_ss.add(when: 'CONFIG_IDE_ICH6', if_true: files('ich6.c', 'bmdma.c'= )) softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('ahci-allwinne= r.c')) softmmu_ss.add(when: 'CONFIG_IDE_CMD646', if_true: files('cmd646.c')) softmmu_ss.add(when: 'CONFIG_IDE_CORE', if_true: files('core.c', 'atapi.c'= )) diff --git a/include/hw/ide/pci.h b/include/hw/ide/pci.h index d8384e1c42..d8bf08e728 100644 --- a/include/hw/ide/pci.h +++ b/include/hw/ide/pci.h @@ -53,6 +53,7 @@ struct PCIIDEState { MemoryRegion bmdma_bar; MemoryRegion cmd_bar[2]; MemoryRegion data_bar[2]; + qemu_irq native_irq; /* used only for ich6-ide */ }; =20 static inline IDEState *bmdma_active_if(BMDMAState *bmdma) diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h index 11abe22d46..cf8767977c 100644 --- a/include/hw/pci/pci_ids.h +++ b/include/hw/pci/pci_ids.h @@ -244,6 +244,7 @@ #define PCI_DEVICE_ID_INTEL_82371AB 0x7111 #define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 +#define PCI_DEVICE_ID_INTEL_82801GB 0x27c0 =20 #define PCI_DEVICE_ID_INTEL_ICH9_0 0x2910 #define PCI_DEVICE_ID_INTEL_ICH9_1 0x2917 --=20 2.35.1