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Fri, 18 Feb 2022 10:38:54 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B2C2611C077; Fri, 18 Feb 2022 10:38:54 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6FF3611C073; Fri, 18 Feb 2022 10:38:54 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with SMTP; Fri, 18 Feb 2022 10:38:54 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.87.94]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 9C2072201F1; Fri, 18 Feb 2022 11:38:53 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 36/39] target/ppc: cpu_init: Expose some SPR registration helpers Date: Fri, 18 Feb 2022 11:38:24 +0100 Message-Id: <20220218103827.682032-37-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220218103827.682032-1-clg@kaod.org> References: <20220218103827.682032-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: u0dPy_pPhZs_Cb1y80B13NdVtotfGcA_ X-Proofpoint-GUID: u0dPy_pPhZs_Cb1y80B13NdVtotfGcA_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-18_04,2022-02-18_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 malwarescore=0 adultscore=0 mlxscore=0 spamscore=0 clxscore=1034 phishscore=0 suspectscore=0 mlxlogscore=797 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2202180067 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , David Gibson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645182243472100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas The following patches will move CPU-specific code into separate files, so expose the most used SPR registration functions: register_sdr1_sprs | 22 callers register_low_BATs | 20 callers register_non_embedded_sprs | 19 callers register_high_BATs | 10 callers register_thrm_sprs | 8 callers register_usprgh_sprs | 6 callers register_6xx_7xx_soft_tlb | only 3 callers, but it helps to keep the soft TLB code consistent. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson Message-Id: <20220216162426.1885923-25-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/spr_common.h | 8 ++++++++ target/ppc/cpu_init.c | 14 +++++++------- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h index 5aec76ade4dd..329b7e91a23a 100644 --- a/target/ppc/spr_common.h +++ b/target/ppc/spr_common.h @@ -141,4 +141,12 @@ void spr_write_hmer(DisasContext *ctx, int sprn, int g= prn); void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn); #endif =20 +void register_low_BATs(CPUPPCState *env); +void register_high_BATs(CPUPPCState *env); +void register_sdr1_sprs(CPUPPCState *env); +void register_thrm_sprs(CPUPPCState *env); +void register_usprgh_sprs(CPUPPCState *env); +void register_non_embedded_sprs(CPUPPCState *env); +void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways); + #endif diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index f0bbe340e4fd..40dd2c0fd813 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -241,7 +241,7 @@ static void register_generic_sprs(PowerPCCPU *cpu) 0x00000000); } =20 -static void register_non_embedded_sprs(CPUPPCState *env) +void register_non_embedded_sprs(CPUPPCState *env) { /* Exception processing */ spr_register_kvm(env, SPR_DSISR, "DSISR", @@ -260,7 +260,7 @@ static void register_non_embedded_sprs(CPUPPCState *env) } =20 /* Storage Description Register 1 */ -static void register_sdr1_sprs(CPUPPCState *env) +void register_sdr1_sprs(CPUPPCState *env) { #ifndef CONFIG_USER_ONLY if (env->has_hv_mode) { @@ -283,7 +283,7 @@ static void register_sdr1_sprs(CPUPPCState *env) } =20 /* BATs 0-3 */ -static void register_low_BATs(CPUPPCState *env) +void register_low_BATs(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) spr_register(env, SPR_IBAT0U, "IBAT0U", @@ -355,7 +355,7 @@ static void register_low_BATs(CPUPPCState *env) } =20 /* BATs 4-7 */ -static void register_high_BATs(CPUPPCState *env) +void register_high_BATs(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) spr_register(env, SPR_IBAT4U, "IBAT4U", @@ -427,7 +427,7 @@ static void register_high_BATs(CPUPPCState *env) } =20 /* Softare table search registers */ -static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int n= b_ways) +void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) { #if !defined(CONFIG_USER_ONLY) env->nb_tlb =3D nb_tlbs; @@ -667,7 +667,7 @@ static void register_iamr_sprs(CPUPPCState *env) } #endif /* TARGET_PPC64 */ =20 -static void register_thrm_sprs(CPUPPCState *env) +void register_thrm_sprs(CPUPPCState *env) { /* Thermal management */ spr_register(env, SPR_THRM1, "THRM1", @@ -1072,7 +1072,7 @@ static void register_l3_ctrl(CPUPPCState *env) 0x00000000); } =20 -static void register_usprgh_sprs(CPUPPCState *env) +void register_usprgh_sprs(CPUPPCState *env) { spr_register(env, SPR_USPRG4, "USPRG4", &spr_read_ureg, SPR_NOACCESS, --=20 2.34.1