From nobody Fri Sep 26 16:54:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645120578985433.84979528937674; Thu, 17 Feb 2022 09:56:18 -0800 (PST) Received: from localhost ([::1]:34852 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKl0s-0005ko-0O for importer@patchew.org; Thu, 17 Feb 2022 12:56:18 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36054) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKksF-00026r-VG; Thu, 17 Feb 2022 12:47:23 -0500 Received: from mga12.intel.com ([192.55.52.136]:31708) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKksD-0007HN-B4; Thu, 17 Feb 2022 12:47:23 -0500 Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Feb 2022 09:47:06 -0800 Received: from lmaniak-dev.igk.intel.com ([10.55.249.72]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Feb 2022 09:47:04 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645120041; x=1676656041; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4RWut82NF1JDOsZUszAaYqR2Q8Cp66jU/U9OsLBJ27w=; b=Yeg91p+Qm4Sp8J+4ueo7asbFhc0rOxhDoi15qL5BmVcLcsspLG9p5quM gyRlzxehR7KWxr9La95QFuwlXwyRxlMQWBGAGQzVyTfyRjLCp3pB3ZDa2 9nUY8Vq6kJH/w9QWFgIZAvVv+OgSKQwVQ3eAoGNTR3XduyDo4VvnUu/XZ iXHpsFkR9jufJJywQdEbxjhD97vvqDKoi5LCooZ9oAa2AcBNP/Z/SKNFl /JApzgpyrR3lDus9QJnxWkBfCtLZ1g179jjrk89RQjm/JDSZc1FZi5qFu yAfBwPbz7NYF/QH+v04DHTA8uNq9/FVK7dhEaPHgJFgtArMHv1q05FzeR Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10261"; a="230894083" X-IronPort-AV: E=Sophos;i="5.88,376,1635231600"; d="scan'208";a="230894083" X-IronPort-AV: E=Sophos;i="5.88,376,1635231600"; d="scan'208";a="545746169" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH v5 08/15] hw/nvme: Implement the Function Level Reset Date: Thu, 17 Feb 2022 18:44:57 +0100 Message-Id: <20220217174504.1051716-9-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220217174504.1051716-1-lukasz.maniak@linux.intel.com> References: <20220217174504.1051716-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.136; envelope-from=lukasz.maniak@linux.intel.com; helo=mga12.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-block@nongnu.org, Klaus Jensen , Lukasz Maniak , Keith Busch , =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645120579691100001 From: =C5=81ukasz Gieryk This patch implements the Function Level Reset, a feature currently not implemented for the Nvme device, while listed as a mandatory ("shall") in the 1.4 spec. The implementation reuses FLR-related building blocks defined for the pci-bridge module, and follows the same logic: - FLR capability is advertised in the PCIE config, - custom pci_write_config callback detects a write to the trigger register and performs the PCI reset, - which, eventually, calls the custom dc->reset handler. Depending on reset type, parts of the state should (or should not) be cleared. To distinguish the type of reset, an additional parameter is passed to the reset function. This patch also enables advertisement of the Power Management PCI capability. The main reason behind it is to announce the no_soft_reset=3D1 bit, to signal SR-IOV support where each VF can be reset individually. The implementation purposedly ignores writes to the PMCS.PS register, as even such na=C3=AFve behavior is enough to correctly handle the D3->D0 transition. It=E2=80=99s worth to note, that the power state transition back to to D3, = with all the corresponding side effects, wasn't and stil isn't handled properly. Signed-off-by: =C5=81ukasz Gieryk Reviewed-by: Klaus Jensen --- hw/nvme/ctrl.c | 52 ++++++++++++++++++++++++++++++++++++++++---- hw/nvme/nvme.h | 5 +++++ hw/nvme/trace-events | 1 + 3 files changed, 54 insertions(+), 4 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 05acd681656..7c1dd80f21d 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -5757,7 +5757,7 @@ static void nvme_process_sq(void *opaque) } } =20 -static void nvme_ctrl_reset(NvmeCtrl *n) +static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType rst) { NvmeNamespace *ns; int i; @@ -5789,7 +5789,9 @@ static void nvme_ctrl_reset(NvmeCtrl *n) } =20 if (!pci_is_vf(&n->parent_obj) && n->params.sriov_max_vfs) { - pcie_sriov_pf_disable_vfs(&n->parent_obj); + if (rst !=3D NVME_RESET_CONTROLLER) { + pcie_sriov_pf_disable_vfs(&n->parent_obj); + } } =20 n->aer_queued =3D 0; @@ -6023,7 +6025,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset= , uint64_t data, } } else if (!NVME_CC_EN(data) && NVME_CC_EN(cc)) { trace_pci_nvme_mmio_stopped(); - nvme_ctrl_reset(n); + nvme_ctrl_reset(n, NVME_RESET_CONTROLLER); cc =3D 0; csts &=3D ~NVME_CSTS_READY; } @@ -6581,6 +6583,28 @@ static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *= pci_dev, uint16_t offset, PCI_BASE_ADDRESS_MEM_TYPE_64, bar_size); } =20 +static int nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset) +{ + Error *err =3D NULL; + int ret; + + ret =3D pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset, + PCI_PM_SIZEOF, &err); + if (err) { + error_report_err(err); + return ret; + } + + pci_set_word(pci_dev->config + offset + PCI_PM_PMC, + PCI_PM_CAP_VER_1_2); + pci_set_word(pci_dev->config + offset + PCI_PM_CTRL, + PCI_PM_CTRL_NO_SOFT_RESET); + pci_set_word(pci_dev->wmask + offset + PCI_PM_CTRL, + PCI_PM_CTRL_STATE_MASK); + + return 0; +} + static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) { uint8_t *pci_conf =3D pci_dev->config; @@ -6602,7 +6626,9 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_= dev, Error **errp) } =20 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS); + nvme_add_pm_capability(pci_dev, 0x60); pcie_endpoint_cap_init(pci_dev, 0x80); + pcie_cap_flr_init(pci_dev); if (n->params.sriov_max_vfs) { pcie_ari_init(pci_dev, 0x100, 1); } @@ -6852,7 +6878,7 @@ static void nvme_exit(PCIDevice *pci_dev) NvmeNamespace *ns; int i; =20 - nvme_ctrl_reset(n); + nvme_ctrl_reset(n, NVME_RESET_FUNCTION); =20 if (n->subsys) { for (i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { @@ -6951,6 +6977,22 @@ static void nvme_set_smart_warning(Object *obj, Visi= tor *v, const char *name, } } =20 +static void nvme_pci_reset(DeviceState *qdev) +{ + PCIDevice *pci_dev =3D PCI_DEVICE(qdev); + NvmeCtrl *n =3D NVME(pci_dev); + + trace_pci_nvme_pci_reset(); + nvme_ctrl_reset(n, NVME_RESET_FUNCTION); +} + +static void nvme_pci_write_config(PCIDevice *dev, uint32_t address, + uint32_t val, int len) +{ + pci_default_write_config(dev, address, val, len); + pcie_cap_flr_write_config(dev, address, val, len); +} + static const VMStateDescription nvme_vmstate =3D { .name =3D "nvme", .unmigratable =3D 1, @@ -6962,6 +7004,7 @@ static void nvme_class_init(ObjectClass *oc, void *da= ta) PCIDeviceClass *pc =3D PCI_DEVICE_CLASS(oc); =20 pc->realize =3D nvme_realize; + pc->config_write =3D nvme_pci_write_config; pc->exit =3D nvme_exit; pc->class_id =3D PCI_CLASS_STORAGE_EXPRESS; pc->revision =3D 2; @@ -6970,6 +7013,7 @@ static void nvme_class_init(ObjectClass *oc, void *da= ta) dc->desc =3D "Non-Volatile Memory Express"; device_class_set_props(dc, nvme_props); dc->vmsd =3D &nvme_vmstate; + dc->reset =3D nvme_pci_reset; } =20 static void nvme_instance_init(Object *obj) diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index f4494e5236f..5ba07b62dff 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -481,6 +481,11 @@ typedef struct NvmeCtrl { NvmeSecCtrlList sec_ctrl_list; } NvmeCtrl; =20 +typedef enum NvmeResetType { + NVME_RESET_FUNCTION =3D 0, + NVME_RESET_CONTROLLER =3D 1, +} NvmeResetType; + static inline NvmeNamespace *nvme_ns(NvmeCtrl *n, uint32_t nsid) { if (!nsid || nsid > NVME_MAX_NAMESPACES) { diff --git a/hw/nvme/trace-events b/hw/nvme/trace-events index 12afb8478a4..f8bf85fb78f 100644 --- a/hw/nvme/trace-events +++ b/hw/nvme/trace-events @@ -106,6 +106,7 @@ pci_nvme_zd_extension_set(uint32_t zone_idx) "set descr= iptor extension for zone_ pci_nvme_clear_ns_close(uint32_t state, uint64_t slba) "zone state=3D%"PRI= u32", slba=3D%"PRIu64" transitioned to Closed state" pci_nvme_clear_ns_reset(uint32_t state, uint64_t slba) "zone state=3D%"PRI= u32", slba=3D%"PRIu64" transitioned to Empty state" pci_nvme_zoned_zrwa_implicit_flush(uint64_t zslba, uint32_t nlb) "zslba 0x= %"PRIx64" nlb %"PRIu32"" +pci_nvme_pci_reset(void) "PCI Function Level Reset" =20 # error conditions pci_nvme_err_mdts(size_t len) "len %zu" --=20 2.25.1