From nobody Fri Sep 26 16:52:40 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645120441777324.4241969192025; Thu, 17 Feb 2022 09:54:01 -0800 (PST) Received: from localhost ([::1]:57962 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKkye-0002Jr-LP for importer@patchew.org; Thu, 17 Feb 2022 12:54:00 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36072) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKksH-0002C9-6r; Thu, 17 Feb 2022 12:47:25 -0500 Received: from mga12.intel.com ([192.55.52.136]:31716) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKksF-0007He-Bg; Thu, 17 Feb 2022 12:47:24 -0500 Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Feb 2022 09:47:10 -0800 Received: from lmaniak-dev.igk.intel.com ([10.55.249.72]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Feb 2022 09:47:08 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645120043; x=1676656043; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Znk2iSf74WV+7vjsxYUtwOrl4+ypIPQ/g9AWgnEKNSI=; b=cXH55862ctP/U0cfXdS49mpLlKust1Hn7w/eD1DKqcwSDrais7KGgXAP 6/Il6ZdSbbFCHQAdXh4hE535ILmgXLlOpLtmJXpue6sQjw2Gevp+sQAHc BMhiM/gxmmLjZfeWxHeCCUDCuPa+3+meawlXziZELdKBUIBvujUAimGvc dV14hwAeGCSZjNjUo2daF004psSDs2vnJm5UZOrXBRervnN9Ap7Ci+o23 rLXF4diS2hPqFBUxh7ZUjovsOV4EUiu2qGVKc2rs9SLwASTACUkQCvLd5 ieeKuwHEccpB+1AFsrZR+c/Cz87JaBGgbR+YZ8WtpCf5DtcHk8f4bRdEZ A==; X-IronPort-AV: E=McAfee;i="6200,9189,10261"; a="230894096" X-IronPort-AV: E=Sophos;i="5.88,376,1635231600"; d="scan'208";a="230894096" X-IronPort-AV: E=Sophos;i="5.88,376,1635231600"; d="scan'208";a="545746214" From: Lukasz Maniak To: qemu-devel@nongnu.org Subject: [PATCH v5 10/15] hw/nvme: Remove reg_size variable and update BAR0 size calculation Date: Thu, 17 Feb 2022 18:44:59 +0100 Message-Id: <20220217174504.1051716-11-lukasz.maniak@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220217174504.1051716-1-lukasz.maniak@linux.intel.com> References: <20220217174504.1051716-1-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.136; envelope-from=lukasz.maniak@linux.intel.com; helo=mga12.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-block@nongnu.org, Klaus Jensen , Lukasz Maniak , Keith Busch , =?UTF-8?q?=C5=81ukasz=20Gieryk?= , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645120442508100001 From: =C5=81ukasz Gieryk The n->reg_size parameter unnecessarily splits the BAR0 size calculation in two phases; removed to simplify the code. With all the calculations done in one place, it seems the pow2ceil, applied originally to reg_size, is unnecessary. The rounding should happen as the last step, when BAR size includes Nvme registers, queue registers, and MSIX-related space. Finally, the size of the mmio memory region is extended to cover the 1st 4KiB padding (see the map below). Access to this range is handled as interaction with a non-existing queue and generates an error trace, so actually nothing changes, while the reg_size variable is no longer needed. -------------------- | BAR0 | -------------------- [Nvme Registers ] [Queues ] [power-of-2 padding] - removed in this patch [4KiB padding (1) ] [MSIX TABLE ] [4KiB padding (2) ] [MSIX PBA ] [power-of-2 padding] Signed-off-by: =C5=81ukasz Gieryk Reviewed-by: Klaus Jensen --- hw/nvme/ctrl.c | 10 +++++----- hw/nvme/nvme.h | 1 - 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index f1b4026e4f8..6abec8e4369 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -6525,9 +6525,6 @@ static void nvme_init_state(NvmeCtrl *n) n->conf_ioqpairs =3D n->params.max_ioqpairs; n->conf_msix_qsize =3D n->params.msix_qsize; =20 - /* add one to max_ioqpairs to account for the admin queue pair */ - n->reg_size =3D pow2ceil(sizeof(NvmeBar) + - 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE= ); n->sq =3D g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1); n->cq =3D g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); n->temperature =3D NVME_TEMPERATURE; @@ -6651,7 +6648,10 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci= _dev, Error **errp) pcie_ari_init(pci_dev, 0x100, 1); } =20 - bar_size =3D QEMU_ALIGN_UP(n->reg_size, 4 * KiB); + /* add one to max_ioqpairs to account for the admin queue pair */ + bar_size =3D sizeof(NvmeBar) + + 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE; + bar_size =3D QEMU_ALIGN_UP(bar_size, 4 * KiB); msix_table_offset =3D bar_size; msix_table_size =3D PCI_MSIX_ENTRY_SIZE * n->params.msix_qsize; =20 @@ -6665,7 +6665,7 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_= dev, Error **errp) =20 memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size); memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", - n->reg_size); + msix_table_offset); memory_region_add_subregion(&n->bar0, 0, &n->iomem); =20 if (pci_is_vf(pci_dev)) { diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index 314a2894759..86b5b321331 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -424,7 +424,6 @@ typedef struct NvmeCtrl { uint16_t max_prp_ents; uint16_t cqe_size; uint16_t sqe_size; - uint32_t reg_size; uint32_t max_q_ents; uint8_t outstanding_aers; uint32_t irq_status; --=20 2.25.1