From nobody Mon May 20 13:25:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645078062830587.4796290686659; Wed, 16 Feb 2022 22:07:42 -0800 (PST) Received: from localhost ([::1]:36808 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKZx7-000132-Fl for importer@patchew.org; Thu, 17 Feb 2022 01:07:41 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52848) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKZuD-0006af-Oc for qemu-devel@nongnu.org; Thu, 17 Feb 2022 01:04:42 -0500 Received: from mga18.intel.com ([134.134.136.126]:2006) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKZuA-0005nq-Ul for qemu-devel@nongnu.org; Thu, 17 Feb 2022 01:04:41 -0500 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2022 22:04:35 -0800 Received: from 984fee00bf64.jf.intel.com ([10.165.54.77]) by fmsmga002.fm.intel.com with ESMTP; 16 Feb 2022 22:04:34 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645077878; x=1676613878; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+BXCxmOSs5NcgfU8u9eDLvKR4KO8CyUBdVj9wcxcXHo=; b=knHdYitC57mCfd5l8/5i8l7LMqMplhSLtRy6e+e/yelzW6WIok0M9N23 rqgKzsuyMAptXnrY66UUDLNMQN6V6xeNeneCP8QTti4a2yw9Yjv86Fx1L LIPA+gvFD+ZbU+5iaJTXYCJcSV7Hw/HG70v93y92Fd5ZlaPWQXUuxWwe4 +H4kW9y3miKHfhefFCt9HdZy+7IEQP6X5DEQBzfZXslAu6c+g0GMil9qm 51antvJbOj29dDG1nOtVrvtJkCcyQEgu3Ukd2Pif8U+M23tH4sXWgxZgz tXaHimV8B6UTYqfK5HKxg4Enclrwwaqgp4l1BWad679z0yIw8Dm5cwIs8 Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10260"; a="234332893" X-IronPort-AV: E=Sophos;i="5.88,375,1635231600"; d="scan'208";a="234332893" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,375,1635231600"; d="scan'208";a="634318690" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [PATCH v2 1/8] x86: Fix the 64-byte boundary enumeration for extended state Date: Wed, 16 Feb 2022 22:04:27 -0800 Message-Id: <20220217060434.52460-2-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220217060434.52460-1-yang.zhong@intel.com> References: <20220217060434.52460-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=yang.zhong@intel.com; helo=mga18.intel.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.083, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645078065274100001 Content-Type: text/plain; charset="utf-8" From: Jing Liu The extended state subleaves (EAX=3D0Dh, ECX=3Dn, n>1).ECX[1] indicate whether the extended state component locates on the next 64-byte boundary following the preceding state component when the compacted format of an XSAVE area is used. Right now, they are all zero because no supported component needed the bit to be set, but the upcoming AMX feature will use it. Fix the subleaves value according to KVM's supported cpuid. Signed-off-by: Jing Liu Signed-off-by: Yang Zhong Reviewed-by: David Edmondson --- target/i386/cpu.h | 6 ++++++ target/i386/cpu.c | 1 + target/i386/kvm/kvm-cpu.c | 1 + 3 files changed, 8 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9911d7c871..de1dc124ab 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -548,6 +548,11 @@ typedef enum X86Seg { #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) =20 +#define ESA_FEATURE_ALIGN64_BIT 1 + +#define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT) + + /* CPUID feature words */ typedef enum FeatureWord { FEAT_1_EDX, /* CPUID[1].EDX */ @@ -1354,6 +1359,7 @@ QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) !=3D 0x8); typedef struct ExtSaveArea { uint32_t feature, bits; uint32_t offset, size; + uint32_t ecx; } ExtSaveArea; =20 #define XSAVE_STATE_AREA_COUNT (XSTATE_PKRU_BIT + 1) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index aa9e636800..37f06b0b1a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5487,6 +5487,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, const ExtSaveArea *esa =3D &x86_ext_save_areas[count]; *eax =3D esa->size; *ebx =3D esa->offset; + *ecx =3D esa->ecx & ESA_FEATURE_ALIGN64_MASK; } } break; diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index d95028018e..ce27d3b1df 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -104,6 +104,7 @@ static void kvm_cpu_xsave_init(void) if (sz !=3D 0) { assert(esa->size =3D=3D sz); esa->offset =3D kvm_arch_get_supported_cpuid(s, 0xd, i, R_= EBX); + esa->ecx =3D kvm_arch_get_supported_cpuid(s, 0xd, i, R_ECX= ); } } } From nobody Mon May 20 13:25:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164507821799265.36449692525582; Wed, 16 Feb 2022 22:10:17 -0800 (PST) Received: from localhost ([::1]:44412 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKZzc-000661-2V for importer@patchew.org; Thu, 17 Feb 2022 01:10:16 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKZuG-0006cW-Kf for qemu-devel@nongnu.org; Thu, 17 Feb 2022 01:04:44 -0500 Received: from mga18.intel.com ([134.134.136.126]:2006) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKZuE-0005nq-NV for qemu-devel@nongnu.org; Thu, 17 Feb 2022 01:04:44 -0500 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2022 22:04:35 -0800 Received: from 984fee00bf64.jf.intel.com ([10.165.54.77]) by fmsmga002.fm.intel.com with ESMTP; 16 Feb 2022 22:04:34 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645077882; x=1676613882; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+XEbN/3qC+pPbXglDATQzARQh0TWxGNnLC/6TB3OpCw=; b=SSoQWpt1R64BXWYxDK/vfB0V10ZQJNIRj8FJTDCDy7GZe/rXppWmORIr VqWZ8B5y17tg4TwRuDiynDA0YoZDPEU2bzgVqQCtKZFnwvJs3X/6zEQrH PWPM7rPC2RUA9mn+Lw3tXMDV3MGfzTsipssENAn38ieAfTmcLqDZEV+zu mQpM6JtIRQLg+sw4F+YU5ldJvmIYFHR/VVSKH02fblSNxbnLSfjL+plBD cbeHEeuMP2DJNzP8h0feshXLCNwaNM/PRM52DcqiMYVCXvmmbdWlTIDRp bY26IP6oFl8oMppu1Q2M0zjjqFgqDybRvZFvUf3NH6hjmQM9sv+85flU1 g==; X-IronPort-AV: E=McAfee;i="6200,9189,10260"; a="234332895" X-IronPort-AV: E=Sophos;i="5.88,375,1635231600"; d="scan'208";a="234332895" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,375,1635231600"; d="scan'208";a="634318695" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [PATCH v2 2/8] x86: Add AMX XTILECFG and XTILEDATA components Date: Wed, 16 Feb 2022 22:04:28 -0800 Message-Id: <20220217060434.52460-3-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220217060434.52460-1-yang.zhong@intel.com> References: <20220217060434.52460-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=yang.zhong@intel.com; helo=mga18.intel.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.083, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645078220564100003 Content-Type: text/plain; charset="utf-8" From: Jing Liu The AMX TILECFG register and the TMMx tile data registers are saved/restored via XSAVE, respectively in state component 17 (64 bytes) and state component 18 (8192 bytes). Add AMX feature bits to x86_ext_save_areas array to set up AMX components. Add structs that define the layout of AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the structs sizes. Signed-off-by: Jing Liu Signed-off-by: Yang Zhong Reviewed-by: David Edmondson --- target/i386/cpu.h | 18 +++++++++++++++++- target/i386/cpu.c | 8 ++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index de1dc124ab..06d2d6bccf 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -537,6 +537,8 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_BIT 6 #define XSTATE_Hi16_ZMM_BIT 7 #define XSTATE_PKRU_BIT 9 +#define XSTATE_XTILE_CFG_BIT 17 +#define XSTATE_XTILE_DATA_BIT 18 =20 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) @@ -845,6 +847,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) /* AVX512_FP16 instruction */ #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) +/* AMX tile (two-dimensional register) */ +#define CPUID_7_0_EDX_AMX_TILE (1U << 24) /* Speculation Control */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Single Thread Indirect Branch Predictors */ @@ -1348,6 +1352,16 @@ typedef struct XSavePKRU { uint32_t padding; } XSavePKRU; =20 +/* Ext. save area 17: AMX XTILECFG state */ +typedef struct XSaveXTILECFG { + uint8_t xtilecfg[64]; +} XSaveXTILECFG; + +/* Ext. save area 18: AMX XTILEDATA state */ +typedef struct XSaveXTILEDATA { + uint8_t xtiledata[8][1024]; +} XSaveXTILEDATA; + QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) !=3D 0x100); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) !=3D 0x40); @@ -1355,6 +1369,8 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) !=3D 0x200); QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) !=3D 0x400); QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) !=3D 0x8); +QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) !=3D 0x40); +QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) !=3D 0x2000); =20 typedef struct ExtSaveArea { uint32_t feature, bits; @@ -1362,7 +1378,7 @@ typedef struct ExtSaveArea { uint32_t ecx; } ExtSaveArea; =20 -#define XSAVE_STATE_AREA_COUNT (XSTATE_PKRU_BIT + 1) +#define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1) =20 extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT]; =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 37f06b0b1a..ea7e8f9081 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1401,6 +1401,14 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUN= T] =3D { [XSTATE_PKRU_BIT] =3D { .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_PKU, .size =3D sizeof(XSavePKRU) }, + [XSTATE_XTILE_CFG_BIT] =3D { + .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_AMX_TILE, + .size =3D sizeof(XSaveXTILECFG), + }, + [XSTATE_XTILE_DATA_BIT] =3D { + .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_AMX_TILE, + .size =3D sizeof(XSaveXTILEDATA) + }, }; =20 static uint32_t xsave_area_size(uint64_t mask) From nobody Mon May 20 13:25:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164507806516923.696639320554823; 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charset="utf-8" Kernel allocates 4K xstate buffer by default. For XSAVE features which require large state component (e.g. AMX), Linux kernel dynamically expands the xstate buffer only after the process has acquired the necessary permissions. Those are called dynamically- enabled XSAVE features (or dynamic xfeatures). There are separate permissions for native tasks and guests. Qemu should request the guest permissions for dynamic xfeatures which will be exposed to the guest. This only needs to be done once before the first vcpu is created. KVM implemented one new ARCH_GET_XCOMP_SUPP system attribute API to get host side supported_xcr0 and Qemu can decide if it can request dynamically enabled XSAVE features permission. https://lore.kernel.org/all/20220126152210.3044876-1-pbonzini@redhat.com/ Suggested-by: Paolo Bonzini Signed-off-by: Yang Zhong Signed-off-by: Jing Liu --- target/i386/cpu.h | 7 +++++++ target/i386/cpu.c | 43 +++++++++++++++++++++++++++++++++++++++ target/i386/kvm/kvm-cpu.c | 12 +++++------ target/i386/kvm/kvm.c | 20 ++++++++++++++++++ 4 files changed, 76 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 06d2d6bccf..d4ad0f56bd 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -549,6 +549,13 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) +#define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT) +#define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT) +#define XFEATURE_XTILE_MASK (XSTATE_XTILE_CFG_MASK \ + | XSTATE_XTILE_DATA_MASK) + +#define ARCH_GET_XCOMP_GUEST_PERM 0x1024 +#define ARCH_REQ_XCOMP_GUEST_PERM 0x1025 =20 #define ESA_FEATURE_ALIGN64_BIT 1 =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ea7e8f9081..377d993438 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -43,6 +43,8 @@ #include "disas/capstone.h" #include "cpu-internal.h" =20 +#include + /* Helpers for building CPUID[2] descriptors: */ =20 struct CPUID2CacheDescriptorInfo { @@ -6000,12 +6002,47 @@ static void x86_cpu_adjust_feat_level(X86CPU *cpu, = FeatureWord w) } } =20 +static void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask) +{ + KVMState *s =3D kvm_state; + uint64_t bitmask; + long rc; + + if ((mask & XSTATE_XTILE_DATA_MASK) =3D=3D XSTATE_XTILE_DATA_MASK) { + bitmask =3D kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX); + if (!(bitmask & XSTATE_XTILE_DATA_MASK)) { + warn_report("no amx support from supported_xcr0, " + "bitmask:0x%lx", bitmask); + return; + } + + rc =3D syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, + XSTATE_XTILE_DATA_BIT); + if (rc) { + /* + * The older kernel version(<5.15) can't support + * ARCH_REQ_XCOMP_GUEST_PERM and directly return. + */ + return; + } + + rc =3D syscall(SYS_arch_prctl, ARCH_GET_XCOMP_GUEST_PERM, &bitmask= ); + if (rc) { + warn_report("prctl(ARCH_GET_XCOMP_GUEST_PERM) error: %ld", rc); + } else if (!(bitmask & XFEATURE_XTILE_MASK)) { + warn_report("prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure " + "and bitmask=3D0x%lx", bitmask); + } + } +} + /* Calculate XSAVE components based on the configured CPU feature flags */ static void x86_cpu_enable_xsave_components(X86CPU *cpu) { CPUX86State *env =3D &cpu->env; int i; uint64_t mask; + static bool request_perm; =20 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { env->features[FEAT_XSAVE_COMP_LO] =3D 0; @@ -6021,6 +6058,12 @@ static void x86_cpu_enable_xsave_components(X86CPU *= cpu) } } =20 + /* Only request permission for first vcpu */ + if (kvm_enabled() && !request_perm) { + kvm_request_xsave_components(cpu, mask); + request_perm =3D true; + } + env->features[FEAT_XSAVE_COMP_LO] =3D mask; env->features[FEAT_XSAVE_COMP_HI] =3D mask >> 32; } diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index ce27d3b1df..a35a1bf9fe 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -84,7 +84,7 @@ static void kvm_cpu_max_instance_init(X86CPU *cpu) static void kvm_cpu_xsave_init(void) { static bool first =3D true; - KVMState *s =3D kvm_state; + uint32_t eax, ebx, ecx, edx; int i; =20 if (!first) { @@ -100,11 +100,11 @@ static void kvm_cpu_xsave_init(void) ExtSaveArea *esa =3D &x86_ext_save_areas[i]; =20 if (esa->size) { - int sz =3D kvm_arch_get_supported_cpuid(s, 0xd, i, R_EAX); - if (sz !=3D 0) { - assert(esa->size =3D=3D sz); - esa->offset =3D kvm_arch_get_supported_cpuid(s, 0xd, i, R_= EBX); - esa->ecx =3D kvm_arch_get_supported_cpuid(s, 0xd, i, R_ECX= ); + host_cpuid(0xd, i, &eax, &ebx, &ecx, &edx); + if (eax !=3D 0) { + assert(esa->size =3D=3D eax); + esa->offset =3D ebx; + esa->ecx =3D ecx; } } } diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 2c8feb4a6f..3bdcd724c4 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -348,6 +348,7 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint= 32_t function, struct kvm_cpuid2 *cpuid; uint32_t ret =3D 0; uint32_t cpuid_1_edx; + uint64_t bitmask; =20 cpuid =3D get_supported_cpuid(s); =20 @@ -405,6 +406,25 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uin= t32_t function, if (!has_msr_arch_capabs) { ret &=3D ~CPUID_7_0_EDX_ARCH_CAPABILITIES; } + } else if (function =3D=3D 0xd && index =3D=3D 0 && + (reg =3D=3D R_EAX || reg =3D=3D R_EDX)) { + struct kvm_device_attr attr =3D { + .group =3D 0, + .attr =3D KVM_X86_XCOMP_GUEST_SUPP, + .addr =3D (unsigned long) &bitmask + }; + + bool sys_attr =3D kvm_check_extension(s, KVM_CAP_SYS_ATTRIBUTES); + if (!sys_attr) { + warn_report("cannot get sys attribute capabilities %d", sys_at= tr); + } + + int rc =3D kvm_ioctl(s, KVM_GET_DEVICE_ATTR, &attr); + if (rc =3D=3D -1 && (errno =3D=3D ENXIO || errno =3D=3D EINVAL)) { + warn_report("KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) " + "error: %d", rc); + } + ret =3D (reg =3D=3D R_EAX) ? bitmask : bitmask >> 32; } else if (function =3D=3D 0x80000001 && reg =3D=3D R_ECX) { /* * It's safe to enable TOPOEXT even if it's not returned by From nobody Mon May 20 13:25:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645078102693240.144951628233; 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charset="utf-8" From: Jing Liu Intel introduces XFD faulting mechanism for extended XSAVE features to dynamically enable the features in runtime. If CPUID (EAX=3D0Dh, ECX=3Dn, n>1).ECX[2] is set as 1, it indicates support for XFD faulting of this state component. Signed-off-by: Jing Liu Signed-off-by: Yang Zhong Reviewed-by: David Edmondson --- target/i386/cpu.h | 2 ++ target/i386/cpu.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d4ad0f56bd..f7fc2e97a6 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -558,8 +558,10 @@ typedef enum X86Seg { #define ARCH_REQ_XCOMP_GUEST_PERM 0x1025 =20 #define ESA_FEATURE_ALIGN64_BIT 1 +#define ESA_FEATURE_XFD_BIT 2 =20 #define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT) +#define ESA_FEATURE_XFD_MASK (1U << ESA_FEATURE_XFD_BIT) =20 =20 /* CPUID feature words */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 377d993438..5a7ee8c7e1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5497,7 +5497,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, const ExtSaveArea *esa =3D &x86_ext_save_areas[count]; *eax =3D esa->size; *ebx =3D esa->offset; - *ecx =3D esa->ecx & ESA_FEATURE_ALIGN64_MASK; + *ecx =3D (esa->ecx & ESA_FEATURE_ALIGN64_MASK) | + (esa->ecx & ESA_FEATURE_XFD_MASK); } } break; From nobody Mon May 20 13:25:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645078218680254.63677864494605; Wed, 16 Feb 2022 22:10:18 -0800 (PST) Received: from localhost ([::1]:44540 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKZzd-0006BT-J7 for importer@patchew.org; Thu, 17 Feb 2022 01:10:17 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53004) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKZuJ-0006fM-6R for qemu-devel@nongnu.org; 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charset="utf-8" From: Jing Liu Add AMX primary feature bits XFD and AMX_TILE to enumerate the CPU's AMX capability. Meanwhile, add AMX TILE and TMUL CPUID leaf and subleaves which exist when AMX TILE is present to provide the maximum capability of TILE and TMUL. Signed-off-by: Jing Liu Signed-off-by: Yang Zhong Reviewed-by: David Edmondson --- target/i386/cpu.c | 55 ++++++++++++++++++++++++++++++++++++++++--- target/i386/kvm/kvm.c | 4 +++- 2 files changed, 55 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5a7ee8c7e1..2465bed5df 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -576,6 +576,18 @@ static CPUCacheInfo legacy_l3_cache =3D { #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32= K,64K */ =20 +/* CPUID Leaf 0x1D constants: */ +#define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 +#define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 +#define INTEL_AMX_BYTES_PER_TILE 0x400 +#define INTEL_AMX_BYTES_PER_ROW 0x40 +#define INTEL_AMX_TILE_MAX_NAMES 0x8 +#define INTEL_AMX_TILE_MAX_ROWS 0x10 + +/* CPUID Leaf 0x1E constants: */ +#define INTEL_AMX_TMUL_MAX_K 0x10 +#define INTEL_AMX_TMUL_MAX_N 0x40 + void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, uint32_t vendor2, uint32_t vendor3) { @@ -845,8 +857,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "avx512-vp2intersect", NULL, "md-clear", NULL, NULL, NULL, "serialize", NULL, "tsx-ldtrk", NULL, NULL /* pconfig */, NULL, - NULL, NULL, NULL, "avx512-fp16", - NULL, NULL, "spec-ctrl", "stibp", + NULL, NULL, "amx-bf16", "avx512-fp16", + "amx-tile", "amx-int8", "spec-ctrl", "stibp", NULL, "arch-capabilities", "core-capability", "ssbd", }, .cpuid =3D { @@ -911,7 +923,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "xsaveopt", "xsavec", "xgetbv1", "xsaves", - NULL, NULL, NULL, NULL, + "xfd", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -5587,6 +5599,43 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } break; } + case 0x1D: { + /* AMX TILE */ + *eax =3D 0; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; + if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { + break; + } + + if (count =3D=3D 0) { + /* Highest numbered palette subleaf */ + *eax =3D INTEL_AMX_TILE_MAX_SUBLEAF; + } else if (count =3D=3D 1) { + *eax =3D INTEL_AMX_TOTAL_TILE_BYTES | + (INTEL_AMX_BYTES_PER_TILE << 16); + *ebx =3D INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES <= < 16); + *ecx =3D INTEL_AMX_TILE_MAX_ROWS; + } + break; + } + case 0x1E: { + /* AMX TMUL */ + *eax =3D 0; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; + if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { + break; + } + + if (count =3D=3D 0) { + /* Highest numbered palette subleaf */ + *ebx =3D INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); + } + break; + } case 0x40000000: /* * CPUID code in kvm_arch_init_vcpu() ignores stuff diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 3bdcd724c4..8562d3d138 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1779,7 +1779,9 @@ int kvm_arch_init_vcpu(CPUState *cs) c =3D &cpuid_data.entries[cpuid_i++]; } break; - case 0x14: { + case 0x14: + case 0x1d: + case 0x1e: { uint32_t times; =20 c->function =3D i; From nobody Mon May 20 13:25:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645078396811187.26342414254907; Wed, 16 Feb 2022 22:13:16 -0800 (PST) Received: from localhost ([::1]:48872 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKa2V-0000mb-SO for importer@patchew.org; Thu, 17 Feb 2022 01:13:15 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53026) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKZuJ-0006iJ-T3 for qemu-devel@nongnu.org; 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charset="utf-8" From: Jing Liu When dynamic xfeatures (e.g. AMX) are used by the guest, the xsave area would be larger than 4KB. KVM_GET_XSAVE2 and KVM_SET_XSAVE under KVM_CAP_XSAVE2 works with a xsave buffer larger than 4KB. Always use the new ioctls under KVM_CAP_XSAVE2 when KVM supports it. Signed-off-by: Jing Liu Signed-off-by: Zeng Guang Signed-off-by: Wei Wang Signed-off-by: Yang Zhong --- target/i386/cpu.h | 4 ++++ target/i386/kvm/kvm.c | 42 ++++++++++++++++++++++++-------------- target/i386/xsave_helper.c | 33 ++++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+), 15 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index f7fc2e97a6..de9da38e42 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1528,6 +1528,10 @@ typedef struct CPUX86State { uint64_t opmask_regs[NB_OPMASK_REGS]; YMMReg zmmh_regs[CPU_NB_REGS]; ZMMReg hi16_zmm_regs[CPU_NB_REGS]; +#ifdef TARGET_X86_64 + uint8_t xtilecfg[64]; + uint8_t xtiledata[8192]; +#endif =20 /* sysenter registers */ uint32_t sysenter_cs; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 8562d3d138..ff064e3d8f 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -122,6 +122,7 @@ static uint32_t num_architectural_pmu_gp_counters; static uint32_t num_architectural_pmu_fixed_counters; =20 static int has_xsave; +static int has_xsave2; static int has_xcrs; static int has_pit_state2; static int has_sregs2; @@ -1585,6 +1586,26 @@ static Error *invtsc_mig_blocker; =20 #define KVM_MAX_CPUID_ENTRIES 100 =20 +static void kvm_init_xsave(CPUX86State *env) +{ + if (has_xsave2) { + env->xsave_buf_len =3D QEMU_ALIGN_UP(has_xsave2, 4096); + } else if (has_xsave) { + env->xsave_buf_len =3D sizeof(struct kvm_xsave); + } else { + return; + } + + env->xsave_buf =3D qemu_memalign(4096, env->xsave_buf_len); + memset(env->xsave_buf, 0, env->xsave_buf_len); + /* + * The allocated storage must be large enough for all of the + * possible XSAVE state components. + */ + assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <=3D + env->xsave_buf_len); +} + int kvm_arch_init_vcpu(CPUState *cs) { struct { @@ -1614,6 +1635,8 @@ int kvm_arch_init_vcpu(CPUState *cs) =20 cpuid_i =3D 0; =20 + has_xsave2 =3D kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2); + r =3D kvm_arch_set_tsc_khz(cs); if (r < 0) { return r; @@ -2003,19 +2026,7 @@ int kvm_arch_init_vcpu(CPUState *cs) if (r) { goto fail; } - - if (has_xsave) { - env->xsave_buf_len =3D sizeof(struct kvm_xsave); - env->xsave_buf =3D qemu_memalign(4096, env->xsave_buf_len); - memset(env->xsave_buf, 0, env->xsave_buf_len); - - /* - * The allocated storage must be large enough for all of the - * possible XSAVE state components. - */ - assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) - <=3D env->xsave_buf_len); - } + kvm_init_xsave(env); =20 max_nested_state_len =3D kvm_max_nested_state_length(); if (max_nested_state_len > 0) { @@ -3319,13 +3330,14 @@ static int kvm_get_xsave(X86CPU *cpu) { CPUX86State *env =3D &cpu->env; void *xsave =3D env->xsave_buf; - int ret; + int type, ret; =20 if (!has_xsave) { return kvm_get_fpu(cpu); } =20 - ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave); + type =3D has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE; + ret =3D kvm_vcpu_ioctl(CPU(cpu), type, xsave); if (ret < 0) { return ret; } diff --git a/target/i386/xsave_helper.c b/target/i386/xsave_helper.c index ac61a96344..b6a004505f 100644 --- a/target/i386/xsave_helper.c +++ b/target/i386/xsave_helper.c @@ -5,6 +5,7 @@ #include "qemu/osdep.h" =20 #include "cpu.h" +#include =20 void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen) { @@ -126,6 +127,22 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, u= int32_t buflen) =20 memcpy(pkru, &env->pkru, sizeof(env->pkru)); } + + e =3D &x86_ext_save_areas[XSTATE_XTILE_CFG_BIT]; + if (e->size && e->offset) { + XSaveXTILECFG *tilecfg =3D buf + e->offset; + + memcpy(tilecfg, &env->xtilecfg, sizeof(env->xtilecfg)); + } + + if (buflen > sizeof(struct kvm_xsave)) { + e =3D &x86_ext_save_areas[XSTATE_XTILE_DATA_BIT]; + if (e->size && e->offset && buflen >=3D e->size + e->offset) { + XSaveXTILEDATA *tiledata =3D buf + e->offset; + + memcpy(tiledata, &env->xtiledata, sizeof(env->xtiledata)); + } + } #endif } =20 @@ -247,5 +264,21 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void = *buf, uint32_t buflen) pkru =3D buf + e->offset; memcpy(&env->pkru, pkru, sizeof(env->pkru)); } + + e =3D &x86_ext_save_areas[XSTATE_XTILE_CFG_BIT]; + if (e->size && e->offset) { + const XSaveXTILECFG *tilecfg =3D buf + e->offset; + + memcpy(&env->xtilecfg, tilecfg, sizeof(env->xtilecfg)); + } + + if (buflen > sizeof(struct kvm_xsave)) { + e =3D &x86_ext_save_areas[XSTATE_XTILE_DATA_BIT]; + if (e->size && e->offset && buflen >=3D e->size + e->offset) { + const XSaveXTILEDATA *tiledata =3D buf + e->offset; + + memcpy(&env->xtiledata, tiledata, sizeof(env->xtiledata)); + } + } #endif } From nobody Mon May 20 13:25:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645078384601426.5725713391647; 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charset="utf-8" From: Zeng Guang XFD(eXtended Feature Disable) allows to enable a feature on xsave state while preventing specific user threads from using the feature. Support save and restore XFD MSRs if CPUID.D.1.EAX[4] enumerate to be valid. Likewise migrate the MSRs and related xsave state necessarily. Signed-off-by: Zeng Guang Signed-off-by: Wei Wang Signed-off-by: Yang Zhong Reviewed-by: David Edmondson --- target/i386/cpu.h | 9 +++++++++ target/i386/kvm/kvm.c | 18 ++++++++++++++++++ target/i386/machine.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 69 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index de9da38e42..509c16323a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -505,6 +505,9 @@ typedef enum X86Seg { =20 #define MSR_VM_HSAVE_PA 0xc0010117 =20 +#define MSR_IA32_XFD 0x000001c4 +#define MSR_IA32_XFD_ERR 0x000001c5 + #define MSR_IA32_BNDCFGS 0x00000d90 #define MSR_IA32_XSS 0x00000da0 #define MSR_IA32_UMWAIT_CONTROL 0xe1 @@ -873,6 +876,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) /* AVX512 BFloat16 Instruction */ #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) +/* XFD Extend Feature Disabled */ +#define CPUID_D_1_EAX_XFD (1U << 4) =20 /* Packets which contain IP payload have LIP values */ #define CPUID_14_0_ECX_LIP (1U << 31) @@ -1617,6 +1622,10 @@ typedef struct CPUX86State { uint64_t msr_rtit_cr3_match; uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; =20 + /* Per-VCPU XFD MSRs */ + uint64_t msr_xfd; + uint64_t msr_xfd_err; + /* exception/interrupt handling */ int error_code; int exception_is_int; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index ff064e3d8f..3dd24b6b0e 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -3275,6 +3275,13 @@ static int kvm_put_msrs(X86CPU *cpu, int level) env->msr_ia32_sgxlepubkeyhash[3]); } =20 + if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) { + kvm_msr_entry_add(cpu, MSR_IA32_XFD, + env->msr_xfd); + kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, + env->msr_xfd_err); + } + /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see * kvm_put_msr_feature_control. */ } @@ -3667,6 +3674,11 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0); } =20 + if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) { + kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0); + kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0); + } + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); if (ret < 0) { return ret; @@ -3963,6 +3975,12 @@ static int kvm_get_msrs(X86CPU *cpu) env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH= 0] =3D msrs[i].data; break; + case MSR_IA32_XFD: + env->msr_xfd =3D msrs[i].data; + break; + case MSR_IA32_XFD_ERR: + env->msr_xfd_err =3D msrs[i].data; + break; } } =20 diff --git a/target/i386/machine.c b/target/i386/machine.c index 6202f47793..1f9d0c46f1 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1483,6 +1483,46 @@ static const VMStateDescription vmstate_pdptrs =3D { } }; =20 +static bool xfd_msrs_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return !!(env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD); +} + +static const VMStateDescription vmstate_msr_xfd =3D { + .name =3D "cpu/msr_xfd", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D xfd_msrs_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.msr_xfd, X86CPU), + VMSTATE_UINT64(env.msr_xfd_err, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool amx_xtile_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return !!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE); +} + +static const VMStateDescription vmstate_amx_xtile =3D { + .name =3D "cpu/intel_amx_xtile", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D amx_xtile_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8_ARRAY(env.xtilecfg, X86CPU, 64), + VMSTATE_UINT8_ARRAY(env.xtiledata, X86CPU, 8192), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_x86_cpu =3D { .name =3D "cpu", .version_id =3D 12, @@ -1622,6 +1662,8 @@ const VMStateDescription vmstate_x86_cpu =3D { &vmstate_msr_tsx_ctrl, &vmstate_msr_intel_sgx, &vmstate_pdptrs, + &vmstate_msr_xfd, + &vmstate_amx_xtile, NULL } }; From nobody Mon May 20 13:25:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" This patch will be dropped once Qemu sync linux 5.17 header. Making all linux-headers changes here are only for maintainers to easily remove those changes once those patches are queued. Signed-off-by: Yang Zhong --- linux-headers/asm-x86/kvm.h | 17 +++++++++++++++++ linux-headers/linux/kvm.h | 4 ++++ 2 files changed, 21 insertions(+) diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h index 5a776a08f7..17735430db 100644 --- a/linux-headers/asm-x86/kvm.h +++ b/linux-headers/asm-x86/kvm.h @@ -375,7 +375,21 @@ struct kvm_debugregs { =20 /* for KVM_CAP_XSAVE */ struct kvm_xsave { + /* + * KVM_GET_XSAVE2 and KVM_SET_XSAVE write and read as many bytes + * as are returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2) + * respectively, when invoked on the vm file descriptor. + * + * The size value returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2) + * will always be at least 4096. Currently, it is only greater + * than 4096 if a dynamic feature has been enabled with + * ``arch_prctl()``, but this may change in the future. + * + * The offsets of the state save areas in struct kvm_xsave follow + * the contents of CPUID leaf 0xD on the host. + */ __u32 region[1024]; + __u32 extra[0]; }; =20 #define KVM_MAX_XCRS 16 @@ -438,6 +452,9 @@ struct kvm_sync_regs { =20 #define KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE 0x00000001 =20 +/* attributes for system fd (group 0) */ +#define KVM_X86_XCOMP_GUEST_SUPP 0 + struct kvm_vmx_nested_state_data { __u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; __u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 02c5e7b7bb..54ce7e6d90 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1130,6 +1130,8 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_BINARY_STATS_FD 203 #define KVM_CAP_EXIT_ON_EMULATION_FAILURE 204 #define KVM_CAP_ARM_MTE 205 +#define KVM_CAP_XSAVE2 208 +#define KVM_CAP_SYS_ATTRIBUTES 209 =20 #ifdef KVM_CAP_IRQ_ROUTING =20 @@ -1677,6 +1679,8 @@ struct kvm_xen_hvm_attr { #define KVM_GET_SREGS2 _IOR(KVMIO, 0xcc, struct kvm_sregs2) #define KVM_SET_SREGS2 _IOW(KVMIO, 0xcd, struct kvm_sregs2) =20 +#define KVM_GET_XSAVE2 _IOR(KVMIO, 0xcf, struct kvm_xsave) + struct kvm_xen_vcpu_attr { __u16 type; __u16 pad[3];