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a="250756928" X-IronPort-AV: E=Sophos;i="5.88,373,1635231600"; d="scan'208";a="250756928" X-IronPort-AV: E=Sophos;i="5.88,373,1635231600"; d="scan'208";a="633418296" From: Yang Weijiang To: pbonzini@redhat.com, ehabkost@redhat.com, mtosatti@redhat.com, seanjc@google.com, richard.henderson@linaro.org, like.xu.linux@gmail.com, wei.w.wang@intel.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH 8/8] target/i386: Support Arch LBR in CPUID enumeration Date: Tue, 15 Feb 2022 14:52:58 -0500 Message-Id: <20220215195258.29149-9-weijiang.yang@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220215195258.29149-1-weijiang.yang@intel.com> References: <20220215195258.29149-1-weijiang.yang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=weijiang.yang@intel.com; helo=mga14.intel.com X-Spam_score_int: -60 X-Spam_score: -6.1 X-Spam_bar: ------ X-Spam_report: (-6.1 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_12_24=1.049, DKIMWL_WL_HIGH=-0.083, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1645003730280100001 Content-Type: text/plain; charset="utf-8" If CPUID.(EAX=3D07H, ECX=3D0):EDX[19] is set to 1, the processor supports Architectural LBRs. In this case, CPUID leaf 01CH indicates details of the Architectural LBRs capabilities. XSAVE support for Architectural LBRs is enumerated in CPUID.(EAX=3D0DH, ECX=3D0FH). Signed-off-by: Yang Weijiang --- target/i386/cpu.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e505c926b2..1092618683 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -858,7 +858,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "fsrm", NULL, NULL, NULL, "avx512-vp2intersect", NULL, "md-clear", NULL, NULL, NULL, "serialize", NULL, - "tsx-ldtrk", NULL, NULL /* pconfig */, NULL, + "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", NULL, NULL, "amx-bf16", "avx512-fp16", "amx-tile", "amx-int8", "spec-ctrl", "stibp", NULL, "arch-capabilities", "core-capability", "ssbd", @@ -5494,6 +5494,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, assert(!(*eax & ~0x1f)); *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ break; + case 0x1C: + *eax =3D kvm_arch_get_supported_cpuid(cs->kvm_state, 0x1C, 0, R_EA= X); + *ebx =3D kvm_arch_get_supported_cpuid(cs->kvm_state, 0x1C, 0, R_EB= X); + *ecx =3D kvm_arch_get_supported_cpuid(cs->kvm_state, 0x1C, 0, R_EC= X); + *edx =3D 0; + break; case 0x1F: /* V2 Extended Topology Enumeration Leaf */ if (env->nr_dies < 2) { @@ -5556,6 +5562,19 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *ebx =3D xsave_area_size(xstate, true); *ecx =3D env->features[FEAT_XSAVE_XSS_LO]; *edx =3D env->features[FEAT_XSAVE_XSS_HI]; + if (kvm_enabled() && cpu->enable_pmu && + (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && + (*eax & CPUID_XSAVE_XSAVES)) { + *ecx |=3D XSTATE_ARCH_LBR_MASK; + } else { + *ecx &=3D ~XSTATE_ARCH_LBR_MASK; + } + } else if (count =3D=3D 0xf && kvm_enabled() && cpu->enable_pmu && + (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR))= { + *eax =3D kvm_arch_get_supported_cpuid(cs->kvm_state, 0xD, 0xf,= R_EAX); + *ebx =3D kvm_arch_get_supported_cpuid(cs->kvm_state, 0xD, 0xf,= R_EBX); + *ecx =3D kvm_arch_get_supported_cpuid(cs->kvm_state, 0xD, 0xf,= R_ECX); + *edx =3D kvm_arch_get_supported_cpuid(cs->kvm_state, 0xD, 0xf,= R_EDX); } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { const ExtSaveArea *esa =3D &x86_ext_save_areas[count]; =20 --=20 2.27.0