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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644624228; x=1647216229; bh=xBwofrwi48pVPtDFWu xDh/a2BN1h2L8su5YfJ1V9v60=; b=sNDOx9RlI2+JvFkO8aHycUW9qKF9QVx4PM ZfqaGpJ7TD80ZqHtB6gQiTFhv6BC5ildhYGqghZHSQebMsMK/qV4noH7kJzktsYu 60rkaDmg/4f8KqLpHxRz5Du4biM1qAlgUkRnZz5J4Gn2XINO1T2USYTKfqNcRrN/ JeW5JdXBJmfi9qD7z9pwioTemLvOuYNEyIypGPkapd2EM3X/MxePJU8IG3XJtGI+ b5uaDjmikT1XTqplPyqj1qmEDmmVihNDhZkKcelyI7zrq6bx0Vz2ZbmBlGv9CvMT o7KR7DZ9G9Iy6MyyzV/Unvbwpud1x+cF8K2hCeju3y10jZS7/1EA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Guo Ren , Liu Zhiwei , Alistair Francis , Bin Meng Subject: [PULL 35/40] target/riscv: Ignore reserved bits in PTE for RV64 Date: Sat, 12 Feb 2022 10:00:26 +1000 Message-Id: <20220212000031.3946524-36-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220212000031.3946524-1-alistair.francis@opensource.wdc.com> References: <20220212000031.3946524-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=03511bb56=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644628010899100001 Content-Type: text/plain; charset="utf-8" From: Guo Ren Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit Virtual-Memory System 2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.= pdf Signed-off-by: Guo Ren Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis Cc: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20220204022658.18097-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 15 +++++++++++++++ target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_helper.c | 13 ++++++++++++- 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7ecb1387dd..cefccb4016 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -359,6 +359,8 @@ struct RISCVCPUConfig { bool ext_counters; bool ext_ifencei; bool ext_icsr; + bool ext_svnapot; + bool ext_svpbmt; bool ext_zfh; bool ext_zfhmin; bool ext_zve32f; @@ -558,6 +560,19 @@ static inline int riscv_cpu_xlen(CPURISCVState *env) return 16 << env->xl; } =20 +#ifdef TARGET_RISCV32 +#define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) +#else +static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) +{ +#ifdef CONFIG_USER_ONLY + return env->misa_mxl; +#else + return get_field(env->mstatus, MSTATUS64_SXL); +#endif +} +#endif + /* * Encode LMUL to lmul as follows: * LMUL vlmul lmul diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 068c4d8034..b3489cbc10 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -565,6 +565,9 @@ typedef enum { /* Page table PPN shift amount */ #define PTE_PPN_SHIFT 10 =20 +/* Page table PPN mask */ +#define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL + /* Leaf page shift amount */ #define PGSHIFT 12 =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 430060dcd8..7df4569526 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -751,6 +751,8 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; int mode =3D mmu_idx & TB_FLAGS_PRIV_MMU_MASK; bool use_background =3D false; + hwaddr ppn; + RISCVCPU *cpu =3D env_archcpu(env); =20 /* * Check if we should use the background registers for the two @@ -919,7 +921,16 @@ restart: return TRANSLATE_FAIL; } =20 - hwaddr ppn =3D pte >> PTE_PPN_SHIFT; + if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { + ppn =3D pte >> PTE_PPN_SHIFT; + } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) { + ppn =3D (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; + } else { + ppn =3D pte >> PTE_PPN_SHIFT; + if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) { + return TRANSLATE_FAIL; + } + } =20 if (!(pte & PTE_V)) { /* Invalid PTE */ --=20 2.34.1