From nobody Mon Feb 9 07:55:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1644582602; cv=none; d=zohomail.com; s=zohoarc; b=Wf5+ahJO1Z2Mb30mFzjq0PWtydu0MhCsYCsMu0PlpbVUGQCZmNwUmthVcwS4We3TcTBRmFHrFWfq5Tw1G400yb6LsW5MDPvn/9kB3jnT8PvmQjwCUfgw5IWFh08SAbKgXkUCNNATjJ21j/WPwAzU5mRUkmjlY74/LIeER67YVag= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1644582602; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=N++5XmLlQYfAyVLwjzQK1EvZfcQwqgkfKU1PkeRvvQ4=; b=Dg9LOX3M5nxf6In+dkFPpdCng4K1gD6+orGZmls5AE0SWQB9eTk9BPSDFQzp/Sh565aLlnIncBcgpxU7J0kqci9pHwnIVR5e2Dk+Sm67KUoErXuIfFgoQKzeDccM8A/3TPgw4a3lNie8TRTWuDeqIzckWbruGZhbUUb/8WREVqs= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644582602634793.8480751303889; Fri, 11 Feb 2022 04:30:02 -0800 (PST) Received: from localhost ([::1]:53724 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nIV3q-000139-9v for importer@patchew.org; Fri, 11 Feb 2022 07:30:02 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40224) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nIUrq-0001sD-0z for qemu-devel@nongnu.org; Fri, 11 Feb 2022 07:17:38 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]:2295) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nIUrk-0004YR-Vn for qemu-devel@nongnu.org; Fri, 11 Feb 2022 07:17:37 -0500 Received: from fraeml715-chm.china.huawei.com (unknown [172.18.147.207]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4JwCKp49MGz67Y9y; Fri, 11 Feb 2022 20:17:18 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml715-chm.china.huawei.com (10.206.15.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.21; Fri, 11 Feb 2022 13:17:27 +0100 Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.21; Fri, 11 Feb 2022 12:17:27 +0000 To: , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Marcel Apfelbaum , "Michael S . Tsirkin" , Igor Mammedov CC: , Ben Widawsky , "Peter Maydell" , , "Shameerali Kolothum Thodi" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Saransh Gupta1 , Shreyas Shah , Chris Browy , Samarth Saxena , "Dan Williams" Subject: [PATCH v6 19/43] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Date: Fri, 11 Feb 2022 12:07:23 +0000 Message-ID: <20220211120747.3074-20-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220211120747.3074-1-Jonathan.Cameron@huawei.com> References: <20220211120747.3074-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhreml743-chm.china.huawei.com (10.201.108.193) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Jonathan Cameron From: Jonathan Cameron via X-ZM-MESSAGEID: 1644582622339100001 Content-Type: text/plain; charset="utf-8" From: Ben Widawsky A device's volatile and persistent memory are known Host Defined Memory (HDM) regions. The mechanism by which the device is programmed to claim the addresses associated with those regions is through dedicated logic known as the HDM decoder. In order to allow the OS to properly program the HDMs, the HDM decoders must be modeled. There are two ways the HDM decoders can be implemented, the legacy mechanism is through the PCIe DVSEC programming from CXL 1.1 (8.1.3.8), and MMIO is found in 8.2.5.12 of the spec. For now, 8.1.3.8 is not implemented. Much of CXL device logic is implemented in cxl-utils. The HDM decoder however is implemented directly by the device implementation. Whilst the implementation currently does no validity checks on the encoder set up, future work will add sanity checking specific to the type of cxl component. Signed-off-by: Ben Widawsky Co-developed-by: Jonathan Cameron Signed-off-by: Jonathan Cameron Reviewed-by: Alex Benn=C3=A9e --- hw/mem/cxl_type3.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index c4021d2434..da091157f2 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -61,6 +61,56 @@ static void build_dvsecs(CXLType3Dev *ct3d) REG_LOC_DVSEC_REVID, dvsec); } =20 +static void hdm_decoder_commit(CXLType3Dev *ct3d, int which) +{ + ComponentRegisters *cregs =3D &ct3d->cxl_cstate.crb; + uint32_t *cache_mem =3D cregs->cache_mem_registers; + + assert(which =3D=3D 0); + + /* TODO: Sanity checks that the decoder is possible */ + ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0); + ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0); + + ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); +} + +static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + CXLComponentState *cxl_cstate =3D opaque; + ComponentRegisters *cregs =3D &cxl_cstate->crb; + CXLType3Dev *ct3d =3D container_of(cxl_cstate, CXLType3Dev, cxl_cstate= ); + uint32_t *cache_mem =3D cregs->cache_mem_registers; + bool should_commit =3D false; + int which_hdm =3D -1; + + assert(size =3D=3D 4); + + switch (offset) { + case A_CXL_HDM_DECODER0_CTRL: + should_commit =3D FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT); + which_hdm =3D 0; + break; + default: + break; + } + + stl_le_p((uint8_t *)cache_mem + offset, value); + if (should_commit) { + hdm_decoder_commit(ct3d, which_hdm); + } +} + +static void ct3_finalize(Object *obj) +{ + CXLType3Dev *ct3d =3D CT3(obj); + CXLComponentState *cxl_cstate =3D &ct3d->cxl_cstate; + ComponentRegisters *regs =3D &cxl_cstate->crb; + + g_free((void *)regs->special_ops); +} + static void cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) { MemoryRegion *mr; @@ -103,6 +153,9 @@ static void ct3_realize(PCIDevice *pci_dev, Error **err= p) ct3d->cxl_cstate.pdev =3D pci_dev; build_dvsecs(ct3d); =20 + regs->special_ops =3D g_new0(MemoryRegionOps, 1); + regs->special_ops->write =3D ct3d_reg_write; + cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate, TYPE_CXL_TYPE3_DEV); =20 @@ -155,6 +208,7 @@ static const TypeInfo ct3d_info =3D { .parent =3D TYPE_PCI_DEVICE, .class_init =3D ct3_class_init, .instance_size =3D sizeof(CXLType3Dev), + .instance_finalize =3D ct3_finalize, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CXL_DEVICE }, { INTERFACE_PCIE_DEVICE }, --=20 2.32.0