From nobody Tue Feb 10 11:12:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644578620391687.2898155961772; Fri, 11 Feb 2022 03:23:40 -0800 (PST) Received: from localhost ([::1]:42756 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nIU1b-0007j6-B7 for importer@patchew.org; Fri, 11 Feb 2022 06:23:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:55742) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nITvs-0007Nu-5O for qemu-devel@nongnu.org; Fri, 11 Feb 2022 06:17:46 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:20461) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1nITvg-00015o-75 for qemu-devel@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.46.98.28; envelope-from=tsimpson@qualcomm.com; helo=alexa-out.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, tsimpson@quicinc.com, richard.henderson@linaro.org, f4bug@amsat.org, zongyuan.li@smartx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1644578621150100001 Tests to confirm floating point instructions are properly setting exception bits in USR Signed-off-by: Taylor Simpson Message-Id: <20220210021556.9217-8-tsimpson@quicinc.com> Acked-by: Richard Henderson --- tests/tcg/hexagon/usr.c | 339 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 339 insertions(+) diff --git a/tests/tcg/hexagon/usr.c b/tests/tcg/hexagon/usr.c index e82727237e..bb61731aab 100644 --- a/tests/tcg/hexagon/usr.c +++ b/tests/tcg/hexagon/usr.c @@ -78,6 +78,34 @@ static void __check64(int line, uint64_t val, uint64_t e= xpect) #define USR_FPUNFF (1 << USR_FPUNFF_BIT) #define USR_FPINPF (1 << USR_FPINPF_BIT) =20 +/* Some useful floating point values */ +const uint32_t SF_INF =3D 0x7f800000; +const uint32_t SF_QNaN =3D 0x7fc00000; +const uint32_t SF_SNaN =3D 0x7fb00000; +const uint32_t SF_QNaN_neg =3D 0xffc00000; +const uint32_t SF_SNaN_neg =3D 0xffb00000; +const uint32_t SF_HEX_NaN =3D 0xffffffff; +const uint32_t SF_zero =3D 0x00000000; +const uint32_t SF_one =3D 0x3f800000; +const uint32_t SF_one_recip =3D 0x3f7f0001; /* 0.9960... */ +const uint32_t SF_one_invsqrta =3D 0x3f7f0000; /* 0.99609375 */ +const uint32_t SF_two =3D 0x40000000; +const uint32_t SF_four =3D 0x40800000; +const uint32_t SF_small_neg =3D 0xab98fba8; +const uint32_t SF_large_pos =3D 0x5afa572e; + +const uint64_t DF_QNaN =3D 0x7ff8000000000000ULL; +const uint64_t DF_SNaN =3D 0x7ff7000000000000ULL; +const uint64_t DF_QNaN_neg =3D 0xfff8000000000000ULL; +const uint64_t DF_SNaN_neg =3D 0xfff7000000000000ULL; +const uint64_t DF_HEX_NaN =3D 0xffffffffffffffffULL; +const uint64_t DF_zero =3D 0x0000000000000000ULL; +const uint64_t DF_any =3D 0x3f80000000000000ULL; +const uint64_t DF_one =3D 0x3ff0000000000000ULL; +const uint64_t DF_one_hh =3D 0x3ff001ff80000000ULL; /* 1.000= 48... */ +const uint64_t DF_small_neg =3D 0xbd731f7500000000ULL; +const uint64_t DF_large_pos =3D 0x7f80000000000001ULL; + /* * Templates for functions to execute an instruction * @@ -309,6 +337,29 @@ static RESTYPE NAME(RESTYPE result, SRC1TYPE src1, SRC= 2TYPE src2, uint8_t pred,\ #define FUNC_XR_OP_RRp(NAME, INSN) \ FUNC_Xx_OP_xxp(uint32_t, uint32_t, uint32_t, NAME, INSN) =20 +/* Template for compare instructions with two register operands */ +#define FUNC_CMP_xx(SRC1TYPE, SRC2TYPE, NAME, INSN) \ +static uint32_t NAME(SRC1TYPE src1, SRC2TYPE src2, uint32_t *usr_result) \ +{ \ + uint32_t result; \ + uint32_t usr; \ + asm(CLEAR_USRBITS \ + INSN "\n\t" \ + "%0 =3D p1\n\t" \ + "%1 =3D usr\n\t" \ + : "=3Dr"(result), "=3Dr"(usr) \ + : "r"(src1), "r"(src2) \ + : "p1", "r2", "usr"); \ + *usr_result =3D usr & 0x3f; \ + return result; \ +} + +#define FUNC_CMP_RR(NAME, INSN) \ +FUNC_CMP_xx(uint32_t, uint32_t, NAME, INSN) + +#define FUNC_CMP_PP(NAME, INSN) \ +FUNC_CMP_xx(uint64_t, uint64_t, NAME, INSN) + /* * Function declarations using the templates */ @@ -379,6 +430,69 @@ FUNC_R_OP_RR(asr_r_r_sat, "%0 =3D asr(%2, %3):sa= t") =20 FUNC_XPp_OP_PP(ACS, "%0, p2 =3D vacsh(%3, %4)") =20 +/* Floating point */ +FUNC_R_OP_RR(sfmin, "%0 =3D sfmin(%2, %3)") +FUNC_R_OP_RR(sfmax, "%0 =3D sfmax(%2, %3)") +FUNC_R_OP_RR(sfadd, "%0 =3D sfadd(%2, %3)") +FUNC_R_OP_RR(sfsub, "%0 =3D sfsub(%2, %3)") +FUNC_R_OP_RR(sfmpy, "%0 =3D sfmpy(%2, %3)") +FUNC_XR_OP_RR(sffma, "%0 +=3D sfmpy(%2, %3)") +FUNC_XR_OP_RR(sffms, "%0 -=3D sfmpy(%2, %3)") +FUNC_CMP_RR(sfcmpuo, "p1 =3D sfcmp.uo(%2, %3)") +FUNC_CMP_RR(sfcmpeq, "p1 =3D sfcmp.eq(%2, %3)") +FUNC_CMP_RR(sfcmpgt, "p1 =3D sfcmp.gt(%2, %3)") +FUNC_CMP_RR(sfcmpge, "p1 =3D sfcmp.ge(%2, %3)") + +FUNC_P_OP_PP(dfadd, "%0 =3D dfadd(%2, %3)") +FUNC_P_OP_PP(dfsub, "%0 =3D dfsub(%2, %3)") + +#if CORE_IS_V67 +FUNC_P_OP_PP(dfmin, "%0 =3D dfmin(%2, %3)") +FUNC_P_OP_PP(dfmax, "%0 =3D dfmax(%2, %3)") +FUNC_XP_OP_PP(dfmpyhh, "%0 +=3D dfmpyhh(%2, %3)") +#endif + +FUNC_CMP_PP(dfcmpuo, "p1 =3D dfcmp.uo(%2, %3)") +FUNC_CMP_PP(dfcmpeq, "p1 =3D dfcmp.eq(%2, %3)") +FUNC_CMP_PP(dfcmpgt, "p1 =3D dfcmp.gt(%2, %3)") +FUNC_CMP_PP(dfcmpge, "p1 =3D dfcmp.ge(%2, %3)") + +/* Conversions from sf */ +FUNC_P_OP_R(conv_sf2df, "%0 =3D convert_sf2df(%2)") +FUNC_R_OP_R(conv_sf2uw, "%0 =3D convert_sf2uw(%2)") +FUNC_R_OP_R(conv_sf2w, "%0 =3D convert_sf2w(%2)") +FUNC_P_OP_R(conv_sf2ud, "%0 =3D convert_sf2ud(%2)") +FUNC_P_OP_R(conv_sf2d, "%0 =3D convert_sf2d(%2)") +FUNC_R_OP_R(conv_sf2uw_chop, "%0 =3D convert_sf2uw(%2):chop") +FUNC_R_OP_R(conv_sf2w_chop, "%0 =3D convert_sf2w(%2):chop") +FUNC_P_OP_R(conv_sf2ud_chop, "%0 =3D convert_sf2ud(%2):chop") +FUNC_P_OP_R(conv_sf2d_chop, "%0 =3D convert_sf2d(%2):chop") + +/* Conversions from df */ +FUNC_R_OP_P(conv_df2sf, "%0 =3D convert_df2sf(%2)") +FUNC_R_OP_P(conv_df2uw, "%0 =3D convert_df2uw(%2)") +FUNC_R_OP_P(conv_df2w, "%0 =3D convert_df2w(%2)") +FUNC_P_OP_P(conv_df2ud, "%0 =3D convert_df2ud(%2)") +FUNC_P_OP_P(conv_df2d, "%0 =3D convert_df2d(%2)") +FUNC_R_OP_P(conv_df2uw_chop, "%0 =3D convert_df2uw(%2):chop") +FUNC_R_OP_P(conv_df2w_chop, "%0 =3D convert_df2w(%2):chop") +FUNC_P_OP_P(conv_df2ud_chop, "%0 =3D convert_df2ud(%2):chop") +FUNC_P_OP_P(conv_df2d_chop, "%0 =3D convert_df2d(%2):chop") + +/* Integer to float conversions */ +FUNC_R_OP_R(conv_uw2sf, "%0 =3D convert_uw2sf(%2)") +FUNC_R_OP_R(conv_w2sf, "%0 =3D convert_w2sf(%2)") +FUNC_R_OP_P(conv_ud2sf, "%0 =3D convert_ud2sf(%2)") +FUNC_R_OP_P(conv_d2sf, "%0 =3D convert_d2sf(%2)") + +/* Special purpose floating point instructions */ +FUNC_XR_OP_RRp(sffma_sc, "%0 +=3D sfmpy(%2, %3, p2):scale") +FUNC_Rp_OP_RR(sfrecipa, "%0, p2 =3D sfrecipa(%3, %4)") +FUNC_R_OP_RR(sffixupn, "%0 =3D sffixupn(%2, %3)") +FUNC_R_OP_RR(sffixupd, "%0 =3D sffixupd(%2, %3)") +FUNC_R_OP_R(sffixupr, "%0 =3D sffixupr(%2)") +FUNC_Rp_OP_R(sfinvsqrta, "%0, p2 =3D sfinvsqrta(%3)") + /* * Templates for test cases * @@ -554,6 +668,24 @@ TEST_Xxp_OP_xx(uint64_t, check64, uint64_t, uint64_t, = FUNC, RESIN, SRC1, SRC2, \ TEST_Xx_OP_xxp(uint32_t, check32, uint32_t, uint32_t, \ FUNC, RESIN, SRC1, SRC2, PRED, RES, USR_RES) =20 +#define TEST_CMP_xx(SRC1TYPE, SRC2TYPE, \ + FUNC, SRC1, SRC2, RES, USR_RES) \ + do { \ + uint32_t result; \ + SRC1TYPE src1 =3D SRC1; \ + SRC2TYPE src2 =3D SRC2; \ + uint32_t usr_result; \ + result =3D FUNC(src1, src2, &usr_result); \ + check(result, RES); \ + check(usr_result, USR_RES); \ + } while (0) + +#define TEST_CMP_RR(FUNC, SRC1, SRC2, RES, USR_RES) \ +TEST_CMP_xx(uint32_t, uint32_t, FUNC, SRC1, SRC2, RES, USR_RES) + +#define TEST_CMP_PP(FUNC, SRC1, SRC2, RES, USR_RES) \ +TEST_CMP_xx(uint64_t, uint64_t, FUNC, SRC1, SRC2, RES, USR_RES) + int main() { TEST_R_OP_R(satub, 0, 0, USR_CLEAR); @@ -793,6 +925,213 @@ int main() 0x000a0fff000d0000ULL, 0x000e7fff000f0004ULL, 0xf0, USR_OVF); =20 + /* Floating point */ + TEST_R_OP_RR(sfmin, SF_one, SF_small_neg, SF_small_neg, USR_CL= EAR); + TEST_R_OP_RR(sfmin, SF_one, SF_SNaN, SF_one, USR_FP= INVF); + TEST_R_OP_RR(sfmin, SF_SNaN, SF_one, SF_one, USR_FP= INVF); + TEST_R_OP_RR(sfmin, SF_one, SF_QNaN, SF_one, USR_CL= EAR); + TEST_R_OP_RR(sfmin, SF_QNaN, SF_one, SF_one, USR_CL= EAR); + TEST_R_OP_RR(sfmin, SF_SNaN, SF_QNaN, SF_HEX_NaN, USR_FP= INVF); + TEST_R_OP_RR(sfmin, SF_QNaN, SF_SNaN, SF_HEX_NaN, USR_FP= INVF); + + TEST_R_OP_RR(sfmax, SF_one, SF_small_neg, SF_one, USR_CL= EAR); + TEST_R_OP_RR(sfmax, SF_one, SF_SNaN, SF_one, USR_FP= INVF); + TEST_R_OP_RR(sfmax, SF_SNaN, SF_one, SF_one, USR_FP= INVF); + TEST_R_OP_RR(sfmax, SF_one, SF_QNaN, SF_one, USR_CL= EAR); + TEST_R_OP_RR(sfmax, SF_QNaN, SF_one, SF_one, USR_CL= EAR); + TEST_R_OP_RR(sfmax, SF_SNaN, SF_QNaN, SF_HEX_NaN, USR_FP= INVF); + TEST_R_OP_RR(sfmax, SF_QNaN, SF_SNaN, SF_HEX_NaN, USR_FP= INVF); + + TEST_R_OP_RR(sfadd, SF_one, SF_QNaN, SF_HEX_NaN, USR_CL= EAR); + TEST_R_OP_RR(sfadd, SF_one, SF_SNaN, SF_HEX_NaN, USR_FP= INVF); + TEST_R_OP_RR(sfadd, SF_QNaN, SF_SNaN, SF_HEX_NaN, USR_FP= INVF); + TEST_R_OP_RR(sfadd, SF_SNaN, SF_QNaN, SF_HEX_NaN, USR_FP= INVF); + + TEST_R_OP_RR(sfsub, SF_one, SF_QNaN, SF_HEX_NaN, USR_CL= EAR); + TEST_R_OP_RR(sfsub, SF_one, SF_SNaN, SF_HEX_NaN, USR_FP= INVF); + TEST_R_OP_RR(sfsub, SF_QNaN, SF_SNaN, SF_HEX_NaN, USR_FP= INVF); + TEST_R_OP_RR(sfsub, SF_SNaN, SF_QNaN, SF_HEX_NaN, USR_FP= INVF); + + TEST_R_OP_RR(sfmpy, SF_one, SF_QNaN, SF_HEX_NaN, USR_CL= EAR); + TEST_R_OP_RR(sfmpy, SF_one, SF_SNaN, SF_HEX_NaN, USR_FP= INVF); + TEST_R_OP_RR(sfmpy, SF_QNaN, SF_SNaN, SF_HEX_NaN, USR_FP= INVF); + TEST_R_OP_RR(sfmpy, SF_SNaN, SF_QNaN, SF_HEX_NaN, USR_FP= INVF); + + TEST_XR_OP_RR(sffma, SF_one, SF_one, SF_one, SF_two, USR_CL= EAR); + TEST_XR_OP_RR(sffma, SF_zero, SF_one, SF_QNaN, SF_HEX_NaN, USR_CL= EAR); + TEST_XR_OP_RR(sffma, SF_zero, SF_one, SF_SNaN, SF_HEX_NaN, USR_FP= INVF); + TEST_XR_OP_RR(sffma, SF_zero, SF_QNaN, SF_SNaN, SF_HEX_NaN, USR_FP= INVF); + TEST_XR_OP_RR(sffma, SF_zero, SF_SNaN, SF_QNaN, SF_HEX_NaN, USR_FP= INVF); + + TEST_XR_OP_RR(sffms, SF_one, SF_one, SF_one, SF_zero, USR_CL= EAR); + TEST_XR_OP_RR(sffms, SF_zero, SF_one, SF_QNaN, SF_HEX_NaN, USR_CL= EAR); + TEST_XR_OP_RR(sffms, SF_zero, SF_one, SF_SNaN, SF_HEX_NaN, USR_FP= INVF); + TEST_XR_OP_RR(sffms, SF_zero, SF_QNaN, SF_SNaN, SF_HEX_NaN, USR_FP= INVF); + TEST_XR_OP_RR(sffms, SF_zero, SF_SNaN, SF_QNaN, SF_HEX_NaN, USR_FP= INVF); + + TEST_CMP_RR(sfcmpuo, SF_one, SF_large_pos, 0x00, USR_CLEAR); + TEST_CMP_RR(sfcmpuo, SF_INF, SF_large_pos, 0x00, USR_CLEAR); + TEST_CMP_RR(sfcmpuo, SF_QNaN, SF_large_pos, 0xff, USR_CLEAR); + TEST_CMP_RR(sfcmpuo, SF_QNaN_neg, SF_large_pos, 0xff, USR_CLEAR); + TEST_CMP_RR(sfcmpuo, SF_SNaN, SF_large_pos, 0xff, USR_FPINVF= ); + TEST_CMP_RR(sfcmpuo, SF_SNaN_neg, SF_large_pos, 0xff, USR_FPINVF= ); + TEST_CMP_RR(sfcmpuo, SF_QNaN, SF_QNaN, 0xff, USR_CLEAR); + TEST_CMP_RR(sfcmpuo, SF_QNaN, SF_SNaN, 0xff, USR_FPINVF= ); + + TEST_CMP_RR(sfcmpeq, SF_one, SF_QNaN, 0x00, USR_CLEAR); + TEST_CMP_RR(sfcmpeq, SF_one, SF_SNaN, 0x00, USR_FPINVF= ); + TEST_CMP_RR(sfcmpgt, SF_one, SF_QNaN, 0x00, USR_CLEAR); + TEST_CMP_RR(sfcmpgt, SF_one, SF_SNaN, 0x00, USR_FPINVF= ); + TEST_CMP_RR(sfcmpge, SF_one, SF_QNaN, 0x00, USR_CLEAR); + TEST_CMP_RR(sfcmpge, SF_one, SF_SNaN, 0x00, USR_FPINVF= ); + + TEST_P_OP_PP(dfadd, DF_any, DF_QNaN, DF_HEX_NaN, USR_CL= EAR); + TEST_P_OP_PP(dfadd, DF_any, DF_SNaN, DF_HEX_NaN, USR_FP= INVF); + TEST_P_OP_PP(dfadd, DF_QNaN, DF_SNaN, DF_HEX_NaN, USR_FP= INVF); + TEST_P_OP_PP(dfadd, DF_SNaN, DF_QNaN, DF_HEX_NaN, USR_FP= INVF); + + TEST_P_OP_PP(dfsub, DF_any, DF_QNaN, DF_HEX_NaN, USR_CL= EAR); + TEST_P_OP_PP(dfsub, DF_any, DF_SNaN, DF_HEX_NaN, USR_FP= INVF); + TEST_P_OP_PP(dfsub, DF_QNaN, DF_SNaN, DF_HEX_NaN, USR_FP= INVF); + TEST_P_OP_PP(dfsub, DF_SNaN, DF_QNaN, DF_HEX_NaN, USR_FP= INVF); + +#if CORE_IS_V67 + TEST_P_OP_PP(dfmin, DF_any, DF_small_neg, DF_small_neg, USR_CL= EAR); + TEST_P_OP_PP(dfmin, DF_any, DF_SNaN, DF_any, USR_FP= INVF); + TEST_P_OP_PP(dfmin, DF_SNaN, DF_any, DF_any, USR_FP= INVF); + TEST_P_OP_PP(dfmin, DF_any, DF_QNaN, DF_any, USR_FP= INVF); + TEST_P_OP_PP(dfmin, DF_QNaN, DF_any, DF_any, USR_FP= INVF); + TEST_P_OP_PP(dfmin, DF_SNaN, DF_QNaN, DF_HEX_NaN, USR_FP= INVF); + TEST_P_OP_PP(dfmin, DF_QNaN, DF_SNaN, DF_HEX_NaN, USR_FP= INVF); + + TEST_P_OP_PP(dfmax, DF_any, DF_small_neg, DF_any, USR_CL= EAR); + TEST_P_OP_PP(dfmax, DF_any, DF_SNaN, DF_any, USR_FP= INVF); + TEST_P_OP_PP(dfmax, DF_SNaN, DF_any, DF_any, USR_FP= INVF); + TEST_P_OP_PP(dfmax, DF_any, DF_QNaN, DF_any, USR_FP= INVF); + TEST_P_OP_PP(dfmax, DF_QNaN, DF_any, DF_any, USR_FP= INVF); + TEST_P_OP_PP(dfmax, DF_SNaN, DF_QNaN, DF_HEX_NaN, USR_FP= INVF); + TEST_P_OP_PP(dfmax, DF_QNaN, DF_SNaN, DF_HEX_NaN, USR_FP= INVF); + + TEST_XP_OP_PP(dfmpyhh, DF_one, DF_one, DF_one, DF_one_hh, USR_CL= EAR); + TEST_XP_OP_PP(dfmpyhh, DF_zero, DF_any, DF_QNaN, DF_HEX_NaN, USR_CL= EAR); + TEST_XP_OP_PP(dfmpyhh, DF_zero, DF_any, DF_SNaN, DF_HEX_NaN, USR_FP= INVF); + TEST_XP_OP_PP(dfmpyhh, DF_zero, DF_QNaN, DF_SNaN, DF_HEX_NaN, USR_FP= INVF); + TEST_XP_OP_PP(dfmpyhh, DF_zero, DF_SNaN, DF_QNaN, DF_HEX_NaN, USR_FP= INVF); +#else + printf("v67 instructions skipped\n"); +#endif + + TEST_CMP_PP(dfcmpuo, DF_small_neg, DF_any, 0x00, USR_CLEAR= ); + TEST_CMP_PP(dfcmpuo, DF_large_pos, DF_any, 0x00, USR_CLEAR= ); + TEST_CMP_PP(dfcmpuo, DF_QNaN, DF_any, 0xff, USR_CLEAR= ); + TEST_CMP_PP(dfcmpuo, DF_QNaN_neg, DF_any, 0xff, USR_CLEAR= ); + TEST_CMP_PP(dfcmpuo, DF_SNaN, DF_any, 0xff, USR_FPINV= F); + TEST_CMP_PP(dfcmpuo, DF_SNaN_neg, DF_any, 0xff, USR_FPINV= F); + TEST_CMP_PP(dfcmpuo, DF_QNaN, DF_QNaN, 0xff, USR_CLEAR= ); + TEST_CMP_PP(dfcmpuo, DF_QNaN, DF_SNaN, 0xff, USR_FPINV= F); + + TEST_CMP_PP(dfcmpeq, DF_any, DF_QNaN, 0x00, USR_CLEAR= ); + TEST_CMP_PP(dfcmpeq, DF_any, DF_SNaN, 0x00, USR_FPINV= F); + TEST_CMP_PP(dfcmpgt, DF_any, DF_QNaN, 0x00, USR_CLEAR= ); + TEST_CMP_PP(dfcmpgt, DF_any, DF_SNaN, 0x00, USR_FPINV= F); + TEST_CMP_PP(dfcmpge, DF_any, DF_QNaN, 0x00, USR_CLEAR= ); + TEST_CMP_PP(dfcmpge, DF_any, DF_SNaN, 0x00, USR_FPINV= F); + + TEST_P_OP_R(conv_sf2df, SF_QNaN, DF_HEX_NaN, USR_CL= EAR); + TEST_P_OP_R(conv_sf2df, SF_SNaN, DF_HEX_NaN, USR_FP= INVF); + TEST_R_OP_R(conv_sf2uw, SF_QNaN, 0xffffffff, USR_FP= INVF); + TEST_R_OP_R(conv_sf2uw, SF_SNaN, 0xffffffff, USR_FP= INVF); + TEST_R_OP_R(conv_sf2w, SF_QNaN, 0xffffffff, USR_FP= INVF); + TEST_R_OP_R(conv_sf2w, SF_SNaN, 0xffffffff, USR_FP= INVF); + TEST_P_OP_R(conv_sf2ud, SF_QNaN, 0xffffffffffffffffULL, USR_FP= INVF); + TEST_P_OP_R(conv_sf2ud, SF_SNaN, 0xffffffffffffffffULL, USR_FP= INVF); + TEST_P_OP_R(conv_sf2d, SF_QNaN, 0xffffffffffffffffULL, USR_FP= INVF); + TEST_P_OP_R(conv_sf2d, SF_SNaN, 0xffffffffffffffffULL, USR_FP= INVF); + TEST_R_OP_R(conv_sf2uw_chop, SF_QNaN, 0xffffffff, USR_FP= INVF); + TEST_R_OP_R(conv_sf2uw_chop, SF_SNaN, 0xffffffff, USR_FP= INVF); + TEST_R_OP_R(conv_sf2w_chop, SF_QNaN, 0xffffffff, USR_FP= INVF); + TEST_R_OP_R(conv_sf2w_chop, SF_SNaN, 0xffffffff, USR_FP= INVF); + TEST_P_OP_R(conv_sf2ud_chop, SF_QNaN, 0xffffffffffffffffULL, USR_FP= INVF); + TEST_P_OP_R(conv_sf2ud_chop, SF_SNaN, 0xffffffffffffffffULL, USR_FP= INVF); + TEST_P_OP_R(conv_sf2d_chop, SF_QNaN, 0xffffffffffffffffULL, USR_FP= INVF); + TEST_P_OP_R(conv_sf2d_chop, SF_SNaN, 0xffffffffffffffffULL, USR_FP= INVF); + + TEST_R_OP_P(conv_df2sf, DF_QNaN, SF_HEX_NaN, USR_CL= EAR); + TEST_R_OP_P(conv_df2sf, DF_SNaN, SF_HEX_NaN, USR_FP= INVF); + TEST_R_OP_P(conv_df2uw, DF_QNaN, 0xffffffff, USR_FP= INVF); + TEST_R_OP_P(conv_df2uw, DF_SNaN, 0xffffffff, USR_FP= INVF); + TEST_R_OP_P(conv_df2w, DF_QNaN, 0xffffffff, USR_FP= INVF); + TEST_R_OP_P(conv_df2w, DF_SNaN, 0xffffffff, USR_FP= INVF); + TEST_P_OP_P(conv_df2ud, DF_QNaN, 0xffffffffffffffffULL, USR_FP= INVF); + TEST_P_OP_P(conv_df2ud, DF_SNaN, 0xffffffffffffffffULL, USR_FP= INVF); + TEST_P_OP_P(conv_df2d, DF_QNaN, 0xffffffffffffffffULL, USR_FP= INVF); + TEST_P_OP_P(conv_df2d, DF_SNaN, 0xffffffffffffffffULL, USR_FP= INVF); + TEST_R_OP_P(conv_df2uw_chop, DF_QNaN, 0xffffffff, USR_FP= INVF); + TEST_R_OP_P(conv_df2uw_chop, DF_SNaN, 0xffffffff, USR_FP= INVF); + TEST_R_OP_P(conv_df2w_chop, DF_QNaN, 0xffffffff, USR_FP= INVF); + TEST_R_OP_P(conv_df2w_chop, DF_SNaN, 0xffffffff, USR_FP= INVF); + TEST_P_OP_P(conv_df2ud_chop, DF_QNaN, 0xffffffffffffffffULL, USR_FP= INVF); + TEST_P_OP_P(conv_df2ud_chop, DF_SNaN, 0xffffffffffffffffULL, USR_FP= INVF); + TEST_P_OP_P(conv_df2d_chop, DF_QNaN, 0xffffffffffffffffULL, USR_FP= INVF); + TEST_P_OP_P(conv_df2d_chop, DF_SNaN, 0xffffffffffffffffULL, USR_FP= INVF); + + TEST_R_OP_R(conv_uw2sf, 0x00000001, SF_one, USR_CL= EAR); + TEST_R_OP_R(conv_uw2sf, 0x010020a5, 0x4b801052, USR_FP= INPF); + TEST_R_OP_R(conv_w2sf, 0x00000001, SF_one, USR_CL= EAR); + TEST_R_OP_R(conv_w2sf, 0x010020a5, 0x4b801052, USR_FP= INPF); + TEST_R_OP_P(conv_ud2sf, 0x0000000000000001ULL, SF_one, USR_CL= EAR); + TEST_R_OP_P(conv_ud2sf, 0x00000000010020a5ULL, 0x4b801052, USR_FP= INPF); + TEST_R_OP_P(conv_d2sf, 0x0000000000000001ULL, SF_one, USR_CL= EAR); + TEST_R_OP_P(conv_d2sf, 0x00000000010020a5ULL, 0x4b801052, USR_FP= INPF); + + TEST_XR_OP_RRp(sffma_sc, SF_one, SF_one, SF_one, 1, SF_four, + USR_CLEAR); + TEST_XR_OP_RRp(sffma_sc, SF_QNaN, SF_one, SF_one, 1, SF_HEX_NaN, + USR_CLEAR); + TEST_XR_OP_RRp(sffma_sc, SF_one, SF_QNaN, SF_one, 1, SF_HEX_NaN, + USR_CLEAR); + TEST_XR_OP_RRp(sffma_sc, SF_one, SF_one, SF_QNaN, 1, SF_HEX_NaN, + USR_CLEAR); + TEST_XR_OP_RRp(sffma_sc, SF_SNaN, SF_one, SF_one, 1, SF_HEX_NaN, + USR_FPINVF); + TEST_XR_OP_RRp(sffma_sc, SF_one, SF_SNaN, SF_one, 1, SF_HEX_NaN, + USR_FPINVF); + TEST_XR_OP_RRp(sffma_sc, SF_one, SF_one, SF_SNaN, 1, SF_HEX_NaN, + USR_FPINVF); + + TEST_Rp_OP_RR(sfrecipa, SF_one, SF_one, SF_one_recip, 0x00, + USR_CLEAR); + TEST_Rp_OP_RR(sfrecipa, SF_QNaN, SF_one, SF_HEX_NaN, 0x00, + USR_CLEAR); + TEST_Rp_OP_RR(sfrecipa, SF_one, SF_QNaN, SF_HEX_NaN, 0x00, + USR_CLEAR); + TEST_Rp_OP_RR(sfrecipa, SF_one, SF_SNaN, SF_HEX_NaN, 0x00, + USR_FPINVF); + TEST_Rp_OP_RR(sfrecipa, SF_SNaN, SF_one, SF_HEX_NaN, 0x00, + USR_FPINVF); + + TEST_R_OP_RR(sffixupn, SF_one, SF_one, SF_one, USR_CLEAR); + TEST_R_OP_RR(sffixupn, SF_QNaN, SF_one, SF_HEX_NaN, USR_CLEAR); + TEST_R_OP_RR(sffixupn, SF_one, SF_QNaN, SF_HEX_NaN, USR_CLEAR); + TEST_R_OP_RR(sffixupn, SF_SNaN, SF_one, SF_HEX_NaN, USR_FPINVF= ); + TEST_R_OP_RR(sffixupn, SF_one, SF_SNaN, SF_HEX_NaN, USR_FPINVF= ); + + TEST_R_OP_RR(sffixupd, SF_one, SF_one, SF_one, USR_CLEAR); + TEST_R_OP_RR(sffixupd, SF_QNaN, SF_one, SF_HEX_NaN, USR_CLEAR); + TEST_R_OP_RR(sffixupd, SF_one, SF_QNaN, SF_HEX_NaN, USR_CLEAR); + TEST_R_OP_RR(sffixupd, SF_SNaN, SF_one, SF_HEX_NaN, USR_FPINVF= ); + TEST_R_OP_RR(sffixupd, SF_one, SF_SNaN, SF_HEX_NaN, USR_FPINVF= ); + + TEST_R_OP_R(sffixupr, SF_one, SF_one, USR_CLEAR); + TEST_R_OP_R(sffixupr, SF_QNaN, SF_HEX_NaN, USR_CLEAR); + TEST_R_OP_R(sffixupr, SF_SNaN, SF_HEX_NaN, USR_FPINVF= ); + + TEST_Rp_OP_R(sfinvsqrta, SF_one, SF_one_invsqrta, 0x00, USR_CL= EAR); + TEST_Rp_OP_R(sfinvsqrta, SF_zero, SF_one, 0x00, USR_CL= EAR); + TEST_Rp_OP_R(sfinvsqrta, SF_QNaN, SF_HEX_NaN, 0x00, USR_CL= EAR); + TEST_Rp_OP_R(sfinvsqrta, SF_small_neg, SF_HEX_NaN, 0x00, USR_FP= INVF); + TEST_Rp_OP_R(sfinvsqrta, SF_SNaN, SF_HEX_NaN, 0x00, USR_FP= INVF); + puts(err ? "FAIL" : "PASS"); return err; } --=20 2.17.1