From nobody Tue Feb 10 05:39:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644459763208902.2549458230247; Wed, 9 Feb 2022 18:22:43 -0800 (PST) Received: from localhost ([::1]:36846 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nHz6Z-0006j2-0K for importer@patchew.org; Wed, 09 Feb 2022 21:22:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35962) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nHz0u-0007B2-1h for qemu-devel@nongnu.org; Wed, 09 Feb 2022 21:16:56 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:47689) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1nHz0p-0008Ve-Lw for qemu-devel@nongnu.org; Wed, 09 Feb 2022 21:16:51 -0500 Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 09 Feb 2022 18:16:02 -0800 Received: from hu-tsimpson-lv.qualcomm.com (HELO hu-devc-lv-u18-c.qualcomm.com) ([10.47.235.220]) by ironmsg07-lv.qualcomm.com with ESMTP; 09 Feb 2022 18:16:02 -0800 Received: by hu-devc-lv-u18-c.qualcomm.com (Postfix, from userid 47164) id 07B635005A2; Wed, 9 Feb 2022 18:16:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644459408; x=1675995408; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wnJyMXznj/NY6S7udslUPpj6o4RnH2MZKcgpGtQSUlg=; b=C0KtX48aCRYxWbhnw3+EaECkP1lj5iAw/bV0GbE3vCpEO1DZmymDT0xu yHBPCPhKKbKj5Ll+IGBnyDOTjYYjGxfWrNG24UupeLjRVabFe51czjxLj LbuQix2vPV6XQlNx7ubW99gJwF09yL/rCZvFRZNg8fEn8Nt9alHRYon8J E=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH v2 11/12] Hexagon (target/hexagon) make VyV operands use a unique temp Date: Wed, 9 Feb 2022 18:15:55 -0800 Message-Id: <20220210021556.9217-12-tsimpson@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220210021556.9217-1-tsimpson@quicinc.com> References: <20220210021556.9217-1-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.46.98.28; envelope-from=tsimpson@qualcomm.com; helo=alexa-out.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, f4bug@amsat.org, tsimpson@quicinc.com, mlambert@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1644459764880100001 VyV operand is only used in the vshuff and vdeal instructions. These instructions write to both VyV and VxV operands. In the case where both operands are the same register, we need a separate location for VyV. We use the existing vtmp field in CPUHexagonState. Test case added in tests/tcg/hexagon/hvx_misc.c Signed-off-by: Taylor Simpson --- tests/tcg/hexagon/hvx_misc.c | 45 +++++++++++++++++++++++++++++++++ target/hexagon/gen_tcg_funcs.py | 9 +++---- 2 files changed, 49 insertions(+), 5 deletions(-) diff --git a/tests/tcg/hexagon/hvx_misc.c b/tests/tcg/hexagon/hvx_misc.c index b896f5897e..6e2c9ab3cd 100644 --- a/tests/tcg/hexagon/hvx_misc.c +++ b/tests/tcg/hexagon/hvx_misc.c @@ -498,6 +498,49 @@ static void test_vsubuwsat_dv(void) check_output_w(__LINE__, 2); } =20 +static void test_vshuff(void) +{ + /* Test that vshuff works when the two operands are the same register = */ + const uint32_t splat =3D 0x089be55c; + const uint32_t shuff =3D 0x454fa926; + MMVector v0, v1; + + memset(expect, 0x12, sizeof(MMVector)); + memset(output, 0x34, sizeof(MMVector)); + + asm volatile("v25 =3D vsplat(%0)\n\t" + "vshuff(v25, v25, %1)\n\t" + "vmem(%2 + #0) =3D v25\n\t" + : /* no outputs */ + : "r"(splat), "r"(shuff), "r"(output) + : "v25", "memory"); + + /* + * The semantics of Hexagon are the operands are pass-by-value, so cre= ate + * two copies of the vsplat result. + */ + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { + v0.uw[i] =3D splat; + v1.uw[i] =3D splat; + } + /* Do the vshuff operation */ + for (int offset =3D 1; offset < MAX_VEC_SIZE_BYTES; offset <<=3D 1) { + if (shuff & offset) { + for (int k =3D 0; k < MAX_VEC_SIZE_BYTES; k++) { + if (!(k & offset)) { + uint8_t tmp =3D v0.ub[k]; + v0.ub[k] =3D v1.ub[k + offset]; + v1.ub[k + offset] =3D tmp; + } + } + } + } + /* Put the result in the expect buffer for verification */ + expect[0] =3D v1; + + check_output_b(__LINE__, 1); +} + int main() { init_buffers(); @@ -533,6 +576,8 @@ int main() test_vadduwsat(); test_vsubuwsat_dv(); =20 + test_vshuff(); + puts(err ? "FAIL" : "PASS"); return err ? 1 : 0; } diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index 1fd9de95d5..d72c689ad7 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 =20 ## -## Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. +## Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Res= erved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -164,7 +164,9 @@ def genptr_decl(f, tag, regtype, regid, regno): (regtype, regid, regno)) f.write(" const intptr_t %s%sV_off =3D\n" % \ (regtype, regid)) - if (hex_common.is_tmp_result(tag)): + if (regid =3D=3D "y"): + f.write(" offsetof(CPUHexagonState, vtmp);\n") + elif (hex_common.is_tmp_result(tag)): f.write(" ctx_tmp_vreg_off(ctx, %s%sN, 1, true);\n"= % \ (regtype, regid)) else: @@ -379,9 +381,6 @@ def genptr_src_read(f, tag, regtype, regid): f.write(" vreg_src_off(ctx, %s%sN),\n" % \ (regtype, regid)) f.write(" sizeof(MMVector), sizeof(MMVector));\n") - if (not hex_common.skip_qemu_helper(tag)): - f.write(" tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\= n" % \ - (regtype, regid, regtype, regid)) else: print("Bad register parse: ", regtype, regid) elif (regtype =3D=3D "Q"): --=20 2.17.1