From nobody Mon Feb 9 04:14:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644027077222113.23808133071464; Fri, 4 Feb 2022 18:11:17 -0800 (PST) Received: from localhost ([::1]:60060 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nGAXj-0002ki-Vd for importer@patchew.org; Fri, 04 Feb 2022 21:11:16 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50410) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nGA7O-0003xc-3y for qemu-devel@nongnu.org; Fri, 04 Feb 2022 20:44:02 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]:34301) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nGA7I-0003PQ-2b for qemu-devel@nongnu.org; Fri, 04 Feb 2022 20:44:01 -0500 Received: from mail-wr1-f70.google.com (mail-wr1-f70.google.com [209.85.221.70]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-56-4hZPU3cBNQik0yVfqiu-lQ-1; Fri, 04 Feb 2022 20:43:53 -0500 Received: by mail-wr1-f70.google.com with SMTP id g17-20020adfa591000000b001da86c91c22so2800793wrc.5 for ; Fri, 04 Feb 2022 17:43:53 -0800 (PST) Received: from redhat.com ([2a10:8005:331d:0:5c51:c095:613e:277c]) by smtp.gmail.com with ESMTPSA id i13sm4110189wrf.3.2022.02.04.17.43.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 17:43:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1644025435; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=md+0x/hL3eI2WJAyKsSmYY0vg8hYC+rd2o6i0IUdA18=; b=bfl6hdLxQJm0uvSwYBMYoEr/gltghKDslEum4T3512KAIwhjdJqTs2n1BM4nSYzVHRCMgB CPSN2UrqReETVz8d44HBeJGzrCN/6R5ZiDVQIMD73cifFc0ZkzCPM8ZeuH2+RVjvWcjaYV iinSJKRQpoaImfxZW1qcC0u/Wzob+0w= X-MC-Unique: 4hZPU3cBNQik0yVfqiu-lQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=md+0x/hL3eI2WJAyKsSmYY0vg8hYC+rd2o6i0IUdA18=; b=S4IGl5kyzCJOgyvVK/xwNPMJ2HfjE52N4OmWom0+7icScrbAxm81uqSnquwdvi6VM+ 9yeAKz9F5fPs15SJLvUsrixuoMYlknDW+UwB0pvwfnxbKiHtVrpFlPgBb/xs0udPyFfD 431pYljvtDfWjYRO/rNRNlnaN2Ygsybz1Qq3r6j6+IgWimQjWpLCFj8VOu45EYOVB8nZ usQ1An/MnZhVX/rF4nvW8FvIGROPNXDvFfcYKaYwU5RX62Dtwemqsv/ByISsqUcrhq4z NbTCSjfHNVnaI8CEqKymtG0JQHa6J5zdNz2ajqdkR3kGnd2N+7pMkCdyZXKvCBegRHc3 AArA== X-Gm-Message-State: AOAM531wGj1yLl/9pbRAVsY7d/XaiqyRJ+DeGVfsfUR7gE79u0gFVbY/ +kbpQ4ZmwJ+BfbPGqsT6Bx+rioqDgSMqEwMiwMmJruazJK4ZVD56b5P3cw+ylbA3JdlHuJM73Fh ItTs1VT3zCSqczkQcV9K5iHMFspaNMUWjCPwY+pPnm95NVy2k2tTX21Hh/Uyx X-Received: by 2002:a5d:548a:: with SMTP id h10mr1230667wrv.221.1644025431670; Fri, 04 Feb 2022 17:43:51 -0800 (PST) X-Google-Smtp-Source: ABdhPJzkmfucGkdhuUpnku3kFNvBhUFWuQy/NZ3L+huYGqwdiIIk8x05I9V/WQbWqbGIdk4XtxF38A== X-Received: by 2002:a5d:548a:: with SMTP id h10mr1230650wrv.221.1644025431194; Fri, 04 Feb 2022 17:43:51 -0800 (PST) Date: Fri, 4 Feb 2022 20:43:49 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Subject: [PULL 26/32] ACPI ERST: support for ACPI ERST feature Message-ID: <20220205014149.1189026-27-mst@redhat.com> References: <20220205014149.1189026-1-mst@redhat.com> MIME-Version: 1.0 In-Reply-To: <20220205014149.1189026-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=mst@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Disposition: inline Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.092, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ani Sinha , Peter Maydell , Eric DeVolder , Igor Mammedov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1644027078468100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Eric DeVolder This implements a PCI device for ACPI ERST. This implements the non-NVRAM "mode" of operation for ERST as it is supported by Linux and Windows. Signed-off-by: Eric DeVolder Reviewed-by: Ani Sinha Message-Id: <1643402289-22216-6-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/acpi/erst.c | 844 +++++++++++++++++++++++++++++++++++++++++++ hw/acpi/Kconfig | 6 + hw/acpi/meson.build | 1 + hw/acpi/trace-events | 15 + 4 files changed, 866 insertions(+) create mode 100644 hw/acpi/erst.c diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c new file mode 100644 index 0000000000..fe9ba51de7 --- /dev/null +++ b/hw/acpi/erst.c @@ -0,0 +1,844 @@ +/* + * ACPI Error Record Serialization Table, ERST, Implementation + * + * ACPI ERST introduced in ACPI 4.0, June 16, 2009. + * ACPI Platform Error Interfaces : Error Serialization + * + * Copyright (c) 2021 Oracle and/or its affiliates. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/qdev-core.h" +#include "exec/memory.h" +#include "qom/object.h" +#include "hw/pci/pci.h" +#include "qom/object_interfaces.h" +#include "qemu/error-report.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/acpi-defs.h" +#include "hw/acpi/aml-build.h" +#include "hw/acpi/bios-linker-loader.h" +#include "exec/address-spaces.h" +#include "sysemu/hostmem.h" +#include "hw/acpi/erst.h" +#include "trace.h" + +/* ACPI 4.0: Table 17-16 Serialization Actions */ +#define ACTION_BEGIN_WRITE_OPERATION 0x0 +#define ACTION_BEGIN_READ_OPERATION 0x1 +#define ACTION_BEGIN_CLEAR_OPERATION 0x2 +#define ACTION_END_OPERATION 0x3 +#define ACTION_SET_RECORD_OFFSET 0x4 +#define ACTION_EXECUTE_OPERATION 0x5 +#define ACTION_CHECK_BUSY_STATUS 0x6 +#define ACTION_GET_COMMAND_STATUS 0x7 +#define ACTION_GET_RECORD_IDENTIFIER 0x8 +#define ACTION_SET_RECORD_IDENTIFIER 0x9 +#define ACTION_GET_RECORD_COUNT 0xA +#define ACTION_BEGIN_DUMMY_WRITE_OPERATION 0xB +#define ACTION_RESERVED 0xC +#define ACTION_GET_ERROR_LOG_ADDRESS_RANGE 0xD +#define ACTION_GET_ERROR_LOG_ADDRESS_LENGTH 0xE +#define ACTION_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0xF +#define ACTION_GET_EXECUTE_OPERATION_TIMINGS 0x10 /* ACPI 6.3 */ + +/* ACPI 4.0: Table 17-17 Command Status Definitions */ +#define STATUS_SUCCESS 0x00 +#define STATUS_NOT_ENOUGH_SPACE 0x01 +#define STATUS_HARDWARE_NOT_AVAILABLE 0x02 +#define STATUS_FAILED 0x03 +#define STATUS_RECORD_STORE_EMPTY 0x04 +#define STATUS_RECORD_NOT_FOUND 0x05 + +/* UEFI 2.1: Appendix N Common Platform Error Record */ +#define UEFI_CPER_RECORD_MIN_SIZE 128U +#define UEFI_CPER_RECORD_LENGTH_OFFSET 20U +#define UEFI_CPER_RECORD_ID_OFFSET 96U +#define IS_UEFI_CPER_RECORD(ptr) \ + (((ptr)[0] =3D=3D 'C') && \ + ((ptr)[1] =3D=3D 'P') && \ + ((ptr)[2] =3D=3D 'E') && \ + ((ptr)[3] =3D=3D 'R')) + +/* + * NOTE that when accessing CPER fields within a record, memcpy() + * is utilized to avoid a possible misaligned access on the host. + */ + +/* + * This implementation is an ACTION (cmd) and VALUE (data) + * interface consisting of just two 64-bit registers. + */ +#define ERST_REG_SIZE (16UL) +#define ERST_ACTION_OFFSET (0UL) /* action (cmd) */ +#define ERST_VALUE_OFFSET (8UL) /* argument/value (data) */ + +/* + * ERST_RECORD_SIZE is the buffer size for exchanging ERST + * record contents. Thus, it defines the maximum record size. + * As this is mapped through a PCI BAR, it must be a power of + * two and larger than UEFI_CPER_RECORD_MIN_SIZE. + * The backing storage is divided into fixed size "slots", + * each ERST_RECORD_SIZE in length, and each "slot" + * storing a single record. No attempt at optimizing storage + * through compression, compaction, etc is attempted. + * NOTE that slot 0 is reserved for the backing storage header. + * Depending upon the size of the backing storage, additional + * slots will be part of the slot 0 header in order to account + * for a record_id for each available remaining slot. + */ +/* 8KiB records, not too small, not too big */ +#define ERST_RECORD_SIZE (8192UL) + +#define ACPI_ERST_MEMDEV_PROP "memdev" +#define ACPI_ERST_RECORD_SIZE_PROP "record_size" + +/* + * From the ACPI ERST spec sections: + * A record id of all 0s is used to indicate 'unspecified' record id. + * A record id of all 1s is used to indicate empty or end. + */ +#define ERST_UNSPECIFIED_RECORD_ID (0UL) +#define ERST_EMPTY_END_RECORD_ID (~0UL) + +#define ERST_IS_VALID_RECORD_ID(rid) \ + ((rid !=3D ERST_UNSPECIFIED_RECORD_ID) && \ + (rid !=3D ERST_EMPTY_END_RECORD_ID)) + +/* + * Implementation-specific definitions and types. + * Values are arbitrary and chosen for this implementation. + * See erst.rst documentation for details. + */ +#define ERST_EXECUTE_OPERATION_MAGIC 0x9CUL +#define ERST_STORE_MAGIC 0x524F545354535245UL /* ERSTSTOR */ +typedef struct { + uint64_t magic; + uint32_t record_size; + uint32_t storage_offset; /* offset to record storage beyond header */ + uint16_t version; + uint16_t reserved; + uint32_t record_count; + uint64_t map[]; /* contains record_ids, and position indicates index */ +} __attribute__((packed)) ERSTStorageHeader; + +/* + * Object cast macro + */ +#define ACPIERST(obj) \ + OBJECT_CHECK(ERSTDeviceState, (obj), TYPE_ACPI_ERST) + +/* + * Main ERST device state structure + */ +typedef struct { + PCIDevice parent_obj; + + /* Backend storage */ + HostMemoryBackend *hostmem; + MemoryRegion *hostmem_mr; + uint32_t storage_size; + uint32_t default_record_size; + + /* Programming registers */ + MemoryRegion iomem_mr; + + /* Exchange buffer */ + MemoryRegion exchange_mr; + + /* Interface state */ + uint8_t operation; + uint8_t busy_status; + uint8_t command_status; + uint32_t record_offset; + uint64_t reg_action; + uint64_t reg_value; + uint64_t record_identifier; + ERSTStorageHeader *header; + unsigned first_record_index; + unsigned last_record_index; + unsigned next_record_index; + +} ERSTDeviceState; + +/*******************************************************************/ +/*******************************************************************/ +static uint8_t *get_nvram_ptr_by_index(ERSTDeviceState *s, unsigned index) +{ + uint8_t *rc =3D NULL; + off_t offset =3D (index * le32_to_cpu(s->header->record_size)); + + g_assert(offset < s->storage_size); + + rc =3D memory_region_get_ram_ptr(s->hostmem_mr); + rc +=3D offset; + + return rc; +} + +static void make_erst_storage_header(ERSTDeviceState *s) +{ + ERSTStorageHeader *header =3D s->header; + unsigned mapsz, headersz; + + header->magic =3D cpu_to_le64(ERST_STORE_MAGIC); + header->record_size =3D cpu_to_le32(s->default_record_size); + header->version =3D cpu_to_le16(0x0100); + header->reserved =3D cpu_to_le16(0x0000); + + /* Compute mapsize */ + mapsz =3D s->storage_size / s->default_record_size; + mapsz *=3D sizeof(uint64_t); + /* Compute header+map size */ + headersz =3D sizeof(ERSTStorageHeader) + mapsz; + /* Round up to nearest integer multiple of ERST_RECORD_SIZE */ + headersz =3D QEMU_ALIGN_UP(headersz, s->default_record_size); + header->storage_offset =3D cpu_to_le32(headersz); + + /* + * The HostMemoryBackend initializes contents to zero, + * so all record_ids stashed in the map are zero'd. + * As well the record_count is zero. Properly initialized. + */ +} + +static void check_erst_backend_storage(ERSTDeviceState *s, Error **errp) +{ + ERSTStorageHeader *header; + uint32_t record_size; + + header =3D memory_region_get_ram_ptr(s->hostmem_mr); + s->header =3D header; + + /* Ensure pointer to header is 64-bit aligned */ + g_assert(QEMU_PTR_IS_ALIGNED(header, sizeof(uint64_t))); + + /* + * Check if header is uninitialized; HostMemoryBackend inits to 0 + */ + if (le64_to_cpu(header->magic) =3D=3D 0UL) { + make_erst_storage_header(s); + } + + /* Validity check record_size */ + record_size =3D le32_to_cpu(header->record_size); + if (!( + (record_size) && /* non zero */ + (record_size >=3D UEFI_CPER_RECORD_MIN_SIZE) && + (((record_size - 1) & record_size) =3D=3D 0) && /* is power of 2 */ + (record_size >=3D 4096) /* PAGE_SIZE */ + )) { + error_setg(errp, "ERST record_size %u is invalid", record_size); + } + + /* Validity check header */ + if (!( + (le64_to_cpu(header->magic) =3D=3D ERST_STORE_MAGIC) && + ((le32_to_cpu(header->storage_offset) % record_size) =3D=3D 0) && + (le16_to_cpu(header->version) =3D=3D 0x0100) && + (le16_to_cpu(header->reserved) =3D=3D 0) + )) { + error_setg(errp, "ERST backend storage header is invalid"); + } + + /* Check storage_size against record_size */ + if (((s->storage_size % record_size) !=3D 0) || + (record_size > s->storage_size)) { + error_setg(errp, "ACPI ERST requires storage size be multiple of " + "record size (%uKiB)", record_size); + } + + /* Compute offset of first and last record storage slot */ + s->first_record_index =3D le32_to_cpu(header->storage_offset) + / record_size; + s->last_record_index =3D (s->storage_size / record_size); +} + +static void update_map_entry(ERSTDeviceState *s, unsigned index, + uint64_t record_id) +{ + if (index < s->last_record_index) { + s->header->map[index] =3D cpu_to_le64(record_id); + } +} + +static unsigned find_next_empty_record_index(ERSTDeviceState *s) +{ + unsigned rc =3D 0; /* 0 not a valid index */ + unsigned index =3D s->first_record_index; + + for (; index < s->last_record_index; ++index) { + if (le64_to_cpu(s->header->map[index]) =3D=3D ERST_UNSPECIFIED_REC= ORD_ID) { + rc =3D index; + break; + } + } + + return rc; +} + +static unsigned lookup_erst_record(ERSTDeviceState *s, + uint64_t record_identifier) +{ + unsigned rc =3D 0; /* 0 not a valid index */ + + /* Find the record_identifier in the map */ + if (record_identifier !=3D ERST_UNSPECIFIED_RECORD_ID) { + /* + * Count number of valid records encountered, and + * short-circuit the loop if identifier not found + */ + uint32_t record_count =3D le32_to_cpu(s->header->record_count); + unsigned count =3D 0; + unsigned index; + for (index =3D s->first_record_index; index < s->last_record_index= && + count < record_count; ++index) { + if (le64_to_cpu(s->header->map[index]) =3D=3D record_identifie= r) { + rc =3D index; + break; + } + if (le64_to_cpu(s->header->map[index]) !=3D + ERST_UNSPECIFIED_RECORD_ID) { + ++count; + } + } + } + + return rc; +} + +/* + * ACPI 4.0: 17.4.1.1 Serialization Actions, also see + * ACPI 4.0: 17.4.2.2 Operations - Reading 6.c and 2.c + */ +static unsigned get_next_record_identifier(ERSTDeviceState *s, + uint64_t *record_identifier, bool first) +{ + unsigned found =3D 0; + unsigned index; + + /* For operations needing to return 'first' record identifier */ + if (first) { + /* Reset initial index to beginning */ + s->next_record_index =3D s->first_record_index; + } + index =3D s->next_record_index; + + *record_identifier =3D ERST_EMPTY_END_RECORD_ID; + + if (le32_to_cpu(s->header->record_count)) { + for (; index < s->last_record_index; ++index) { + if (le64_to_cpu(s->header->map[index]) !=3D + ERST_UNSPECIFIED_RECORD_ID) { + /* where to start next time */ + s->next_record_index =3D index + 1; + *record_identifier =3D le64_to_cpu(s->header->map[inde= x]); + found =3D 1; + break; + } + } + } + if (!found) { + /* at end (ie scan complete), reset */ + s->next_record_index =3D s->first_record_index; + } + + return STATUS_SUCCESS; +} + +/* ACPI 4.0: 17.4.2.3 Operations - Clearing */ +static unsigned clear_erst_record(ERSTDeviceState *s) +{ + unsigned rc =3D STATUS_RECORD_NOT_FOUND; + unsigned index; + + /* Check for valid record identifier */ + if (!ERST_IS_VALID_RECORD_ID(s->record_identifier)) { + return STATUS_FAILED; + } + + index =3D lookup_erst_record(s, s->record_identifier); + if (index) { + /* No need to wipe record, just invalidate its map entry */ + uint32_t record_count; + update_map_entry(s, index, ERST_UNSPECIFIED_RECORD_ID); + record_count =3D le32_to_cpu(s->header->record_count); + record_count -=3D 1; + s->header->record_count =3D cpu_to_le32(record_count); + rc =3D STATUS_SUCCESS; + } + + return rc; +} + +/* ACPI 4.0: 17.4.2.2 Operations - Reading */ +static unsigned read_erst_record(ERSTDeviceState *s) +{ + unsigned rc =3D STATUS_RECORD_NOT_FOUND; + unsigned exchange_length; + unsigned index; + + /* Check if backend storage is empty */ + if (le32_to_cpu(s->header->record_count) =3D=3D 0) { + return STATUS_RECORD_STORE_EMPTY; + } + + exchange_length =3D memory_region_size(&s->exchange_mr); + + /* Check for record identifier of all 0s */ + if (s->record_identifier =3D=3D ERST_UNSPECIFIED_RECORD_ID) { + /* Set to 'first' record in storage */ + get_next_record_identifier(s, &s->record_identifier, true); + /* record_identifier is now a valid id, or all 1s */ + } + + /* Check for record identifier of all 1s */ + if (s->record_identifier =3D=3D ERST_EMPTY_END_RECORD_ID) { + return STATUS_FAILED; + } + + /* Validate record_offset */ + if (s->record_offset > (exchange_length - UEFI_CPER_RECORD_MIN_SIZE)) { + return STATUS_FAILED; + } + + index =3D lookup_erst_record(s, s->record_identifier); + if (index) { + uint8_t *nvram; + uint8_t *exchange; + uint32_t record_length; + + /* Obtain pointer to the exchange buffer */ + exchange =3D memory_region_get_ram_ptr(&s->exchange_mr); + exchange +=3D s->record_offset; + /* Obtain pointer to slot in storage */ + nvram =3D get_nvram_ptr_by_index(s, index); + /* Validate CPER record_length */ + memcpy((uint8_t *)&record_length, + &nvram[UEFI_CPER_RECORD_LENGTH_OFFSET], + sizeof(uint32_t)); + record_length =3D le32_to_cpu(record_length); + if (record_length < UEFI_CPER_RECORD_MIN_SIZE) { + rc =3D STATUS_FAILED; + } + if ((s->record_offset + record_length) > exchange_length) { + rc =3D STATUS_FAILED; + } + /* If all is ok, copy the record to the exchange buffer */ + if (rc !=3D STATUS_FAILED) { + memcpy(exchange, nvram, record_length); + rc =3D STATUS_SUCCESS; + } + } else { + /* + * See "Reading : 'The steps performed by the platform ...' 2.c" + * Set to 'first' record in storage + */ + get_next_record_identifier(s, &s->record_identifier, true); + } + + return rc; +} + +/* ACPI 4.0: 17.4.2.1 Operations - Writing */ +static unsigned write_erst_record(ERSTDeviceState *s) +{ + unsigned rc =3D STATUS_FAILED; + unsigned exchange_length; + unsigned index; + uint64_t record_identifier; + uint32_t record_length; + uint8_t *exchange; + uint8_t *nvram =3D NULL; + bool record_found =3D false; + + exchange_length =3D memory_region_size(&s->exchange_mr); + + /* Validate record_offset */ + if (s->record_offset > (exchange_length - UEFI_CPER_RECORD_MIN_SIZE)) { + return STATUS_FAILED; + } + + /* Obtain pointer to record in the exchange buffer */ + exchange =3D memory_region_get_ram_ptr(&s->exchange_mr); + exchange +=3D s->record_offset; + + /* Validate CPER record_length */ + memcpy((uint8_t *)&record_length, &exchange[UEFI_CPER_RECORD_LENGTH_OF= FSET], + sizeof(uint32_t)); + record_length =3D le32_to_cpu(record_length); + if (record_length < UEFI_CPER_RECORD_MIN_SIZE) { + return STATUS_FAILED; + } + if ((s->record_offset + record_length) > exchange_length) { + return STATUS_FAILED; + } + + /* Extract record identifier */ + memcpy((uint8_t *)&record_identifier, &exchange[UEFI_CPER_RECORD_ID_OF= FSET], + sizeof(uint64_t)); + record_identifier =3D le64_to_cpu(record_identifier); + + /* Check for valid record identifier */ + if (!ERST_IS_VALID_RECORD_ID(record_identifier)) { + return STATUS_FAILED; + } + + index =3D lookup_erst_record(s, record_identifier); + if (index) { + /* Record found, overwrite existing record */ + nvram =3D get_nvram_ptr_by_index(s, index); + record_found =3D true; + } else { + /* Record not found, not an overwrite, allocate for write */ + index =3D find_next_empty_record_index(s); + if (index) { + nvram =3D get_nvram_ptr_by_index(s, index); + } else { + /* All slots are occupied */ + rc =3D STATUS_NOT_ENOUGH_SPACE; + } + } + if (nvram) { + /* Write the record into the slot */ + memcpy(nvram, exchange, record_length); + memset(nvram + record_length, exchange_length - record_length, 0xF= F); + /* If a new record, increment the record_count */ + if (!record_found) { + uint32_t record_count; + record_count =3D le32_to_cpu(s->header->record_count); + record_count +=3D 1; /* writing new record */ + s->header->record_count =3D cpu_to_le32(record_count); + } + update_map_entry(s, index, record_identifier); + rc =3D STATUS_SUCCESS; + } + + return rc; +} + +/*******************************************************************/ + +static uint64_t erst_rd_reg64(hwaddr addr, + uint64_t reg, unsigned size) +{ + uint64_t rdval; + uint64_t mask; + unsigned shift; + + if (size =3D=3D sizeof(uint64_t)) { + /* 64b access */ + mask =3D 0xFFFFFFFFFFFFFFFFUL; + shift =3D 0; + } else { + /* 32b access */ + mask =3D 0x00000000FFFFFFFFUL; + shift =3D ((addr & 0x4) =3D=3D 0x4) ? 32 : 0; + } + + rdval =3D reg; + rdval >>=3D shift; + rdval &=3D mask; + + return rdval; +} + +static uint64_t erst_wr_reg64(hwaddr addr, + uint64_t reg, uint64_t val, unsigned size) +{ + uint64_t wrval; + uint64_t mask; + unsigned shift; + + if (size =3D=3D sizeof(uint64_t)) { + /* 64b access */ + mask =3D 0xFFFFFFFFFFFFFFFFUL; + shift =3D 0; + } else { + /* 32b access */ + mask =3D 0x00000000FFFFFFFFUL; + shift =3D ((addr & 0x4) =3D=3D 0x4) ? 32 : 0; + } + + val &=3D mask; + val <<=3D shift; + mask <<=3D shift; + wrval =3D reg; + wrval &=3D ~mask; + wrval |=3D val; + + return wrval; +} + +static void erst_reg_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + ERSTDeviceState *s =3D (ERSTDeviceState *)opaque; + + /* + * NOTE: All actions/operations/side effects happen on the WRITE, + * by this implementation's design. The READs simply return the + * reg_value contents. + */ + trace_acpi_erst_reg_write(addr, val, size); + + switch (addr) { + case ERST_VALUE_OFFSET + 0: + case ERST_VALUE_OFFSET + 4: + s->reg_value =3D erst_wr_reg64(addr, s->reg_value, val, size); + break; + case ERST_ACTION_OFFSET + 0: + /* + * NOTE: all valid values written to this register are of the + * ACTION_* variety. Thus there is no need to make this a 64-bit + * register, 32-bits is appropriate. As such ERST_ACTION_OFFSET+4 + * is not needed. + */ + switch (val) { + case ACTION_BEGIN_WRITE_OPERATION: + case ACTION_BEGIN_READ_OPERATION: + case ACTION_BEGIN_CLEAR_OPERATION: + case ACTION_BEGIN_DUMMY_WRITE_OPERATION: + case ACTION_END_OPERATION: + s->operation =3D val; + break; + case ACTION_SET_RECORD_OFFSET: + s->record_offset =3D s->reg_value; + break; + case ACTION_EXECUTE_OPERATION: + if ((uint8_t)s->reg_value =3D=3D ERST_EXECUTE_OPERATION_MAGIC)= { + s->busy_status =3D 1; + switch (s->operation) { + case ACTION_BEGIN_WRITE_OPERATION: + s->command_status =3D write_erst_record(s); + break; + case ACTION_BEGIN_READ_OPERATION: + s->command_status =3D read_erst_record(s); + break; + case ACTION_BEGIN_CLEAR_OPERATION: + s->command_status =3D clear_erst_record(s); + break; + case ACTION_BEGIN_DUMMY_WRITE_OPERATION: + s->command_status =3D STATUS_SUCCESS; + break; + case ACTION_END_OPERATION: + s->command_status =3D STATUS_SUCCESS; + break; + default: + s->command_status =3D STATUS_FAILED; + break; + } + s->busy_status =3D 0; + } + break; + case ACTION_CHECK_BUSY_STATUS: + s->reg_value =3D s->busy_status; + break; + case ACTION_GET_COMMAND_STATUS: + s->reg_value =3D s->command_status; + break; + case ACTION_GET_RECORD_IDENTIFIER: + s->command_status =3D get_next_record_identifier(s, + &s->reg_value, false); + break; + case ACTION_SET_RECORD_IDENTIFIER: + s->record_identifier =3D s->reg_value; + break; + case ACTION_GET_RECORD_COUNT: + s->reg_value =3D le32_to_cpu(s->header->record_count); + break; + case ACTION_GET_ERROR_LOG_ADDRESS_RANGE: + s->reg_value =3D (hwaddr)pci_get_bar_addr(PCI_DEVICE(s), 1); + break; + case ACTION_GET_ERROR_LOG_ADDRESS_LENGTH: + s->reg_value =3D le32_to_cpu(s->header->record_size); + break; + case ACTION_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES: + s->reg_value =3D 0x0; /* intentional, not NVRAM mode */ + break; + case ACTION_GET_EXECUTE_OPERATION_TIMINGS: + s->reg_value =3D + (100ULL << 32) | /* 100us max time */ + (10ULL << 0) ; /* 10us min time */ + break; + default: + /* Unknown action/command, NOP */ + break; + } + break; + default: + /* This should not happen, but if it does, NOP */ + break; + } +} + +static uint64_t erst_reg_read(void *opaque, hwaddr addr, + unsigned size) +{ + ERSTDeviceState *s =3D (ERSTDeviceState *)opaque; + uint64_t val =3D 0; + + switch (addr) { + case ERST_ACTION_OFFSET + 0: + case ERST_ACTION_OFFSET + 4: + val =3D erst_rd_reg64(addr, s->reg_action, size); + break; + case ERST_VALUE_OFFSET + 0: + case ERST_VALUE_OFFSET + 4: + val =3D erst_rd_reg64(addr, s->reg_value, size); + break; + default: + break; + } + trace_acpi_erst_reg_read(addr, val, size); + return val; +} + +static const MemoryRegionOps erst_reg_ops =3D { + .read =3D erst_reg_read, + .write =3D erst_reg_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +/*******************************************************************/ +/*******************************************************************/ +static int erst_post_load(void *opaque, int version_id) +{ + ERSTDeviceState *s =3D opaque; + + /* Recompute pointer to header */ + s->header =3D (ERSTStorageHeader *)get_nvram_ptr_by_index(s, 0); + trace_acpi_erst_post_load(s->header, le32_to_cpu(s->header->record_siz= e)); + + return 0; +} + +static const VMStateDescription erst_vmstate =3D { + .name =3D "acpi-erst", + .version_id =3D 1, + .minimum_version_id =3D 1, + .post_load =3D erst_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8(operation, ERSTDeviceState), + VMSTATE_UINT8(busy_status, ERSTDeviceState), + VMSTATE_UINT8(command_status, ERSTDeviceState), + VMSTATE_UINT32(record_offset, ERSTDeviceState), + VMSTATE_UINT64(reg_action, ERSTDeviceState), + VMSTATE_UINT64(reg_value, ERSTDeviceState), + VMSTATE_UINT64(record_identifier, ERSTDeviceState), + VMSTATE_UINT32(next_record_index, ERSTDeviceState), + VMSTATE_END_OF_LIST() + } +}; + +static void erst_realizefn(PCIDevice *pci_dev, Error **errp) +{ + ERSTDeviceState *s =3D ACPIERST(pci_dev); + + trace_acpi_erst_realizefn_in(); + + if (!s->hostmem) { + error_setg(errp, "'" ACPI_ERST_MEMDEV_PROP "' property is not set"= ); + return; + } else if (host_memory_backend_is_mapped(s->hostmem)) { + error_setg(errp, "can't use already busy memdev: %s", + object_get_canonical_path_component(OBJECT(s->hostmem))= ); + return; + } + + s->hostmem_mr =3D host_memory_backend_get_memory(s->hostmem); + + /* HostMemoryBackend size will be multiple of PAGE_SIZE */ + s->storage_size =3D object_property_get_int(OBJECT(s->hostmem), "size"= , errp); + + /* Initialize backend storage and record_count */ + check_erst_backend_storage(s, errp); + + /* BAR 0: Programming registers */ + memory_region_init_io(&s->iomem_mr, OBJECT(pci_dev), &erst_reg_ops, s, + TYPE_ACPI_ERST, ERST_REG_SIZE); + pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->iomem_= mr); + + /* BAR 1: Exchange buffer memory */ + memory_region_init_ram(&s->exchange_mr, OBJECT(pci_dev), + "erst.exchange", + le32_to_cpu(s->header->record_size), errp); + pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, + &s->exchange_mr); + + /* Include the backend storage in the migration stream */ + vmstate_register_ram_global(s->hostmem_mr); + + trace_acpi_erst_realizefn_out(s->storage_size); +} + +static void erst_reset(DeviceState *dev) +{ + ERSTDeviceState *s =3D ACPIERST(dev); + + trace_acpi_erst_reset_in(le32_to_cpu(s->header->record_count)); + s->operation =3D 0; + s->busy_status =3D 0; + s->command_status =3D STATUS_SUCCESS; + s->record_identifier =3D ERST_UNSPECIFIED_RECORD_ID; + s->record_offset =3D 0; + s->next_record_index =3D s->first_record_index; + /* NOTE: first/last_record_index are computed only once */ + trace_acpi_erst_reset_out(le32_to_cpu(s->header->record_count)); +} + +static Property erst_properties[] =3D { + DEFINE_PROP_LINK(ACPI_ERST_MEMDEV_PROP, ERSTDeviceState, hostmem, + TYPE_MEMORY_BACKEND, HostMemoryBackend *), + DEFINE_PROP_UINT32(ACPI_ERST_RECORD_SIZE_PROP, ERSTDeviceState, + default_record_size, ERST_RECORD_SIZE), + DEFINE_PROP_END_OF_LIST(), +}; + +static void erst_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + trace_acpi_erst_class_init_in(); + k->realize =3D erst_realizefn; + k->vendor_id =3D PCI_VENDOR_ID_REDHAT; + k->device_id =3D PCI_DEVICE_ID_REDHAT_ACPI_ERST; + k->revision =3D 0x00; + k->class_id =3D PCI_CLASS_OTHERS; + dc->reset =3D erst_reset; + dc->vmsd =3D &erst_vmstate; + dc->user_creatable =3D true; + dc->hotpluggable =3D false; + device_class_set_props(dc, erst_properties); + dc->desc =3D "ACPI Error Record Serialization Table (ERST) device"; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + trace_acpi_erst_class_init_out(); +} + +static const TypeInfo erst_type_info =3D { + .name =3D TYPE_ACPI_ERST, + .parent =3D TYPE_PCI_DEVICE, + .class_init =3D erst_class_init, + .instance_size =3D sizeof(ERSTDeviceState), + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { } + } +}; + +static void erst_register_types(void) +{ + type_register_static(&erst_type_info); +} + +type_init(erst_register_types) diff --git a/hw/acpi/Kconfig b/hw/acpi/Kconfig index 622b0b50b7..19caebde6c 100644 --- a/hw/acpi/Kconfig +++ b/hw/acpi/Kconfig @@ -10,6 +10,7 @@ config ACPI_X86 select ACPI_HMAT select ACPI_PIIX4 select ACPI_PCIHP + select ACPI_ERST =20 config ACPI_X86_ICH bool @@ -60,3 +61,8 @@ config ACPI_HW_REDUCED select ACPI select ACPI_MEMORY_HOTPLUG select ACPI_NVDIMM + +config ACPI_ERST + bool + default y + depends on ACPI && PCI diff --git a/hw/acpi/meson.build b/hw/acpi/meson.build index adf6347bc4..f5b22983bb 100644 --- a/hw/acpi/meson.build +++ b/hw/acpi/meson.build @@ -22,6 +22,7 @@ acpi_ss.add(when: 'CONFIG_ACPI_PCIHP', if_true: files('pc= ihp.c')) acpi_ss.add(when: 'CONFIG_ACPI_PCIHP', if_false: files('acpi-pci-hotplug-s= tub.c')) acpi_ss.add(when: 'CONFIG_ACPI_VIOT', if_true: files('viot.c')) acpi_ss.add(when: 'CONFIG_ACPI_X86_ICH', if_true: files('ich9.c', 'tco.c')) +acpi_ss.add(when: 'CONFIG_ACPI_ERST', if_true: files('erst.c')) acpi_ss.add(when: 'CONFIG_IPMI', if_true: files('ipmi.c'), if_false: files= ('ipmi-stub.c')) acpi_ss.add(when: 'CONFIG_PC', if_false: files('acpi-x86-stub.c')) acpi_ss.add(when: 'CONFIG_TPM', if_true: files('tpm.c')) diff --git a/hw/acpi/trace-events b/hw/acpi/trace-events index 974d770e8b..2250126a22 100644 --- a/hw/acpi/trace-events +++ b/hw/acpi/trace-events @@ -55,3 +55,18 @@ piix4_gpe_writeb(uint64_t addr, unsigned width, uint64_t= val) "addr: 0x%" PRIx64 # tco.c tco_timer_reload(int ticks, int msec) "ticks=3D%d (%d ms)" tco_timer_expired(int timeouts_no, bool strap, bool no_reboot) "timeouts_n= o=3D%d no_reboot=3D%d/%d" + +# erst.c +acpi_erst_reg_write(uint64_t addr, uint64_t val, unsigned size) "addr: 0x%= 04" PRIx64 " <=3D=3D 0x%016" PRIx64 " (size: %u)" +acpi_erst_reg_read(uint64_t addr, uint64_t val, unsigned size) " addr: 0x%= 04" PRIx64 " =3D=3D> 0x%016" PRIx64 " (size: %u)" +acpi_erst_mem_write(uint64_t addr, uint64_t val, unsigned size) "addr: 0x%= 06" PRIx64 " <=3D=3D 0x%016" PRIx64 " (size: %u)" +acpi_erst_mem_read(uint64_t addr, uint64_t val, unsigned size) " addr: 0x%= 06" PRIx64 " =3D=3D> 0x%016" PRIx64 " (size: %u)" +acpi_erst_pci_bar_0(uint64_t addr) "BAR0: 0x%016" PRIx64 +acpi_erst_pci_bar_1(uint64_t addr) "BAR1: 0x%016" PRIx64 +acpi_erst_realizefn_in(void) +acpi_erst_realizefn_out(unsigned size) "total nvram size %u bytes" +acpi_erst_reset_in(unsigned record_count) "record_count %u" +acpi_erst_reset_out(unsigned record_count) "record_count %u" +acpi_erst_post_load(void *header, unsigned slot_size) "header: 0x%p slot_s= ize %u" +acpi_erst_class_init_in(void) +acpi_erst_class_init_out(void) --=20 MST