From nobody Tue Dec 16 17:04:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643998910378491.0489189343814; Fri, 4 Feb 2022 10:21:50 -0800 (PST) Received: from localhost ([::1]:46578 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nG3DR-0005o7-Sc for importer@patchew.org; Fri, 04 Feb 2022 13:21:49 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39584) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nG2hF-0005kH-23 for qemu-devel@nongnu.org; Fri, 04 Feb 2022 12:48:33 -0500 Received: from [2a00:1450:4864:20::430] (port=44808 helo=mail-wr1-x430.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nG2h7-0003ug-6H for qemu-devel@nongnu.org; Fri, 04 Feb 2022 12:48:32 -0500 Received: by mail-wr1-x430.google.com with SMTP id k18so12702614wrg.11 for ; Fri, 04 Feb 2022 09:48:16 -0800 (PST) Received: from localhost.localdomain ([122.167.157.188]) by smtp.gmail.com with ESMTPSA id f13sm11381876wmq.29.2022.02.04.09.48.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 09:48:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YbfdSx7eK3gPEz2ZUK6pK/RyjIZy0OjB/6uDwADy6Mg=; b=ZNLRCcSoeLYGf85F+53Ffz4t1RJdCovUcSqq4hhfSarZjYBNQfQxyabJf2wqqP6MMu azifPnIKPetj7PiHoaEwN4LZTmE+af0Wv3tee5rxtn+neCUV7XUebq+KnoeZmNCcvxo6 4crkSbKVRESH+0n4sx1C0TCdrV5a0/6AZIsETeNgmNKl1z8zCigVYv/XG/VoknLDPBH/ vq278/q4bAb908XA1RstY2OebSZGyTmlpJIeueBCl1uf3DtOyprmcc4cRoDhbA9M0tQ6 iZQV+ktmwh4J1Usu1oDfbdgrbOPG+oeeOCMArqS9b4OkYvXCv28TaHX3kiK3l7BIKB6B kQtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YbfdSx7eK3gPEz2ZUK6pK/RyjIZy0OjB/6uDwADy6Mg=; b=7pNyfzODZoO1MMRKRrixHTQnnFTS8FIt8nI0yz95IqbbnpCFa7YUZZOwJb2TVXVDjZ tkM6AJP5EnsHUfuTVeLjMZh0nvgYq5b9xNeC/5b2kXXSej8elw+7cYE0ERIsuTAnOay0 Z1Qt6RwgfGhtqe44lGzLdDxfiUXjl3nweU46TbL7TaewxSK0kLrhRrflEvYFk2ct4iG+ /mvT1ROcjYtwyS9sYcsSzedoq7CAAxgHntHn2lLsBfoCw/L6vBVf/fgpDCFFXrCXQl2q w+bmng5ynh2j94tkcr5KPgKwd6lEzXotpVYwPcQOsNxoEfVrl8eODJFzgx/WT55pTtoH az4w== X-Gm-Message-State: AOAM533+y410VNBi9Bt4GNO0Jri/fAlTJuHZVkOx+8w2vMgGY6SW9saZ zD8aZuxzKmolRZvzo3AtiYvM8Q== X-Google-Smtp-Source: ABdhPJzrh97D6PD+xB/deRtDSuo2owMeiPLHE6ATQHkgdvHZWffaX0PFF6LvIQnmf0hTS1ZlEA0/Zg== X-Received: by 2002:a05:6000:16c8:: with SMTP id h8mr3336583wrf.693.1643996895311; Fri, 04 Feb 2022 09:48:15 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Subject: [PATCH v9 12/23] target/riscv: Implement AIA interrupt filtering CSRs Date: Fri, 4 Feb 2022 23:16:48 +0530 Message-Id: <20220204174700.534953-13-anup@brainfault.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220204174700.534953-1-anup@brainfault.org> References: <20220204174700.534953-1-anup@brainfault.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::430 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2a00:1450:4864:20::430; envelope-from=anup@brainfault.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Anup Patel , qemu-devel@nongnu.org, Alistair Francis , Atish Patra , Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1643998922002100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The AIA specificaiton adds interrupt filtering support for M-mode and HS-mode. Using AIA interrupt filtering M-mode and H-mode can take local interrupt 13 or above and selectively inject same local interrupt to lower privilege modes. At the moment, we don't have any local interrupts above 12 so we add dummy implementation (i.e. read zero and ignore write) of AIA interrupt filtering CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/csr.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 552dae1ef8..00f55f47ed 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -158,6 +158,15 @@ static RISCVException any32(CPURISCVState *env, int cs= rno) =20 } =20 +static int aia_any(CPURISCVState *env, int csrno) +{ + if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return any(env, csrno); +} + static int aia_any32(CPURISCVState *env, int csrno) { if (!riscv_feature(env, RISCV_FEATURE_AIA)) { @@ -568,6 +577,12 @@ static RISCVException read_zero(CPURISCVState *env, in= t csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException write_ignore(CPURISCVState *env, int csrno, + target_ulong val) +{ + return RISCV_EXCP_NONE; +} + static RISCVException read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) { @@ -2598,9 +2613,15 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MTVAL] =3D { "mtval", any, read_mtval, write_mtval }, [CSR_MIP] =3D { "mip", any, NULL, NULL, rmw_mip }, =20 + /* Virtual Interrupts for Supervisor Level (AIA) */ + [CSR_MVIEN] =3D { "mvien", aia_any, read_zero, write_ignore }, + [CSR_MVIP] =3D { "mvip", aia_any, read_zero, write_ignore }, + /* Machine-Level High-Half CSRs (AIA) */ [CSR_MIDELEGH] =3D { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, [CSR_MIEH] =3D { "mieh", aia_any32, NULL, NULL, rmw_mieh }, + [CSR_MVIENH] =3D { "mvienh", aia_any32, read_zero, write_ignore }, + [CSR_MVIPH] =3D { "mviph", aia_any32, read_zero, write_ignore }, [CSR_MIPH] =3D { "miph", aia_any32, NULL, NULL, rmw_miph }, =20 /* Supervisor Trap Setup */ @@ -2654,12 +2675,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, writ= e_mtinst }, =20 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) = */ + [CSR_HVIEN] =3D { "hvien", aia_hmode, read_zero, write_ign= ore }, [CSR_HVICTL] =3D { "hvictl", aia_hmode, read_hvictl, write_h= victl }, [CSR_HVIPRIO1] =3D { "hviprio1", aia_hmode, read_hviprio1, wri= te_hviprio1 }, [CSR_HVIPRIO2] =3D { "hviprio2", aia_hmode, read_hviprio2, wri= te_hviprio2 }, =20 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, rmw_hi= delegh }, + [CSR_HVIENH] =3D { "hvienh", aia_hmode32, read_zero, write_i= gnore }, [CSR_HVIPH] =3D { "hviph", aia_hmode32, NULL, NULL, rmw_hv= iph }, [CSR_HVIPRIO1H] =3D { "hviprio1h", aia_hmode32, read_hviprio1h, wr= ite_hviprio1h }, [CSR_HVIPRIO2H] =3D { "hviprio2h", aia_hmode32, read_hviprio2h, wr= ite_hviprio2h }, --=20 2.25.1