From nobody Mon Feb 9 15:11:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164399455175036.82372119262084; Fri, 4 Feb 2022 09:09:11 -0800 (PST) Received: from localhost ([::1]:53844 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nG258-0001Pn-Fb for importer@patchew.org; Fri, 04 Feb 2022 12:09:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53814) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nG1sH-0002xV-Gn for qemu-devel@nongnu.org; Fri, 04 Feb 2022 11:55:53 -0500 Received: from [2a00:1450:4864:20::42b] (port=45620 helo=mail-wr1-x42b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nG1rp-0003BK-Hq for qemu-devel@nongnu.org; Fri, 04 Feb 2022 11:55:39 -0500 Received: by mail-wr1-x42b.google.com with SMTP id m14so12416685wrg.12 for ; Fri, 04 Feb 2022 08:55:10 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12sm2486254wrs.1.2022.02.04.08.55.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 08:55:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ed0qXw0YpiQhxHwBF5JeFrQNFqGWUzVgHXWJkQg7ggw=; b=r1xskzYwJh5kv8t31WC88bJfIdXPdWP1ZzFgIvwTneD793hnHVyb7bUd3M3zXbP3zZ YOYGoyc572RMv02b9HlwoVtXpl9PLwgBKcMGphGdMyefpFcNUWsFjhuTADByaLZ0tvuO 7NgITk7yHRK9q6g1G5A/kVJbS6CmmJZ4KFIfLYEY/8RyGK1+HECbiWybMw+lR3yS6n5c xUowDfKJDFHJDZeb0VMQQDhivyHkBUQg1Uo+vjkDb6MCG5kjedBRvlpC9lDJeK4MhdRa TD4/AdSvr2QUFhea962SPTNZHawPTtPNTIobc0G4mUYHgvktgTQ3FvXVuG6bJ+f5aB74 TP8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ed0qXw0YpiQhxHwBF5JeFrQNFqGWUzVgHXWJkQg7ggw=; b=RFWz9zCQ9NVbXqP/AtvHTDGqYRI6HNQDe4r4hLPdSy4KfK2L45uVFWR2KXMkO3Qz+O 62+RCO2OUtqU1lLeF6AAxaN2UEaMwm2N5Q4s04ogLu3/PZtISi+qub8oOvSaUaFM5C9M JmMwclDneDY05sZm05wP/tWigyjfROKYX57TAcSOiCdbEkrrOoRNF6Sj+kWSaHHvVUre ctqPWr7/rhIaMXxapMVYVsOrDUgaDxxqdy/TPwf1JB6HBfrGFjgceRnhx1P7sP4uIvh3 Xwofu2ctH8qHcrcfj//AtC9ZIe9ExH+XjyI8/Dn/uU4mvnSF5TK+fTF7qveGDXQ/2YKi JJqg== X-Gm-Message-State: AOAM5332uOViFj1bEqwZk9xRFm9bA+E09MvjeVxyZGwDiPmN8YH3Gagk xIFoyrCqmvoMOny7FE0ej+toIQ== X-Google-Smtp-Source: ABdhPJyE6da+r8+WoIPF8UpBlo4tGAEKhvfGGQIgJWNmQHfctdWsyJDJfIb1JeegRzD2VrjHWJDh9g== X-Received: by 2002:adf:e48c:: with SMTP id i12mr3091639wrm.259.1643993709217; Fri, 04 Feb 2022 08:55:09 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/6] target/arm: Move '-cpu host' code to cpu64.c Date: Fri, 4 Feb 2022 16:55:01 +0000 Message-Id: <20220204165506.2846058-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220204165506.2846058-1-peter.maydell@linaro.org> References: <20220204165506.2846058-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , Alexander Graf Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1643994552623100001 Content-Type: text/plain; charset="utf-8" Now that KVM has dropped AArch32 host support, the 'host' CPU type is always AArch64, and we can move it to cpu64.c. This move will allow us to share code between it and '-cpu max', which should behave the same as '-cpu host' when using KVM or HVF. Signed-off-by: Peter Maydell Reviewed-by: Alexander Graf Reviewed-by: Andrew Jones Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu.c | 30 ------------------------------ target/arm/cpu64.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index cdbc4cdd012..d655daa949c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -39,7 +39,6 @@ #include "sysemu/tcg.h" #include "sysemu/hw_accel.h" #include "kvm_arm.h" -#include "hvf_arm.h" #include "disas/capstone.h" #include "fpu/softfloat.h" =20 @@ -2075,31 +2074,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void= *data) #endif /* CONFIG_TCG */ } =20 -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) -static void arm_host_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - -#ifdef CONFIG_KVM - kvm_arm_set_cpu_features_from_host(cpu); - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - aarch64_add_sve_properties(obj); - aarch64_add_pauth_properties(obj); - } -#else - hvf_arm_set_cpu_features_from_host(cpu); -#endif - arm_cpu_post_init(obj); -} - -static const TypeInfo host_arm_cpu_type_info =3D { - .name =3D TYPE_ARM_HOST_CPU, - .parent =3D TYPE_AARCH64_CPU, - .instance_init =3D arm_host_initfn, -}; - -#endif - static void arm_cpu_instance_init(Object *obj) { ARMCPUClass *acc =3D ARM_CPU_GET_CLASS(obj); @@ -2147,10 +2121,6 @@ static const TypeInfo arm_cpu_type_info =3D { static void arm_cpu_register_types(void) { type_register_static(&arm_cpu_type_info); - -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) - type_register_static(&host_arm_cpu_type_info); -#endif } =20 type_init(arm_cpu_register_types) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8786be7783e..052666b819e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -30,6 +30,7 @@ #endif #include "sysemu/kvm.h" #include "kvm_arm.h" +#include "hvf_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" =20 @@ -681,6 +682,31 @@ void aarch64_add_pauth_properties(Object *obj) } } =20 +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) +static void arm_host_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + +#ifdef CONFIG_KVM + kvm_arm_set_cpu_features_from_host(cpu); + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + aarch64_add_sve_properties(obj); + aarch64_add_pauth_properties(obj); + } +#else + hvf_arm_set_cpu_features_from_host(cpu); +#endif + arm_cpu_post_init(obj); +} + +static const TypeInfo host_arm_cpu_type_info =3D { + .name =3D TYPE_ARM_HOST_CPU, + .parent =3D TYPE_AARCH64_CPU, + .instance_init =3D arm_host_initfn, +}; + +#endif + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); * otherwise, a CPU with as many features enabled as our emulation support= s. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -1023,6 +1049,10 @@ static void aarch64_cpu_register_types(void) for (i =3D 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { aarch64_cpu_register(&aarch64_cpus[i]); } + +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) + type_register_static(&host_arm_cpu_type_info); +#endif } =20 type_init(aarch64_cpu_register_types) --=20 2.25.1 From nobody Mon Feb 9 15:11:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643994152367146.74907273434485; Fri, 4 Feb 2022 09:02:32 -0800 (PST) Received: from localhost ([::1]:39056 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nG1yh-0008Ef-2e for importer@patchew.org; Fri, 04 Feb 2022 12:02:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53836) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nG1sH-0002y7-LO for qemu-devel@nongnu.org; Fri, 04 Feb 2022 11:55:53 -0500 Received: from [2a00:1450:4864:20::434] (port=39608 helo=mail-wr1-x434.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nG1rp-0003BS-Ka for qemu-devel@nongnu.org; Fri, 04 Feb 2022 11:55:39 -0500 Received: by mail-wr1-x434.google.com with SMTP id r17so3414088wrr.6 for ; Fri, 04 Feb 2022 08:55:10 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12sm2486254wrs.1.2022.02.04.08.55.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 08:55:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tjcvPV/juuMIi4sRDbbU/TdIgPLoSlWdDbYJe45BCYc=; b=KxLxce1+gFmcvFNrRLL2/maGEvJQmt0Hf0OlZuvPiuK1w5Ab3SxyurA45jGZUA/JZI Z4EaOa2pN+i5gYFVJloKQwcbED0T94XcGl2AS0YEvm74S4pnJWtX4JSXYN5TUmLe3oY4 M/JVQ2urRY4NTZ04/5XnCniGrrcvh94IIAJtwLms5cCAiOiNdkbVx3rLbgWVJp6ox82X pZLV/LIuNnmvAhzVRWjTw7LLV+SduwyRJC4l63iobRo0PUYiWv8XvxGPTEl8AL8lHm4j QuuhLw8UYqke81nz9cJJ2SNbPoTq8206bV3LwI+28b4/u0OGDA82ZlD/3D1/BdKk+oeW eD6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tjcvPV/juuMIi4sRDbbU/TdIgPLoSlWdDbYJe45BCYc=; b=4H9PuavoPNEiDh68ArBmmX7bqbFUTRf+U8b/Od0y26L8/KfHebhWrwNEabigOe9sDP +fmFh5H1fwGQ5JO1B1+xwrbRmdWtN40+OZOY95FfdYCRHGpmalMrlAOS+sIal1H1l99f uzvJgyaitWfPyR1JoJ5Pq9EEt3qcNtimHcRs7bCfuz9mFMf7oa98oIglTZg0ZrvO+Jfj O1w02brHxXI8MxzbCZiykEvmJ45m6VkadGPUwnjgHge+B9wKONl7fH14A8qP0ayZuL3x xc5uwuMWmziwxdxiXgjygD/r0t+cuz6bDmfi9oNi3RMEkhuHmFznsWmS7rkSwyNjfsbH RejA== X-Gm-Message-State: AOAM5315OWYG8jklujlgi+CpDvZ3E/z8LdQFrTljEgH/QKckJauU3RRK 26+zklgvLq9MbosRKf0RYn247w== X-Google-Smtp-Source: ABdhPJy62nx2DRiSMhxqO4dfgyiqdLf3MPL/jIOKzEYnnGYDWRXlLmYatWUbQcTY8qVQKvUPgSW3jQ== X-Received: by 2002:a05:6000:1a46:: with SMTP id t6mr2359874wry.49.1643993709904; Fri, 04 Feb 2022 08:55:09 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/6] target/arm: Use aarch64_cpu_register() for 'host' CPU type Date: Fri, 4 Feb 2022 16:55:02 +0000 Message-Id: <20220204165506.2846058-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220204165506.2846058-1-peter.maydell@linaro.org> References: <20220204165506.2846058-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::434 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , Alexander Graf Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1643994154153100001 Content-Type: text/plain; charset="utf-8" Use the aarch64_cpu_register() machinery to register the 'host' CPU type. This doesn't gain us anything functionally, but it does mean that the code for initializing it looks more like that for the other CPU types, in that its initfn then doesn't need to call arm_cpu_post_init() (because aarch64_cpu_instance_init() does that for it). Signed-off-by: Peter Maydell Reviewed-by: Alexander Graf Reviewed-by: Andrew Jones Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 052666b819e..590ac562714 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -683,7 +683,7 @@ void aarch64_add_pauth_properties(Object *obj) } =20 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) -static void arm_host_initfn(Object *obj) +static void aarch64_host_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); =20 @@ -696,15 +696,7 @@ static void arm_host_initfn(Object *obj) #else hvf_arm_set_cpu_features_from_host(cpu); #endif - arm_cpu_post_init(obj); } - -static const TypeInfo host_arm_cpu_type_info =3D { - .name =3D TYPE_ARM_HOST_CPU, - .parent =3D TYPE_AARCH64_CPU, - .instance_init =3D arm_host_initfn, -}; - #endif =20 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); @@ -943,6 +935,9 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) + { .name =3D "host", .initfn =3D aarch64_host_initfn }, +#endif }; =20 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) @@ -1049,10 +1044,6 @@ static void aarch64_cpu_register_types(void) for (i =3D 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { aarch64_cpu_register(&aarch64_cpus[i]); } - -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) - type_register_static(&host_arm_cpu_type_info); -#endif } =20 type_init(aarch64_cpu_register_types) --=20 2.25.1 From nobody Mon Feb 9 15:11:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643994785351981.0935904775021; Fri, 4 Feb 2022 09:13:05 -0800 (PST) Received: from localhost ([::1]:58184 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nG28t-0004Qe-Ve for importer@patchew.org; Fri, 04 Feb 2022 12:13:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53834) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nG1sH-0002y5-Lt for qemu-devel@nongnu.org; Fri, 04 Feb 2022 11:55:53 -0500 Received: from [2a00:1450:4864:20::431] (port=45626 helo=mail-wr1-x431.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nG1rr-0003Cg-Hk for qemu-devel@nongnu.org; Fri, 04 Feb 2022 11:55:39 -0500 Received: by mail-wr1-x431.google.com with SMTP id m14so12416793wrg.12 for ; Fri, 04 Feb 2022 08:55:11 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12sm2486254wrs.1.2022.02.04.08.55.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 08:55:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q3lEtc5flDNZqu3pjs5Zh2F0vIL0PpXE6vU56vUELAY=; b=qMiNaxDCdLYY+0bp2GFATzDbwVh9oh4no7rnM4RUGCQf9bqIOrLdiRabeI7iSA6RUY l21pkwzUHwxks9whV8LWWGDO/mcW94f7WkW+cG4ny82IFsweX6il0f3ZiuJfAQzgUQ25 rSyK1QNlCgao38UCh55GmWx3KuSjJwjD48EWkm8CBirFdgnIbglwbe1PVLjLM8gj7BjN L80gq5T8/4chIVC4iG7wYcMvgZGOaokWygDxKeOrBhWHEPVObG9to7eqNuVW+FrVkuWr oPy63lppSGJEbzQHJUG0gynqExMBsU0PpmtLS+vNFYA+RK5DN27xKyrIA5uk/OTo/2BX mCUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q3lEtc5flDNZqu3pjs5Zh2F0vIL0PpXE6vU56vUELAY=; b=Pqg2GmfaTEJI0gmKME388shhda8fBK/4ECeUjPABk+RzPHFPxsqjc4SOqX8dMYD486 KRvRI+SOCMSPOYXLjt+zQPz0AhWHeePeHKegCR+naXPV7+qdohqkXlBOP7jSNvH2kNg0 kV29BPmKrIuWf8tTsk9P/ObgGWyn2cDKU3f9P77Iz4PnrNwlGwmGghRKIQ/PSfmtDt4B LbXJlk3wsLCJU1gjaDkvZh4dznjPAXw63gOpOPaprDq7oLHigV+PFUhUcYmE/p7j1KYg HRlMRVC9RRhbtwJBZ48hR6hJf+DQomOqPoLtlGrtANQZAlpzZTH4+7uWL1XbaU+v+cy6 0aXw== X-Gm-Message-State: AOAM5337Z5cjaUr7JbxdhkGYfFRQwSpd9QaZNr5w5Qux4DMP/56sKS6B jgdeLNYBZz/uS/9dYnI4onJ/N8vluEBbKQ== X-Google-Smtp-Source: ABdhPJyQstj8oRcDwEAVwouyYWZJxElRo5/9RBuWGS5PJHlDTUXbuzOF3Psb7TehPAaE0zmXrvg52w== X-Received: by 2002:a05:6000:184f:: with SMTP id c15mr3204888wri.218.1643993710666; Fri, 04 Feb 2022 08:55:10 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/6] target/arm: Make KVM -cpu max exactly like -cpu host Date: Fri, 4 Feb 2022 16:55:03 +0000 Message-Id: <20220204165506.2846058-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220204165506.2846058-1-peter.maydell@linaro.org> References: <20220204165506.2846058-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::431 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , Alexander Graf Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1643994785840100001 Content-Type: text/plain; charset="utf-8" Currently for KVM the intention is that '-cpu max' and '-cpu host' are the same thing, but because we did this with two separate pieces of code they have got a little bit out of sync. Specifically, 'max' has a 'sve-max-vq' property, and 'host' does not. Bring the two together by having the initfn for 'max' actually call the initfn for 'host'. This will result in 'max' no longer exposing the 'sve-max-vq' property when using KVM. Signed-off-by: Peter Maydell Reviewed-by: Alexander Graf Reviewed-by: Andrew Jones Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 590ac562714..ae2e431247f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -682,22 +682,22 @@ void aarch64_add_pauth_properties(Object *obj) } } =20 -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) static void aarch64_host_initfn(Object *obj) { +#if defined(CONFIG_KVM) ARMCPU *cpu =3D ARM_CPU(obj); - -#ifdef CONFIG_KVM kvm_arm_set_cpu_features_from_host(cpu); if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { aarch64_add_sve_properties(obj); aarch64_add_pauth_properties(obj); } -#else +#elif defined(CONFIG_HVF) + ARMCPU *cpu =3D ARM_CPU(obj); hvf_arm_set_cpu_features_from_host(cpu); +#else + g_assert_not_reached(); #endif } -#endif =20 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); * otherwise, a CPU with as many features enabled as our emulation support= s. @@ -709,7 +709,9 @@ static void aarch64_max_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); =20 if (kvm_enabled()) { - kvm_arm_set_cpu_features_from_host(cpu); + /* With KVM, '-cpu max' is identical to '-cpu host' */ + aarch64_host_initfn(obj); + return; } else { uint64_t t; uint32_t u; --=20 2.25.1 From nobody Mon Feb 9 15:11:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643994000922209.85183231361634; Fri, 4 Feb 2022 09:00:00 -0800 (PST) Received: from localhost ([::1]:36570 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nG1wF-0006Rv-Qf for importer@patchew.org; Fri, 04 Feb 2022 11:59:59 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nG1sH-0002xK-Fw for qemu-devel@nongnu.org; Fri, 04 Feb 2022 11:55:53 -0500 Received: from [2a00:1450:4864:20::330] (port=52200 helo=mail-wm1-x330.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nG1rt-0003D4-8e for qemu-devel@nongnu.org; Fri, 04 Feb 2022 11:55:40 -0500 Received: by mail-wm1-x330.google.com with SMTP id i204so726720wma.1 for ; Fri, 04 Feb 2022 08:55:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12sm2486254wrs.1.2022.02.04.08.55.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 08:55:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Vu7uIUvA2v4vjGlr2e1UfSedBQQkSc8plW2znNSP+3I=; b=l7SaaV3IYMPx+SGK2gL5WfSRb9468UWFRGa/9T69+zlWTeZU3MQJqP5JlyAPQhz/7j hj+qfXCy0YunecIBZOIx5lTmVrKncTYvd2fulxEvel5sU9tvDCzSAEFYVYRIrO1QT9F4 y4CAPCperPQiZjGrQ9cpBR5z5CyCMBwTsnBvQ4HmKAlMsgzl2udW9excNUficBF5kw84 GPEX4+eVR4KkPAs4yLsn1HXs0KUPajH/HaFDEjptpOMohWIp3O6G5IHAzsy8k9d08ZZ5 VGlJGaU7GrXG1PXXmj3SufQjDWmWsu89TBgaxmA5Dc4Ix3jfBgUlXNFx1kKaHJanJZ+D R3mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Vu7uIUvA2v4vjGlr2e1UfSedBQQkSc8plW2znNSP+3I=; b=3R5SGsEa+2L/cRBu+BKPOhr1/9zD8d2S3sI2Mcp/bssK7R3TgJrnQa4FUaCxm5T31w ECwIZjWkn6IQt1sfTROgd0QIIzUFFX0JqmhcwFNUJoFyBbRo3ikevCMRYzdwlqzGU2Si pjIRNS6OE2oIcm0LcLSxnrjBlrv/ywETdeaOmq0npbPJVSON7JyHyG+Vo8urwhEXZRl2 CMjz2o9skvnU/QyVKLJPOY5JJT/9XEXZcqWd5CanhMTrnhmZXz31zv38rToBWfSFiGZ+ SEe2SHHpHbNtwh+dPQ+u5hHYauLrFfbk/mzhwFN/DOiNasgnumAyjK93Vpi8ZPUUbLGr UEFA== X-Gm-Message-State: AOAM530yjVttw5S5kdXAS/BHkW8E0PxN9MxAOCkI3mdH2G1eXjnn8Iwj BAetDnkoFC/XPcBPm9Pv0yoFpA== X-Google-Smtp-Source: ABdhPJwMBYZibRU6FktX4IwrFKiezbR4jlDpD8DP1JJ80qNvkP9d7hgBWA+jm8KdCvAu5rqgOfF2ig== X-Received: by 2002:a05:600c:3b25:: with SMTP id m37mr2944113wms.40.1643993711621; Fri, 04 Feb 2022 08:55:11 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 4/6] target/arm: Unindent unnecessary else-clause Date: Fri, 4 Feb 2022 16:55:04 +0000 Message-Id: <20220204165506.2846058-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220204165506.2846058-1-peter.maydell@linaro.org> References: <20220204165506.2846058-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::330 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , Alexander Graf Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1643994002055100001 Content-Type: text/plain; charset="utf-8" Now that the if() branch of the condition in aarch64_max_initfn() returns early, we don't need to keep the rest of the code in the function inside an else block. Remove the else, unindenting that code. Signed-off-by: Peter Maydell Reviewed-by: Alexander Graf Reviewed-by: Andrew Jones Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 288 +++++++++++++++++++++++---------------------- 1 file changed, 145 insertions(+), 143 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index ae2e431247f..bc25a2567bf 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -707,176 +707,178 @@ static void aarch64_host_initfn(Object *obj) static void aarch64_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + uint64_t t; + uint32_t u; =20 if (kvm_enabled()) { /* With KVM, '-cpu max' is identical to '-cpu host' */ aarch64_host_initfn(obj); return; - } else { - uint64_t t; - uint32_t u; - aarch64_a57_initfn(obj); + } =20 - /* - * Reset MIDR so the guest doesn't mistake our 'max' CPU type for = a real - * one and try to apply errata workarounds or use impdef features = we - * don't provide. - * An IMPLEMENTER field of 0 means "reserved for software use"; - * ARCHITECTURE must be 0xf indicating "v7 or later, check ID regi= sters - * to see which features are present"; - * the VARIANT, PARTNUM and REVISION fields are all implementation - * defined and we choose to define PARTNUM just in case guest - * code needs to distinguish this QEMU CPU from other software - * implementations, though this shouldn't be needed. - */ - t =3D FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); - t =3D FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); - t =3D FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); - t =3D FIELD_DP64(t, MIDR_EL1, VARIANT, 0); - t =3D FIELD_DP64(t, MIDR_EL1, REVISION, 0); - cpu->midr =3D t; + /* '-cpu max' for TCG: we currently do this as "A57 with extra things"= */ =20 - t =3D cpu->isar.id_aa64isar0; - t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); - t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); - cpu->isar.id_aa64isar0 =3D t; + aarch64_a57_initfn(obj); =20 - t =3D cpu->isar.id_aa64isar1; - t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); - t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); - cpu->isar.id_aa64isar1 =3D t; + /* + * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a re= al + * one and try to apply errata workarounds or use impdef features we + * don't provide. + * An IMPLEMENTER field of 0 means "reserved for software use"; + * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers + * to see which features are present"; + * the VARIANT, PARTNUM and REVISION fields are all implementation + * defined and we choose to define PARTNUM just in case guest + * code needs to distinguish this QEMU CPU from other software + * implementations, though this shouldn't be needed. + */ + t =3D FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); + t =3D FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); + t =3D FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); + t =3D FIELD_DP64(t, MIDR_EL1, VARIANT, 0); + t =3D FIELD_DP64(t, MIDR_EL1, REVISION, 0); + cpu->midr =3D t; =20 - t =3D cpu->isar.id_aa64pfr0; - t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); - cpu->isar.id_aa64pfr0 =3D t; + t =3D cpu->isar.id_aa64isar0; + t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); + t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); + cpu->isar.id_aa64isar0 =3D t; =20 - t =3D cpu->isar.id_aa64pfr1; - t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); - t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); - /* - * Begin with full support for MTE. This will be downgraded to MTE= =3D0 - * during realize if the board provides no tag memory, much like - * we do for EL2 with the virtualization=3Don property. - */ - t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); - cpu->isar.id_aa64pfr1 =3D t; + t =3D cpu->isar.id_aa64isar1; + t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); + t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); + cpu->isar.id_aa64isar1 =3D t; =20 - t =3D cpu->isar.id_aa64mmfr0; - t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits= */ - cpu->isar.id_aa64mmfr0 =3D t; + t =3D cpu->isar.id_aa64pfr0; + t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); + cpu->isar.id_aa64pfr0 =3D t; =20 - t =3D cpu->isar.id_aa64mmfr1; - t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ - cpu->isar.id_aa64mmfr1 =3D t; + t =3D cpu->isar.id_aa64pfr1; + t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); + t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); + /* + * Begin with full support for MTE. This will be downgraded to MTE=3D0 + * during realize if the board provides no tag memory, much like + * we do for EL2 with the virtualization=3Don property. + */ + t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); + cpu->isar.id_aa64pfr1 =3D t; =20 - t =3D cpu->isar.id_aa64mmfr2; - t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ - cpu->isar.id_aa64mmfr2 =3D t; + t =3D cpu->isar.id_aa64mmfr0; + t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */ + cpu->isar.id_aa64mmfr0 =3D t; =20 - t =3D cpu->isar.id_aa64zfr0; - t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); - cpu->isar.id_aa64zfr0 =3D t; + t =3D cpu->isar.id_aa64mmfr1; + t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); + t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); + t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ + cpu->isar.id_aa64mmfr1 =3D t; =20 - /* Replicate the same data to the 32-bit id registers. */ - u =3D cpu->isar.id_isar5; - u =3D FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ - u =3D FIELD_DP32(u, ID_ISAR5, SHA1, 1); - u =3D FIELD_DP32(u, ID_ISAR5, SHA2, 1); - u =3D FIELD_DP32(u, ID_ISAR5, CRC32, 1); - u =3D FIELD_DP32(u, ID_ISAR5, RDM, 1); - u =3D FIELD_DP32(u, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D u; + t =3D cpu->isar.id_aa64mmfr2; + t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); + t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ + cpu->isar.id_aa64mmfr2 =3D t; =20 - u =3D cpu->isar.id_isar6; - u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 1); - u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); - u =3D FIELD_DP32(u, ID_ISAR6, FHM, 1); - u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); - u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); - u =3D FIELD_DP32(u, ID_ISAR6, BF16, 1); - u =3D FIELD_DP32(u, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D u; + t =3D cpu->isar.id_aa64zfr0; + t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); + t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); + t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); + t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); + t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); + t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); + t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); + t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); + cpu->isar.id_aa64zfr0 =3D t; =20 - u =3D cpu->isar.id_pfr0; - u =3D FIELD_DP32(u, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D u; + /* Replicate the same data to the 32-bit id registers. */ + u =3D cpu->isar.id_isar5; + u =3D FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ + u =3D FIELD_DP32(u, ID_ISAR5, SHA1, 1); + u =3D FIELD_DP32(u, ID_ISAR5, SHA2, 1); + u =3D FIELD_DP32(u, ID_ISAR5, CRC32, 1); + u =3D FIELD_DP32(u, ID_ISAR5, RDM, 1); + u =3D FIELD_DP32(u, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D u; =20 - u =3D cpu->isar.id_pfr2; - u =3D FIELD_DP32(u, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D u; + u =3D cpu->isar.id_isar6; + u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 1); + u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); + u =3D FIELD_DP32(u, ID_ISAR6, FHM, 1); + u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); + u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); + u =3D FIELD_DP32(u, ID_ISAR6, BF16, 1); + u =3D FIELD_DP32(u, ID_ISAR6, I8MM, 1); + cpu->isar.id_isar6 =3D u; =20 - u =3D cpu->isar.id_mmfr3; - u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D u; + u =3D cpu->isar.id_pfr0; + u =3D FIELD_DP32(u, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D u; =20 - u =3D cpu->isar.id_mmfr4; - u =3D FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ - u =3D FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - u =3D FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ - u =3D FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D u; + u =3D cpu->isar.id_pfr2; + u =3D FIELD_DP32(u, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D u; =20 - t =3D cpu->isar.id_aa64dfr0; - t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ - cpu->isar.id_aa64dfr0 =3D t; + u =3D cpu->isar.id_mmfr3; + u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D u; =20 - u =3D cpu->isar.id_dfr0; - u =3D FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ - cpu->isar.id_dfr0 =3D u; + u =3D cpu->isar.id_mmfr4; + u =3D FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ + u =3D FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + u =3D FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ + u =3D FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D u; =20 - u =3D cpu->isar.mvfr1; - u =3D FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ - u =3D FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D u; + t =3D cpu->isar.id_aa64dfr0; + t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ + cpu->isar.id_aa64dfr0 =3D t; + + u =3D cpu->isar.id_dfr0; + u =3D FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 =3D u; + + u =3D cpu->isar.mvfr1; + u =3D FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ + u =3D FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D u; =20 #ifdef CONFIG_USER_ONLY - /* For usermode -cpu max we can use a larger and more efficient DCZ - * blocksize since we don't have to follow what the hardware does. - */ - cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT i= cache */ - cpu->dcz_blocksize =3D 7; /* 512 bytes */ + /* For usermode -cpu max we can use a larger and more efficient DCZ + * blocksize since we don't have to follow what the hardware does. + */ + cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ + cpu->dcz_blocksize =3D 7; /* 512 bytes */ #endif =20 - bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ); - } + bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ); =20 aarch64_add_pauth_properties(obj); aarch64_add_sve_properties(obj); --=20 2.25.1 From nobody Mon Feb 9 15:11:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643994400654505.390380306065; Fri, 4 Feb 2022 09:06:40 -0800 (PST) Received: from localhost ([::1]:45436 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nG22h-00047X-CM for importer@patchew.org; Fri, 04 Feb 2022 12:06:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nG1sH-0002xR-FS for qemu-devel@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12sm2486254wrs.1.2022.02.04.08.55.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 08:55:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GEq+WVisRup7DDWYvHMkPo67hjMY0sbprx528SyyNTQ=; b=PQW6Y+Khj/Qrk/sc1YwfoCROKa8j6BW6/7xmrhbN8wqRmSbSkVsTSnrD5ufGRVtcfa ZfVORtiCLtcxI1/yTmDSQ/ZKSOZoyPkXHnI/9+TqSj2vSqMyzNGpeIWa9K5huorHG0PZ rt8ET0hlnowomjeeY545wWe4f/1QtW0axvsSio2RdayhkzLMEYxp+CQjv/zbQqq2Xcpo kixIi1HEQyEiRp3bVI3INtT7pnmBICcReryzz+X0FmVO86appphrGR2lqvRHD5iY9KCg BELIJg/GUM0Kyz1V1xOFkWLvs2yVcK9lerlDcx1EOWi/tQ66iREdivNdbDQgUHMQbq7Z VNQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GEq+WVisRup7DDWYvHMkPo67hjMY0sbprx528SyyNTQ=; b=OT8sxgAoClCenuLEsxBGfOO48lzf90PIlKbwhzj2ulZ9PC7ebDE+Ryybarcjcw2sCI qP9yX/MYWHqOJgq9kXvwsMc6AFXkk4X/N1ZsIDrXOUSAzLKXSHTSQp5mpimrNlMk9CS7 xC0dlqbTDpSaHNMqIjv+hBP7xGvzmtNP/8XWPY83yEcRr5Y6E58eCveyaNbW2Ma/jNKa whdndQ7SNcfmVjOCAqpVJ4H7fa8tWLYgsnGGCdoq4HhvpNr5L8i+9dXeD6V0COvLCf0s j0cEzTVQwxnPfQ5QdzY6V9zoxnB2opreqzBLtI1Khq46qyUXLlz8flRMXmeNwNeR1F5i lBDw== X-Gm-Message-State: AOAM533W47jJ4PBMqPX6F8iJsAFKYzbxrpXmQ5aR+W+ZHBX2KOCYpWxS UruYruYR28irFEW4BgzvipBlaQ== X-Google-Smtp-Source: ABdhPJwpkb3wvZs40lgkIxZZlTznWlbfSjhuU1IRbP55uzE0LHu3C6zM9/TwW7jaHdDGmuyTA9nqoQ== X-Received: by 2002:a05:600c:3ac5:: with SMTP id d5mr2997821wms.101.1643993712352; Fri, 04 Feb 2022 08:55:12 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 5/6] target/arm: Fix '-cpu max' for HVF Date: Fri, 4 Feb 2022 16:55:05 +0000 Message-Id: <20220204165506.2846058-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220204165506.2846058-1-peter.maydell@linaro.org> References: <20220204165506.2846058-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32d (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , Alexander Graf Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1643994402316100001 Content-Type: text/plain; charset="utf-8" Currently when using hvf we mishandle '-cpu max': we fall through to the TCG version of its initfn, which then sets a lot of feature bits that the real host CPU doesn't have. The hvf accelerator code then exposes these bogus ID register values to the guest because it doesn't check that the host really has the features. Make '-cpu host' be like '-cpu max' for hvf, as we do with kvm. Signed-off-by: Peter Maydell Reviewed-by: Alexander Graf Reviewed-by: Andrew Jones Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index bc25a2567bf..fd611c97116 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -29,6 +29,7 @@ #include "hw/loader.h" #endif #include "sysemu/kvm.h" +#include "sysemu/hvf.h" #include "kvm_arm.h" #include "hvf_arm.h" #include "qapi/visitor.h" @@ -710,8 +711,8 @@ static void aarch64_max_initfn(Object *obj) uint64_t t; uint32_t u; =20 - if (kvm_enabled()) { - /* With KVM, '-cpu max' is identical to '-cpu host' */ + if (kvm_enabled() || hvf_enabled()) { + /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ aarch64_host_initfn(obj); return; } --=20 2.25.1 From nobody Mon Feb 9 15:11:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643994379805788.1921458923681; Fri, 4 Feb 2022 09:06:19 -0800 (PST) Received: from localhost ([::1]:45180 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nG22L-0003wV-PO for importer@patchew.org; Fri, 04 Feb 2022 12:06:18 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nG1sH-0002xx-Lh for qemu-devel@nongnu.org; Fri, 04 Feb 2022 11:55:53 -0500 Received: from [2a00:1450:4864:20::32e] (port=38611 helo=mail-wm1-x32e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nG1rr-0003DI-Ht for qemu-devel@nongnu.org; Fri, 04 Feb 2022 11:55:37 -0500 Received: by mail-wm1-x32e.google.com with SMTP id o30-20020a05600c511e00b0034f4c3186f4so9821835wms.3 for ; Fri, 04 Feb 2022 08:55:13 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12sm2486254wrs.1.2022.02.04.08.55.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 08:55:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=umQ/WbOJUobh23pwZIc3MfhXaZpQDP+TCKjJpFme+9w=; b=UgQd5pLlr/hCiydV0vb3UUenZR52JfqSNWK1Qrqd6/yOhqLigr73Peweyo/YQ/MBt5 cuOZZH5U1Xn4USdnYMeld31IFI8I4LfWcbttMSwq5NgVAZy/EeH0yJkF6X4XiH/TxXBW K9alm0W3R1//WYTtGvwqeZDfGbiHRQCmfvqxxKFwfCD7OJShKS2BMhBufZbe8BugLCQz XSX0D9LDCXPUUrtmFdtLB32wurFYdme9JEbTh0A44oSJrHCRUrHGSLemkZxeT0gqFXJV C0kBUqSKiesz7709EIIiVb1WZpMpWwTY7LJAs19tRmQ1Q2E27X9L1aWXxrDLEiSJNy4A 8Qbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=umQ/WbOJUobh23pwZIc3MfhXaZpQDP+TCKjJpFme+9w=; b=jrqCH6YGuJt349takbe+zjC0HkN5Hsaa2HhhvGFbYknvPfE6VQm6+m1XPIM6N5DR8T 1LmT15qqeIq0ZcgxkzK8riOeMrINJc5t9kUgEU7bsbgOVc3dnoQ9n9x3syMuy7a9wuDO BLPOrvQ44RLqy1PF+4kwSM5gNwdQLHFON3h4NY+DQaM/dDhSeBxwyYb+R94qfk8L1Fpb Pwhc0HJmagZ54hFnrBbjEa8IvV41nY+EwgpqdnqD9UiTLxi3zaMyVl8qB+V9uuEkvRkf Ivk01yTuhQ+GZqOJbFY6NKMJHx/fvfLZ30h4jlFa/Pe2STLsoc/GApuHPEESiBPAo7zN Y8vA== X-Gm-Message-State: AOAM530jdcdbbhApZGvxOFd+9QmgGG++aZMtEqDHXin8Lugs+cPeJz4l d+1M1KjM/3FxNCinyv2UotTJzU7k1q82eA== X-Google-Smtp-Source: ABdhPJxAaxGZCDfPSBSlZn/j3XD2TuuYoaFu3fgIaTHv0VO4ysed1IXMvNS0b6I4Z1WEuSltd32Vmg== X-Received: by 2002:a1c:4e09:: with SMTP id g9mr2972347wmh.188.1643993713025; Fri, 04 Feb 2022 08:55:13 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 6/6] target/arm: Support PAuth extension for hvf Date: Fri, 4 Feb 2022 16:55:06 +0000 Message-Id: <20220204165506.2846058-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220204165506.2846058-1-peter.maydell@linaro.org> References: <20220204165506.2846058-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32e (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , Alexander Graf Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1643994382203100001 Content-Type: text/plain; charset="utf-8" Currently we don't allow guests under hvf to use the PAuth extension, because we didn't have any special code to handle that, and therefore in arm_cpu_pauth_finalize() we will sanitize the ID_AA64ISAR1 value the guest sees to clear the PAuth related fields. Add support for this in the same way that KVM does it, by defaulting to "PAuth enabled" if the host CPU has it and allowing the user to disable it via '-cpu pauth=3Dno' on the command line. Signed-off-by: Peter Maydell Reviewed-by: Alexander Graf Reviewed-by: Andrew Jones Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index fd611c97116..5be5ade6c9d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -633,9 +633,10 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) uint64_t t; =20 /* Exit early if PAuth is enabled, and fall through to disable it */ - if (kvm_enabled() && cpu->prop_pauth) { + if ((kvm_enabled() || hvf_enabled()) && cpu->prop_pauth) { if (!cpu_isar_feature(aa64_pauth, cpu)) { - error_setg(errp, "'pauth' feature not supported by KVM on this= host"); + error_setg(errp, "'pauth' feature not supported by %s on this = host", + kvm_enabled() ? "KVM" : "hvf"); } =20 return; @@ -672,10 +673,14 @@ void aarch64_add_pauth_properties(Object *obj) =20 /* Default to PAUTH on, with the architected algorithm on TCG. */ qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); - if (kvm_enabled()) { + if (kvm_enabled() || hvf_enabled()) { /* * Mirror PAuth support from the probed sysregs back into the - * property for KVM. Is it just a bit backward? Yes it is! + * property for KVM or hvf. Is it just a bit backward? Yes it is! + * Note that prop_pauth is true whether the host CPU supports the + * architected QARMA5 algorithm or the IMPDEF one. We don't + * provide the separate pauth-impdef property for KVM or hvf, + * only for TCG. */ cpu->prop_pauth =3D cpu_isar_feature(aa64_pauth, cpu); } else { @@ -695,6 +700,7 @@ static void aarch64_host_initfn(Object *obj) #elif defined(CONFIG_HVF) ARMCPU *cpu =3D ARM_CPU(obj); hvf_arm_set_cpu_features_from_host(cpu); + aarch64_add_pauth_properties(obj); #else g_assert_not_reached(); #endif --=20 2.25.1