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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1643960962505100001 Content-Type: text/plain; charset="utf-8" This will allow us to control exactly what scratch register is used for loading the constant. Also, fix a theoretical problem in recursing through tcg_out_movi, which may provide a different value for in_prologue. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 0c062c60eb..7e3758b798 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -414,7 +414,8 @@ static void tcg_out_movi_imm13(TCGContext *s, TCGReg re= t, int32_t arg) } =20 static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long arg, bool in_prologue) + tcg_target_long arg, bool in_prologue, + TCGReg scratch) { tcg_target_long hi, lo =3D (int32_t)arg; tcg_target_long test, lsb; @@ -471,22 +472,24 @@ static void tcg_out_movi_int(TCGContext *s, TCGType t= ype, TCGReg ret, /* A 64-bit constant decomposed into 2 32-bit pieces. */ if (check_fit_i32(lo, 13)) { hi =3D (arg - lo) >> 32; - tcg_out_movi(s, TCG_TYPE_I32, ret, hi); + tcg_out_movi_int(s, TCG_TYPE_I32, ret, hi, in_prologue, scratch); tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); tcg_out_arithi(s, ret, ret, lo, ARITH_ADD); } else { + tcg_debug_assert(scratch !=3D TCG_REG_G0); hi =3D arg >> 32; - tcg_out_movi(s, TCG_TYPE_I32, ret, hi); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T2, lo); + tcg_out_movi_int(s, TCG_TYPE_I32, ret, hi, in_prologue, scratch); + tcg_out_movi_int(s, TCG_TYPE_I32, scratch, lo, in_prologue, TCG_RE= G_G0); tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); - tcg_out_arith(s, ret, ret, TCG_REG_T2, ARITH_OR); + tcg_out_arith(s, ret, ret, scratch, ARITH_OR); } } =20 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { - tcg_out_movi_int(s, type, ret, arg, false); + tcg_debug_assert(ret !=3D TCG_REG_T2); + tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T2); } =20 static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, @@ -837,7 +840,7 @@ static void tcg_out_call_nodelay(TCGContext *s, const t= cg_insn_unit *dest, } else { uintptr_t desti =3D (uintptr_t)dest; tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, - desti & ~0xfff, in_prologue); + desti & ~0xfff, in_prologue, TCG_REG_O7); tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL); } } @@ -1013,7 +1016,8 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 #ifndef CONFIG_SOFTMMU if (guest_base !=3D 0) { - tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, = true); + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, + true, TCG_REG_T1); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } #endif --=20 2.25.1 From nobody Mon Feb 9 15:17:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1643959452; cv=none; d=zohomail.com; s=zohoarc; b=HT9hRvt6WiNEHUF2itwHwwIyOMJY1cKmBjHnca1keT4wONPTNLvPMNI6yxgcxzASR0Zq6zkzynnOggLoVSS9H0rJU2lfPhfLvyhkmGWLWDpmN8CTBXMqe3NWx9mVe4ULCU1SdtWp/Vfz51cwWNMFF2owwc4dws0zjeBIuoloe44= ARC-Message-Signature: i=1; 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Thu, 03 Feb 2022 23:00:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 2/5] tcg/sparc: Improve code gen for shifted 32-bit constants Date: Fri, 4 Feb 2022 18:00:08 +1100 Message-Id: <20220204070011.573941-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220204070011.573941-1-richard.henderson@linaro.org> References: <20220204070011.573941-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::430 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1643959454895100001 Content-Type: text/plain; charset="utf-8" We had code for checking for 13 and 21-bit shifted constants, but we can do better and allow 32-bit shifted constants. This is still 2 insns shorter than the full 64-bit sequence. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/sparc/tcg-target.c.inc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 7e3758b798..6349f750cc 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -456,17 +456,17 @@ static void tcg_out_movi_int(TCGContext *s, TCGType t= ype, TCGReg ret, return; } =20 - /* A 21-bit constant, shifted. */ + /* A 32-bit constant, shifted. */ lsb =3D ctz64(arg); test =3D (tcg_target_long)arg >> lsb; - if (check_fit_tl(test, 13)) { - tcg_out_movi_imm13(s, ret, test); - tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); - return; - } else if (lsb > 10 && test =3D=3D extract64(test, 0, 21)) { + if (lsb > 10 && test =3D=3D extract64(test, 0, 21)) { tcg_out_sethi(s, ret, test << 10); tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX); return; + } else if (test =3D=3D (uint32_t)test || test =3D=3D (int32_t)test) { + tcg_out_movi_int(s, TCG_TYPE_I64, ret, test, in_prologue, scratch); + tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); + return; } =20 /* A 64-bit constant decomposed into 2 32-bit pieces. */ --=20 2.25.1 From nobody Mon Feb 9 15:17:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1643960986; cv=none; d=zohomail.com; s=zohoarc; b=j4G+jgmbuu7OtzG3ptNc//XOQVbbKPuMiMYFUCqBnWUmg0AecatNSOCndIz0INhEYv08sek3sj3njsgtnrTXDWWXFYiCPXZmJFBoUGEo3W3EKXit7SEP3oXthID0ku0X7tx/Dj1CatENzKiMnJ8Hut2t1Dh5sb+41FZzU7TG91M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1643960986; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=l5/xMg5JmnQhX3P7JdxIT0db5qBXvDtWPFnoD+IGj8I=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1643960988792100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/sparc/tcg-target.c.inc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 6349f750cc..47bdf314a0 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -332,6 +332,13 @@ static bool patch_reloc(tcg_insn_unit *src_rw, int typ= e, insn &=3D ~INSN_OFF19(-1); insn |=3D INSN_OFF19(pcrel); break; + case R_SPARC_13: + if (!check_fit_ptr(value, 13)) { + return false; + } + insn &=3D ~INSN_IMM13(-1); + insn |=3D INSN_IMM13(value); + break; default: g_assert_not_reached(); } @@ -469,6 +476,14 @@ static void tcg_out_movi_int(TCGContext *s, TCGType ty= pe, TCGReg ret, return; } =20 + /* Use the constant pool, if possible. */ + if (!in_prologue && USE_REG_TB) { + new_pool_label(s, arg, R_SPARC_13, s->code_ptr, + tcg_tbrel_diff(s, NULL)); + tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(TCG_REG_TB)); + return; + } + /* A 64-bit constant decomposed into 2 32-bit pieces. */ if (check_fit_i32(lo, 13)) { hi =3D (arg - lo) >> 32; --=20 2.25.1 From nobody Mon Feb 9 15:17:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Thu, 03 Feb 2022 23:00:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 4/5] tcg/sparc: Add tcg_out_jmpl_const for better tail calls Date: Fri, 4 Feb 2022 18:00:10 +1100 Message-Id: <20220204070011.573941-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220204070011.573941-1-richard.henderson@linaro.org> References: <20220204070011.573941-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::f2e (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2e; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2e.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1643961139709100001 Content-Type: text/plain; charset="utf-8" Due to mapping changes, we now rarely place the code_gen_buffer near the main executable. Which means that direct calls will now rarely be in range. So, always use indirect calls for tail calls, which allows us to avoid clobbering %o7, and therefore we need not save and restore it. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/sparc/tcg-target.c.inc | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 47bdf314a0..82a9d88816 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -845,6 +845,19 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg = rl, TCGReg rh, tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); } =20 +static void tcg_out_jmpl_const(TCGContext *s, const tcg_insn_unit *dest, + bool in_prologue, bool tail_call) +{ + uintptr_t desti =3D (uintptr_t)dest; + + /* Be careful not to clobber %o7 for a tail call. */ + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, + desti & ~0xfff, in_prologue, + tail_call ? TCG_REG_G2 : TCG_REG_O7); + tcg_out_arithi(s, tail_call ? TCG_REG_G0 : TCG_REG_O7, + TCG_REG_T1, desti & 0xfff, JMPL); +} + static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, bool in_prologue) { @@ -853,10 +866,7 @@ static void tcg_out_call_nodelay(TCGContext *s, const = tcg_insn_unit *dest, if (disp =3D=3D (int32_t)disp) { tcg_out32(s, CALL | (uint32_t)disp >> 2); } else { - uintptr_t desti =3D (uintptr_t)dest; - tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, - desti & ~0xfff, in_prologue, TCG_REG_O7); - tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL); + tcg_out_jmpl_const(s, dest, in_prologue, false); } } =20 @@ -947,11 +957,10 @@ static void build_trampolines(TCGContext *s) =20 /* Set the retaddr operand. */ tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); - /* Set the env operand. */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); /* Tail call. */ - tcg_out_call_nodelay(s, qemu_ld_helpers[i], true); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); + tcg_out_jmpl_const(s, qemu_ld_helpers[i], true, true); + /* delay slot -- set the env argument */ + tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0); } =20 for (i =3D 0; i < ARRAY_SIZE(qemu_st_helpers); ++i) { @@ -993,14 +1002,14 @@ static void build_trampolines(TCGContext *s) if (ra >=3D TCG_REG_O6) { tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK, TCG_TARGET_CALL_STACK_OFFSET); - ra =3D TCG_REG_G1; + } else { + tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); } - tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); - /* Set the env operand. */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); + /* Tail call. */ - tcg_out_call_nodelay(s, qemu_st_helpers[i], true); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); + tcg_out_jmpl_const(s, qemu_st_helpers[i], true, true); + /* delay slot -- set the env argument */ + tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0); } } #endif --=20 2.25.1 From nobody Mon Feb 9 15:17:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1643962268332100001 Content-Type: text/plain; charset="utf-8" This is kinda sorta the opposite of the other tcg hosts, where we get (normal) alignment checks for free with host SIGBUS and need to add code to support unaligned accesses. This inline code expansion is somewhat large, but it takes quite a few instructions to make a function call to a helper anyway. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 308 +++++++++++++++++++++++++++++++++++-- 1 file changed, 299 insertions(+), 9 deletions(-) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 82a9d88816..a0d206380c 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -211,6 +211,7 @@ static const int tcg_target_call_oarg_regs[] =3D { #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) +#define ARITH_ANDCC (INSN_OP(2) | INSN_OP3(0x11)) #define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05)) #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) @@ -997,7 +998,7 @@ static void build_trampolines(TCGContext *s) /* Skip the oi argument. */ ra +=3D 1; } - =20 + /* Set the retaddr operand. */ if (ra >=3D TCG_REG_O6) { tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK, @@ -1012,6 +1013,38 @@ static void build_trampolines(TCGContext *s) tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0); } } +#else +static const tcg_insn_unit *qemu_unalign_ld_trampoline; +static const tcg_insn_unit *qemu_unalign_st_trampoline; + +static void build_trampolines(TCGContext *s) +{ + for (int ld =3D 0; ld < 2; ++ld) { + void *helper; + + while ((uintptr_t)s->code_ptr & 15) { + tcg_out_nop(s); + } + + if (ld) { + helper =3D helper_unaligned_ld; + qemu_unalign_ld_trampoline =3D tcg_splitwx_to_rx(s->code_ptr); + } else { + helper =3D helper_unaligned_st; + qemu_unalign_st_trampoline =3D tcg_splitwx_to_rx(s->code_ptr); + } + + if (!SPARC64 && TARGET_LONG_BITS =3D=3D 64) { + /* Install the high part of the address. */ + tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX); + } + + /* Tail call. */ + tcg_out_jmpl_const(s, helper, true, true); + /* delay slot -- set the env argument */ + tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0); + } +} #endif =20 /* Generate global QEMU prologue and epilogue code */ @@ -1062,9 +1095,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) /* delay slot */ tcg_out_movi_imm13(s, TCG_REG_O0, 0); =20 -#ifdef CONFIG_SOFTMMU build_trampolines(s); -#endif } =20 static void tcg_out_nop_fill(tcg_insn_unit *p, int count) @@ -1149,18 +1180,22 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGRe= g addr, int mem_index, static const int qemu_ld_opc[(MO_SSIZE | MO_BSWAP) + 1] =3D { [MO_UB] =3D LDUB, [MO_SB] =3D LDSB, + [MO_UB | MO_LE] =3D LDUB, + [MO_SB | MO_LE] =3D LDSB, =20 [MO_BEUW] =3D LDUH, [MO_BESW] =3D LDSH, [MO_BEUL] =3D LDUW, [MO_BESL] =3D LDSW, [MO_BEUQ] =3D LDX, + [MO_BESQ] =3D LDX, =20 [MO_LEUW] =3D LDUH_LE, [MO_LESW] =3D LDSH_LE, [MO_LEUL] =3D LDUW_LE, [MO_LESL] =3D LDSW_LE, [MO_LEUQ] =3D LDX_LE, + [MO_LESQ] =3D LDX_LE, }; =20 static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1] =3D { @@ -1179,11 +1214,12 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= ata, TCGReg addr, MemOpIdx oi, bool is_64) { MemOp memop =3D get_memop(oi); + tcg_insn_unit *label_ptr; + #ifdef CONFIG_SOFTMMU unsigned memi =3D get_mmuidx(oi); TCGReg addrz, param; const tcg_insn_unit *func; - tcg_insn_unit *label_ptr; =20 addrz =3D tcg_out_tlb_load(s, addr, memi, memop, offsetof(CPUTLBEntry, addr_read)); @@ -1247,13 +1283,190 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg = data, TCGReg addr, =20 *label_ptr |=3D INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); #else + TCGReg index =3D (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0); + unsigned a_bits =3D get_alignment_bits(memop); + unsigned s_bits =3D memop & MO_SIZE; + unsigned t_bits; + TCGReg orig_addr =3D addr; + if (SPARC64 && TARGET_LONG_BITS =3D=3D 32) { tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); addr =3D TCG_REG_T1; } - tcg_out_ldst_rr(s, data, addr, - (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0), + + /* + * Normal case: alignment equal to access size. + */ + if (a_bits =3D=3D s_bits) { + tcg_out_ldst_rr(s, data, addr, index, + qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); + return; + } + + /* + * Test for at least natural alignment, and assume most accesses + * will be aligned -- perform a straight load in the delay slot. + * This is required to preserve atomicity for aligned accesses. + */ + t_bits =3D MAX(a_bits, s_bits); + tcg_debug_assert(t_bits < 13); + tcg_out_arithi(s, TCG_REG_G0, addr, (1u << t_bits) - 1, ARITH_ANDCC); + + /* beq,a,pt %icc, label */ + label_ptr =3D s->code_ptr; + tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT | BPCC_ICC, 0); + /* delay slot */ + tcg_out_ldst_rr(s, data, addr, index, qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); + + /* + * Overalignment: When we're asking for really large alignment, + * the actual access is always done above and all we need to do + * here is invoke the handler for SIGBUS. + */ + if (a_bits >=3D s_bits) { + TCGReg arg_low =3D TCG_REG_O1 + (!SPARC64 && TARGET_LONG_BITS =3D= =3D 64); + tcg_out_call_nodelay(s, qemu_unalign_ld_trampoline, false); + /* delay slot -- move to low part of argument reg */ + tcg_out_mov_delay(s, arg_low, addr); + goto done; + } + + /* + * Underalignment: use multiple loads to perform the operation. + * + * Force full address into T1 early; avoids problems with + * overlap between @addr and @data. + * + * Note that the little-endian instructions use the immediate + * asi form, and must use tcg_out_ldst_rr. + */ + tcg_out_arith(s, TCG_REG_T1, addr, index, ARITH_ADD); + + switch ((unsigned)memop) { + case MO_BEUW | MO_UNALN: + case MO_BESW | MO_UNALN: + case MO_BEUL | MO_ALIGN_2: + case MO_BESL | MO_ALIGN_2: + case MO_BEUQ | MO_ALIGN_4: + /* Two loads: shift and combine. */ + tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, 0, + qemu_ld_opc[a_bits | MO_BE | (memop & MO_SIGN)]); + tcg_out_ldst(s, data, TCG_REG_T1, 1 << a_bits, + qemu_ld_opc[a_bits | MO_BE]); + tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, 8 << a_bits, SHIFT_SLLX); + tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR); + break; + + case MO_LEUW | MO_UNALN: + case MO_LESW | MO_UNALN: + case MO_LEUL | MO_ALIGN_2: + case MO_LESL | MO_ALIGN_2: + case MO_LEUQ | MO_ALIGN_4: + /* Similarly, with shifts adjusted for little-endian. */ + tcg_out_ldst_rr(s, TCG_REG_T2, TCG_REG_T1, TCG_REG_G0, + qemu_ld_opc[a_bits | MO_LE]); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 1 << a_bits, ARITH_ADD); + tcg_out_ldst_rr(s, data, TCG_REG_T1, TCG_REG_G0, + qemu_ld_opc[a_bits | MO_LE | (memop & MO_SIGN)]); + tcg_out_arithi(s, data, data, 8 << a_bits, SHIFT_SLLX); + tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR); + break; + + case MO_BEUL | MO_UNALN: + case MO_BESL | MO_UNALN: + /* + * Naively, this would require 4 loads, 3 shifts, 3 ors. + * Use two 32-bit aligned loads, combine, and extract. + */ + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 3, ARITH_ANDN); + tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, 0, LDUW); + tcg_out_ldst(s, TCG_REG_T1, TCG_REG_T1, 4, LDUW); + tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, 32, SHIFT_SLLX); + tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T2, ARITH_OR); + tcg_out_arithi(s, TCG_REG_T2, orig_addr, 3, ARITH_AND); + tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, 3, SHIFT_SLL); + tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T2, SHIFT_SLLX); + tcg_out_arithi(s, data, TCG_REG_T1, 32, + memop & MO_SIGN ? SHIFT_SRAX : SHIFT_SRLX); + break; + + case MO_LEUL | MO_UNALN: + case MO_LESL | MO_UNALN: + /* Similarly, with shifts adjusted for little-endian. */ + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 3, ARITH_ANDN); + tcg_out_ldst_rr(s, TCG_REG_T2, TCG_REG_T1, TCG_REG_G0, LDUW_LE); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 4, ARITH_ADD); + tcg_out_ldst_rr(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_G0, LDUW_LE); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 32, SHIFT_SLLX); + tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T2, ARITH_OR); + tcg_out_arithi(s, TCG_REG_T2, orig_addr, 3, ARITH_AND); + tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, 3, SHIFT_SLL); + tcg_out_arith(s, data, TCG_REG_T1, TCG_REG_T2, SHIFT_SRLX); + if (is_64) { + tcg_out_arithi(s, data, data, 0, + memop & MO_SIGN ? SHIFT_SRA : SHIFT_SRL); + } + break; + + case MO_BEUQ | MO_UNALN: + /* Similarly for 64-bit. */ + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 7, ARITH_ANDN); + tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, 0, LDX); + tcg_out_ldst(s, TCG_REG_T1, TCG_REG_T1, 8, LDX); + tcg_out_arithi(s, data, orig_addr, 7, ARITH_AND); + tcg_out_arithi(s, data, data, 3, SHIFT_SLL); + tcg_out_arith(s, TCG_REG_T2, TCG_REG_T2, data, SHIFT_SLLX); + tcg_out_arithi(s, data, data, 64, ARITH_SUB); + tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, data, SHIFT_SRLX); + tcg_out_arith(s, data, TCG_REG_T1, TCG_REG_T2, ARITH_OR); + break; + + case MO_LEUQ | MO_UNALN: + /* Similarly for little-endian. */ + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 7, ARITH_ANDN); + tcg_out_ldst_rr(s, TCG_REG_T2, TCG_REG_T1, TCG_REG_G0, LDX_LE); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 8, ARITH_ADD); + tcg_out_ldst_rr(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_G0, LDX_LE); + tcg_out_arithi(s, data, orig_addr, 7, ARITH_AND); + tcg_out_arithi(s, data, data, 3, SHIFT_SLL); + tcg_out_arith(s, TCG_REG_T2, TCG_REG_T2, data, SHIFT_SRLX); + tcg_out_arithi(s, data, data, 64, ARITH_SUB); + tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, data, SHIFT_SLLX); + tcg_out_arith(s, data, TCG_REG_T1, TCG_REG_T2, ARITH_OR); + break; + + case MO_BEUQ | MO_ALIGN_2: + /* + * An extra test to verify alignment 2 is 5 insns, which + * is more than we would save by using the slightly smaller + * unaligned sequence above. + */ + tcg_out_ldst(s, data, TCG_REG_T1, 0, LDUH); + for (int i =3D 2; i < 8; i +=3D 2) { + tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, i, LDUW); + tcg_out_arithi(s, data, data, 16, SHIFT_SLLX); + tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR); + } + break; + + case MO_LEUQ | MO_ALIGN_2: + /* Similarly for little-endian. */ + tcg_out_ldst_rr(s, data, TCG_REG_T1, TCG_REG_G0, LDUH_LE); + for (int i =3D 2; i < 8; i +=3D 2) { + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 2, ARITH_ADD); + tcg_out_ldst_rr(s, TCG_REG_T2, TCG_REG_T1, TCG_REG_G0, LDUW_LE= ); + tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, i * 8, SHIFT_SLLX); + tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR); + } + break; + + default: + g_assert_not_reached(); + } + + done: + *label_ptr |=3D INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); #endif /* CONFIG_SOFTMMU */ } =20 @@ -1261,11 +1474,12 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= ata, TCGReg addr, MemOpIdx oi) { MemOp memop =3D get_memop(oi); + tcg_insn_unit *label_ptr; + #ifdef CONFIG_SOFTMMU unsigned memi =3D get_mmuidx(oi); TCGReg addrz, param; const tcg_insn_unit *func; - tcg_insn_unit *label_ptr; =20 addrz =3D tcg_out_tlb_load(s, addr, memi, memop, offsetof(CPUTLBEntry, addr_write)); @@ -1302,13 +1516,89 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= ata, TCGReg addr, =20 *label_ptr |=3D INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); #else + TCGReg index =3D (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0); + unsigned a_bits =3D get_alignment_bits(memop); + unsigned s_bits =3D memop & MO_SIZE; + unsigned t_bits; + if (SPARC64 && TARGET_LONG_BITS =3D=3D 32) { tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); addr =3D TCG_REG_T1; } - tcg_out_ldst_rr(s, data, addr, - (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0), + + /* + * Normal case: alignment equal to access size. + */ + if (a_bits =3D=3D s_bits) { + tcg_out_ldst_rr(s, data, addr, index, + qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); + return; + } + + /* + * Test for at least natural alignment, and assume most accesses + * will be aligned -- perform a straight store in the delay slot. + * This is required to preserve atomicity for aligned accesses. + */ + t_bits =3D MAX(a_bits, s_bits); + tcg_debug_assert(t_bits < 13); + tcg_out_arithi(s, TCG_REG_G0, addr, (1u << t_bits) - 1, ARITH_ANDCC); + + /* beq,a,pt %icc, label */ + label_ptr =3D s->code_ptr; + tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT | BPCC_ICC, 0); + /* delay slot */ + tcg_out_ldst_rr(s, data, addr, index, qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); + + if (a_bits >=3D s_bits) { + TCGReg arg_low =3D TCG_REG_O1 + (!SPARC64 && TARGET_LONG_BITS =3D= =3D 64); + /* Overalignment: only need to call helper for SIGBUS. */ + tcg_out_call_nodelay(s, qemu_unalign_st_trampoline, false); + /* delay slot -- move to low part of argument reg */ + tcg_out_mov_delay(s, arg_low, addr); + } else { + /* Underalignment: store by pieces of minimum alignment. */ + int st_opc, a_size, s_size, i; + + /* + * Force full address into T1 early; avoids problems with + * overlap between @addr and @data. + */ + tcg_out_arith(s, TCG_REG_T1, addr, index, ARITH_ADD); + + a_size =3D 1 << a_bits; + s_size =3D 1 << (memop & MO_SIZE); + if ((memop & MO_BSWAP) =3D=3D MO_BE) { + st_opc =3D qemu_st_opc[a_bits + MO_BE]; + for (i =3D 0; i < s_size; i +=3D a_size) { + TCGReg d =3D data; + int shift =3D (s_size - a_size - i) * 8; + if (shift) { + d =3D TCG_REG_T2; + tcg_out_arithi(s, d, data, shift, SHIFT_SRLX); + } + tcg_out_ldst(s, d, TCG_REG_T1, i, st_opc); + } + } else if (a_bits =3D=3D 0) { + tcg_out_ldst(s, data, TCG_REG_T1, 0, STB); + for (i =3D 1; i < s_size; i++) { + tcg_out_arithi(s, TCG_REG_T2, data, i * 8, SHIFT_SRLX); + tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, i, STB); + } + } else { + /* Note that ST*A with immediate asi must use indexed address.= */ + st_opc =3D qemu_st_opc[a_bits + MO_LE]; + tcg_out_ldst_rr(s, data, TCG_REG_T1, TCG_REG_G0, st_opc); + for (i =3D a_size; i < s_size; i +=3D a_size) { + tcg_out_arithi(s, TCG_REG_T2, data, i * 8, SHIFT_SRLX); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, a_size, ARITH_AD= D); + tcg_out_ldst_rr(s, TCG_REG_T2, TCG_REG_T1, TCG_REG_G0, st_= opc); + } + } + } + + *label_ptr |=3D INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); #endif /* CONFIG_SOFTMMU */ } =20 --=20 2.25.1