From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643628642374566.1861436720228; Mon, 31 Jan 2022 03:30:42 -0800 (PST) Received: from localhost ([::1]:44590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEUtN-0007lO-IS for importer@patchew.org; Mon, 31 Jan 2022 06:30:41 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34128) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYe-00060x-6Y; Mon, 31 Jan 2022 06:09:18 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:23454) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYb-00053O-3n; Mon, 31 Jan 2022 06:09:15 -0500 Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 20V98Y2j019350; Mon, 31 Jan 2022 11:08:20 GMT Received: from ppma03fra.de.ibm.com (6b.4a.5195.ip4.static.sl-reverse.com [149.81.74.107]) by mx0a-001b2d01.pphosted.com with ESMTP id 3dx66b8abr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 31 Jan 2022 11:08:19 +0000 Received: from pps.filterd (ppma03fra.de.ibm.com [127.0.0.1]) by ppma03fra.de.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 20VB2MpP018213; Mon, 31 Jan 2022 11:08:17 GMT Received: from b06cxnps3075.portsmouth.uk.ibm.com (d06relay10.portsmouth.uk.ibm.com [9.149.109.195]) by ppma03fra.de.ibm.com with ESMTP id 3dvw799ueh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 31 Jan 2022 11:08:17 +0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 20VB8Fvh40304900 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 31 Jan 2022 11:08:15 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 344DD4C040; Mon, 31 Jan 2022 11:08:15 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D44B54C046; Mon, 31 Jan 2022 11:08:14 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av22.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:14 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 042322201C1; Mon, 31 Jan 2022 12:08:13 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 01/41] spapr: Force 32bit when resetting a core Date: Mon, 31 Jan 2022 12:07:31 +0100 Message-Id: <20220131110811.619053-2-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 69UHk-AKW-NoaKy3ItjFb64aWp8pHUVs X-Proofpoint-ORIG-GUID: 69UHk-AKW-NoaKy3ItjFb64aWp8pHUVs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1034 impostorscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=620 priorityscore=1501 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643628663440100001 Content-Type: text/plain; charset="utf-8" From: Alexey Kardashevskiy "PowerPC Processor binding to IEEE 1275" says in "8.2.1. Initial Register Values" that the initial state is defined as 32bit so do it for both SLOF and VOF. This should not cause behavioral change as SLOF switches to 64bit very early anyway. As nothing enforces LE anywhere, this drops it for VOF. The goal is to make VOF work with TCG as otherwise it barfs with qemu: fatal: TCG hflags mismatch (current:0x6c000004 rebuilt:0x6c000000) Signed-off-by: Alexey Kardashevskiy Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220107072423.2278113-1-aik@ozlabs.ru> Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/spapr_cpu_core.c | 5 +++++ hw/ppc/spapr_vof.c | 2 -- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index a57ba70a8781..a781e97f8d1d 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -37,6 +37,11 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu) =20 cpu_reset(cs); =20 + /* + * "PowerPC Processor binding to IEEE 1275" defines the initial MSR st= ate + * as 32bit (MSR_SF=3D0) in "8.2.1. Initial Register Values". + */ + env->msr &=3D ~(1ULL << MSR_SF); env->spr[SPR_HIOR] =3D 0; =20 lpcr =3D env->spr[SPR_LPCR]; diff --git a/hw/ppc/spapr_vof.c b/hw/ppc/spapr_vof.c index 40ce8fe0037c..a33f940c32bb 100644 --- a/hw/ppc/spapr_vof.c +++ b/hw/ppc/spapr_vof.c @@ -88,8 +88,6 @@ void spapr_vof_reset(SpaprMachineState *spapr, void *fdt,= Error **errp) spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, stack_ptr, spapr->initrd_base, spapr->initrd_size); - /* VOF is 32bit BE so enforce MSR here */ - first_ppc_cpu->env.msr &=3D ~((1ULL << MSR_SF) | (1ULL << MSR_LE)); =20 /* * At this point the expected allocation map is: --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164363212615655.35261249978055; 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Mon, 31 Jan 2022 11:08:15 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av26.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:15 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id BD32A220149; Mon, 31 Jan 2022 12:08:14 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 02/41] target/ppc: 603: fix restore of GPRs 0-3 on rfi Date: Mon, 31 Jan 2022 12:07:32 +0100 Message-Id: <20220131110811.619053-3-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: p8XCBmS88gvI6c0Y546pOMRELSJqBSKu X-Proofpoint-GUID: p8XCBmS88gvI6c0Y546pOMRELSJqBSKu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=879 lowpriorityscore=0 suspectscore=0 malwarescore=0 mlxscore=0 bulkscore=0 clxscore=1034 phishscore=0 impostorscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Cedric Le Goater , Christophe Leroy , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643632127654100001 Content-Type: text/plain; charset="utf-8" From: Christophe Leroy After a TLB miss exception, GPRs 0-3 must be restored on rfi. This is managed by hreg_store_msr() which is called by do_rfi() However, hreg_store_msr() does it if MSR[TGPR] is unset in the passed MSR value. The problem is that do_rfi() is given the content of SRR1 as the value to be set in MSR, but TGPR bit is not part of SRR1 and that bit is used for something else and is sometimes set to 1, leading to hreg_store_msr() not restoring GPRs. So, do the same way as for POW bit, force clearing it. Signed-off-by: Christophe Leroy Cc: Cedric Le Goater Cc: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220120103824.239573-1-christophe.leroy@csgroup.eu> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index bc646c67a0f5..980f62fd7964 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1164,6 +1164,10 @@ static void do_rfi(CPUPPCState *env, target_ulong ni= p, target_ulong msr) /* MSR:POW cannot be set by any form of rfi */ msr &=3D ~(1ULL << MSR_POW); =20 + /* MSR:TGPR cannot be set by any form of rfi */ + if (env->flags & POWERPC_FLAG_TGPR) + msr &=3D ~(1ULL << MSR_TGPR); + #if defined(TARGET_PPC64) /* Switching to 32-bit ? Crop the nip */ if (!msr_is_64bit(env, msr)) { --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643636179428355.8126663944456; Mon, 31 Jan 2022 05:36:19 -0800 (PST) Received: from localhost ([::1]:33158 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEWqv-0001Qa-TG for importer@patchew.org; Mon, 31 Jan 2022 08:36:17 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34724) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUZ9-0006Fh-NK; Mon, 31 Jan 2022 06:09:50 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:32098) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUZ8-00054u-0w; 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Mon, 31 Jan 2022 11:08:19 +0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 20VAwUgm40829408 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 31 Jan 2022 10:58:31 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3E8F2A4040; Mon, 31 Jan 2022 11:08:17 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BC580A404D; Mon, 31 Jan 2022 11:08:16 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av23.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:16 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 965FC2201C1; Mon, 31 Jan 2022 12:08:15 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 03/41] target/ppc/mmu_common: Fix SRR1/MSR error code on Book-E Date: Mon, 31 Jan 2022 12:07:33 +0100 Message-Id: <20220131110811.619053-4-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 0MC8vO3WyGVq73AjNdp_pneZ_L2dTfPC X-Proofpoint-GUID: NZcBrZ1WAMQYMmejCJHqko8AVfBLuc_G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=704 spamscore=0 lowpriorityscore=0 adultscore=0 clxscore=1034 priorityscore=1501 bulkscore=0 phishscore=0 suspectscore=0 malwarescore=0 mlxscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Daniel Henrique Barboza , Richard Henderson , Greg Kurz , qemu-stable@nongnu.org, Vitaly Cheptsov , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643636181953100003 Content-Type: text/plain; charset="utf-8" From: Vitaly Cheptsov Book-E architecture does not set the error code in 31:27 bits of SRR1, but instead uses these bits for custom fields such as GS (Guest Supervisor). Wrongly setting these fields will result in QEMU crashes when attempting to execute not executable code due to the attempts to use Guest Supervisor mode. Cc: "C=C3=A9dric Le Goater" Cc: Daniel Henrique Barboza Cc: David Gibson Cc: Greg Kurz Cc: qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org Signed-off-by: Vitaly Cheptsov Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220121093107.15478-1-cheptsov@ispras.ru> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/mmu_common.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 91270c1f17eb..6512ee031cfc 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -1367,22 +1367,34 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr = eaddr, case -2: /* Access rights violation */ cs->exception_index =3D POWERPC_EXCP_ISI; - env->error_code =3D 0x08000000; + if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || + (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { + env->error_code =3D 0; + } else { + env->error_code =3D 0x08000000; + } break; case -3: /* No execute protection violation */ if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { env->spr[SPR_BOOKE_ESR] =3D 0x00000000; + env->error_code =3D 0; + } else { + env->error_code =3D 0x10000000; } cs->exception_index =3D POWERPC_EXCP_ISI; - env->error_code =3D 0x10000000; break; case -4: /* Direct store exception */ /* No code fetch is allowed in direct-store areas */ cs->exception_index =3D POWERPC_EXCP_ISI; - env->error_code =3D 0x10000000; + if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || + (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { + env->error_code =3D 0; + } else { + env->error_code =3D 0x10000000; + } break; } } else { --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643629285323209.9788762789019; Mon, 31 Jan 2022 03:41:25 -0800 (PST) Received: from localhost ([::1]:39326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEV3k-0007NQ-EL for importer@patchew.org; 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Mon, 31 Jan 2022 11:08:17 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:17 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id A6BAE220149; Mon, 31 Jan 2022 12:08:16 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 04/41] ppc/pnv: Fail DMA access if page permissions are not correct Date: Mon, 31 Jan 2022 12:07:34 +0100 Message-Id: <20220131110811.619053-5-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: K_t2vxeyDVyM71mrsXRZPrSsnsA86b8f X-Proofpoint-GUID: D0Yg2Oa_GhHfAne49tLAhSFsqPrx1Czi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 suspectscore=0 phishscore=0 impostorscore=0 malwarescore=0 mlxlogscore=922 bulkscore=0 adultscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frederic Barrat , Peter Maydell , Daniel Henrique Barboza , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643629287329100001 Content-Type: text/plain; charset="utf-8" From: Frederic Barrat If an iommu page has wrong permissions, an error message is displayed, but the access is allowed, which is odd. This patch fixes it. Signed-off-by: Frederic Barrat Reviewed-by: Daniel Henrique Barboza Message-Id: <20220121152350.381685-1-fbarrat@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- hw/pci-host/pnv_phb3.c | 11 ++++++----- hw/pci-host/pnv_phb4.c | 11 ++++++----- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index 7fb35dc03147..a757f1a58ec8 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -816,18 +816,19 @@ static void pnv_phb3_translate_tve(PnvPhb3DMASpace *d= s, hwaddr addr, } =20 /* We exit the loop with TCE being the final TCE */ - tce_mask =3D ~((1ull << tce_shift) - 1); - tlb->iova =3D addr & tce_mask; - tlb->translated_addr =3D tce & tce_mask; - tlb->addr_mask =3D ~tce_mask; - tlb->perm =3D tce & 3; if ((is_write & !(tce & 2)) || ((!is_write) && !(tce & 1))) { phb3_error(phb, "TCE access fault at 0x%"PRIx64, taddr); phb3_error(phb, " xlate %"PRIx64":%c TVE=3D%"PRIx64, addr, is_write ? 'W' : 'R', tve); phb3_error(phb, " tta=3D%"PRIx64" lev=3D%d tts=3D%d tps=3D%d", tta, lev, tts, tps); + return; } + tce_mask =3D ~((1ull << tce_shift) - 1); + tlb->iova =3D addr & tce_mask; + tlb->translated_addr =3D tce & tce_mask; + tlb->addr_mask =3D ~tce_mask; + tlb->perm =3D tce & 3; } } =20 diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index a78add75b043..ee56377c02be 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1291,18 +1291,19 @@ static void pnv_phb4_translate_tve(PnvPhb4DMASpace = *ds, hwaddr addr, } =20 /* We exit the loop with TCE being the final TCE */ - tce_mask =3D ~((1ull << tce_shift) - 1); - tlb->iova =3D addr & tce_mask; - tlb->translated_addr =3D tce & tce_mask; - tlb->addr_mask =3D ~tce_mask; - tlb->perm =3D tce & 3; if ((is_write & !(tce & 2)) || ((!is_write) && !(tce & 1))) { phb_error(ds->phb, "TCE access fault at 0x%"PRIx64, taddr); phb_error(ds->phb, " xlate %"PRIx64":%c TVE=3D%"PRIx64, addr, is_write ? 'W' : 'R', tve); phb_error(ds->phb, " tta=3D%"PRIx64" lev=3D%d tts=3D%d tps=3D%= d", tta, lev, tts, tps); + return; } + tce_mask =3D ~((1ull << tce_shift) - 1); + tlb->iova =3D addr & tce_mask; + tlb->translated_addr =3D tce & tce_mask; + tlb->addr_mask =3D ~tce_mask; + tlb->perm =3D tce & 3; } } =20 --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643628249539194.93983734664505; Mon, 31 Jan 2022 03:24:09 -0800 (PST) Received: from localhost ([::1]:33424 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEUn0-0008LJ-Bv for importer@patchew.org; Mon, 31 Jan 2022 06:24:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34104) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYe-00060w-29; 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Mon, 31 Jan 2022 11:08:18 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av26.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:18 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 9D9B82201C1; Mon, 31 Jan 2022 12:08:17 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 05/41] ppc/pnv: use a do-while() loop in pnv_phb3_translate_tve() Date: Mon, 31 Jan 2022 12:07:35 +0100 Message-Id: <20220131110811.619053-6-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: TAx0p68UvMm9hZzCj-wykyJEO9CEVIbY X-Proofpoint-GUID: PDoRibSI5nXzHICQFJLtO0-hXjpjrmDw Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 suspectscore=0 phishscore=0 impostorscore=0 malwarescore=0 mlxlogscore=892 bulkscore=0 adultscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Daniel Henrique Barboza , Richard Henderson , "Matheus K . Ferst" , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643628250780100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The 'taddr' variable is left unintialized, being set only inside the "while ((lev--) >=3D 0)" loop where we get the TCE address. The 'lev' var is an int32_t that is being initiliazed by the GETFIELD() macro, which returns an uint64_t. For a human reader this means that 'lev' will always be positive or zero. But some compilers may beg to differ. 'lev' being an int32_t can in theory be set as negative, and the "while ((lev--) >=3D 0)" loop might never be reached, and 'taddr' will be left unitialized. This can cause phb3_error() to use 'taddr' uninitialized down below: if ((is_write & !(tce & 2)) || ((!is_write) && !(tce & 1))) { phb3_error(phb, "TCE access fault at 0x%"PRIx64, taddr); A quick way of fixing it is to use a do/while() loop. This will keep the same semanting as the existing while() loop does and the compiler will understand that 'taddr' will be initialized at least once. Suggested-by: Matheus K. Ferst Resolves: https://gitlab.com/qemu-project/qemu/-/issues/573 Signed-off-by: Daniel Henrique Barboza Message-Id: <20220127122234.842145-2-danielhb413@gmail.com> Signed-off-by: C=C3=A9dric Le Goater --- hw/pci-host/pnv_phb3.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index a757f1a58ec8..aafd46b635e8 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -792,7 +792,9 @@ static void pnv_phb3_translate_tve(PnvPhb3DMASpace *ds,= hwaddr addr, sh =3D tbl_shift * lev + tce_shift; =20 /* TODO: Multi-level untested */ - while ((lev--) >=3D 0) { + do { + lev--; + /* Grab the TCE address */ taddr =3D base | (((addr >> sh) & ((1ul << tbl_shift) - 1)) <<= 3); if (dma_memory_read(&address_space_memory, taddr, &tce, @@ -813,7 +815,7 @@ static void pnv_phb3_translate_tve(PnvPhb3DMASpace *ds,= hwaddr addr, } sh -=3D tbl_shift; base =3D tce & ~0xfffull; - } + } while (lev >=3D 0); =20 /* We exit the loop with TCE being the final TCE */ if ((is_write & !(tce & 2)) || ((!is_write) && !(tce & 1))) { --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 31 Jan 2022 11:08:21 +0000 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 20VAwX6X45744440 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 31 Jan 2022 10:58:33 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C21AA4207B; Mon, 31 Jan 2022 11:08:19 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6279C4207C; Mon, 31 Jan 2022 11:08:19 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av24.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:19 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 72C48220149; Mon, 31 Jan 2022 12:08:18 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 06/41] ppc/pnv: use a do-while() loop in pnv_phb4_translate_tve() Date: Mon, 31 Jan 2022 12:07:36 +0100 Message-Id: <20220131110811.619053-7-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 4HpIhlw-Y3uVH--fXLbz9kySbz-G85qW X-Proofpoint-ORIG-GUID: BRof-b9T_BxtfC19BLtKRr9UqBPrik_F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1034 impostorscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=838 priorityscore=1501 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Daniel Henrique Barboza , Richard Henderson , Matheus Ferst , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643627601480100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza pnv_phb4_translate_tve() is quite similar to pnv_phb3_translate_tve(), and that includes the fact that 'taddr' can be considered uninitialized when throwing the "TCE access fault" error because, in theory, the loop that sets 'taddr' can be skippable due to 'lev' being an signed int. No one complained about this specific case yet, but since we took the time to handle the same situtation in pnv_phb3_translate_tve(), let's replicate it here as well. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Matheus Ferst Message-Id: <20220127122234.842145-3-danielhb413@gmail.com> Signed-off-by: C=C3=A9dric Le Goater --- hw/pci-host/pnv_phb4.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index ee56377c02be..e91249ef641d 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1267,7 +1267,9 @@ static void pnv_phb4_translate_tve(PnvPhb4DMASpace *d= s, hwaddr addr, /* TODO: Limit to support IO page sizes */ =20 /* TODO: Multi-level untested */ - while ((lev--) >=3D 0) { + do { + lev--; + /* Grab the TCE address */ taddr =3D base | (((addr >> sh) & ((1ul << tbl_shift) - 1)) <<= 3); if (dma_memory_read(&address_space_memory, taddr, &tce, @@ -1288,7 +1290,7 @@ static void pnv_phb4_translate_tve(PnvPhb4DMASpace *d= s, hwaddr addr, } sh -=3D tbl_shift; base =3D tce & ~0xfffull; - } + } while (lev >=3D 0); =20 /* We exit the loop with TCE being the final TCE */ if ((is_write & !(tce & 2)) || ((!is_write) && !(tce & 1))) { --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 31 Jan 2022 11:08:20 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2640811C04C; Mon, 31 Jan 2022 11:08:20 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:20 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 498F32201C1; Mon, 31 Jan 2022 12:08:19 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 07/41] ppc/xive: check return value of ldq_be_dma() Date: Mon, 31 Jan 2022 12:07:37 +0100 Message-Id: <20220131110811.619053-8-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: ezsarR_oLbr6VIwqq0co3N6sOILKFhXk X-Proofpoint-GUID: ezsarR_oLbr6VIwqq0co3N6sOILKFhXk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=823 suspectscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 malwarescore=0 impostorscore=0 phishscore=0 mlxscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643631884755100001 Content-Type: text/plain; charset="utf-8" The ldq_be_dma() routine was recently changed to return a result of the transaction. Use it when loading the virtual structure descriptors in the XIVE PowerNV model. Cc: Philippe Mathieu-Daud=C3=A9 Signed-off-by: C=C3=A9dric Le Goater Message-Id: <20220124081635.3672439-1-clg@kaod.org> Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index bb207514f2dd..621b20a03f5f 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -172,7 +172,12 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xi= ve, uint32_t type, =20 /* Get the page size of the indirect table. */ vsd_addr =3D vsd & VSD_ADDRESS_MASK; - ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFI= ED); + if (ldq_be_dma(&address_space_memory, vsd_addr, &vsd, + MEMTXATTRS_UNSPECIFIED)) { + xive_error(xive, "VST: failed to access %s entry %x @0x%" PRIx64, + info->name, idx, vsd_addr); + return 0; + } =20 if (!(vsd & VSD_ADDRESS_MASK)) { #ifdef XIVE_DEBUG @@ -195,8 +200,12 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xi= ve, uint32_t type, /* Load the VSD we are looking for, if not already done */ if (vsd_idx) { vsd_addr =3D vsd_addr + vsd_idx * XIVE_VSD_SIZE; - ldq_be_dma(&address_space_memory, vsd_addr, &vsd, - MEMTXATTRS_UNSPECIFIED); + if (ldq_be_dma(&address_space_memory, vsd_addr, &vsd, + MEMTXATTRS_UNSPECIFIED)) { + xive_error(xive, "VST: failed to access %s entry %x @0x%" + PRIx64, info->name, vsd_idx, vsd_addr); + return 0; + } =20 if (!(vsd & VSD_ADDRESS_MASK)) { #ifdef XIVE_DEBUG @@ -543,7 +552,12 @@ static uint64_t pnv_xive_vst_per_subpage(PnvXive *xive= , uint32_t type) =20 /* Get the page size of the indirect table. */ vsd_addr =3D vsd & VSD_ADDRESS_MASK; - ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFI= ED); + if (ldq_be_dma(&address_space_memory, vsd_addr, &vsd, + MEMTXATTRS_UNSPECIFIED)) { + xive_error(xive, "VST: failed to access %s entry @0x%" PRIx64, + info->name, vsd_addr); + return 0; + } =20 if (!(vsd & VSD_ADDRESS_MASK)) { #ifdef XIVE_DEBUG --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643631787943867.2589750305231; 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Mon, 31 Jan 2022 11:08:21 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7B920A406A; Mon, 31 Jan 2022 11:08:21 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 10FDFA4073; Mon, 31 Jan 2022 11:08:21 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:20 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 0EDFA220149; Mon, 31 Jan 2022 12:08:19 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 08/41] target/ppc: fix 'skip KVM' cond in cpu_interrupt_exittb() Date: Mon, 31 Jan 2022 12:07:38 +0100 Message-Id: <20220131110811.619053-9-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 1GvU6uQoFpVNBxCy2tqtl9nokJlsdclP X-Proofpoint-ORIG-GUID: YXwNwpVHF6zEiHzQg0LOg0nRSqoMW7Mo Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 bulkscore=0 adultscore=0 impostorscore=0 mlxlogscore=945 malwarescore=0 phishscore=0 suspectscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Fabiano Rosas , Daniel Henrique Barboza , Richard Henderson , Greg Kurz , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643631790246100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza cpu_interrupt_exittb() was introduced by commit 044897ef4a22 ("target/ppc: Fix system lockups caused by interrupt_request state corruption") as a way to wrap cpu_interrupt() helper in BQL. After that, commit 6d38666a8931 ("ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVM") added a condition to skip this interrupt if we're running with KVM. Problem is that the change made by the above commit, testing for !kvm_enabled() at the start of cpu_interrupt_exittb(): static inline void cpu_interrupt_exittb(CPUState *cs) { if (!kvm_enabled()) { return; } (... do cpu_interrupt(cs, CPU_INTERRUPT_EXITTB) ...) is doing the opposite of what it intended to do. This will return immediately if not kvm_enabled(), i.e. it's a emulated CPU, and if kvm_enabled() it will proceed to fire CPU_INTERRUPT_EXITTB. Fix the 'skip KVM' condition so the function is a no-op when kvm_enabled(). CC: Greg Kurz Resolves: https://gitlab.com/qemu-project/qemu/-/issues/809 Fixes: 6d38666a8931 ("ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with K= VM") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Fabiano Rosas Reviewed-by: Greg Kurz Message-Id: <20220121160841.9102-1-danielhb413@gmail.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/helper_regs.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 8671b7bb691f..7dca585dddeb 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -201,7 +201,11 @@ void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulo= ng *pc, =20 void cpu_interrupt_exittb(CPUState *cs) { - if (!kvm_enabled()) { + /* + * We don't need to worry about translation blocks + * when running with KVM. + */ + if (kvm_enabled()) { return; } =20 --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 31 Jan 2022 11:08:24 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 20VB8Mqv44892422 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 31 Jan 2022 11:08:22 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 28B1CAE058; Mon, 31 Jan 2022 11:08:22 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C9625AE051; Mon, 31 Jan 2022 11:08:21 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av26.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:21 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id ED4692201C1; Mon, 31 Jan 2022 12:08:20 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 09/41] spapr.c: check bus != NULL in spapr_get_fw_dev_path() Date: Mon, 31 Jan 2022 12:07:39 +0100 Message-Id: <20220131110811.619053-10-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: n-yBrLazQJAcKC2nYP3CF8vfDdPxoXVq X-Proofpoint-ORIG-GUID: C48WjND4Nw9L4sxJays9Y3hzF0-72ya_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1034 priorityscore=1501 mlxlogscore=588 impostorscore=0 mlxscore=0 spamscore=0 adultscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Daniel Henrique Barboza , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643630312266100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza spapr_get_fw_dev_path() is an impl of FWPathProviderClass::get_dev_path(). This interface is used by hw/core/qdev-fw.c via fw_path_provider_try_get_dev_path() in two functions: - static char *qdev_get_fw_dev_path_from_handler(), which is used only in qdev_get_fw_dev_path_helper() and it's guarded by "if (dev && dev->parent_bus)"; - char *qdev_get_own_fw_dev_path_from_handler(), which is used in softmmu/bootdevice.c in get_boot_device_path() like this: if (dev) { d =3D qdev_get_own_fw_dev_path_from_handler(dev->parent_bus, dev); This means that, when called via softmmu/bootdevice.c, there's no check of 'dev->parent_bus' being not NULL. The result is that the "BusState *bus" arg of spapr_get_fw_dev_path() can potentially be NULL and if, at the same time, "SCSIDevice *d" is not NULL, we'll hit this line: void *spapr =3D CAST(void, bus->parent, "spapr-vscsi"); And we'll SIGINT because 'bus' is NULL and we're accessing bus->parent. Adding a simple 'bus !=3D NULL' check to guard the instances where we access 'bus->parent' can avoid this altogether. Signed-off-by: Daniel Henrique Barboza Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220121213852.30243-1-danielhb413@gmail.com> Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/spapr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 72f5dce751ee..3d6ec309dd21 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3053,7 +3053,7 @@ static char *spapr_get_fw_dev_path(FWPathProvider *p,= BusState *bus, VHostSCSICommon *vsc =3D CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_CO= MMON); PCIDevice *pcidev =3D CAST(PCIDevice, dev, TYPE_PCI_DEVICE); =20 - if (d) { + if (d && bus) { void *spapr =3D CAST(void, bus->parent, "spapr-vscsi"); VirtIOSCSI *virtio =3D CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_S= CSI); USBDevice *usb =3D CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164363017966691.76247120659843; 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Mon, 31 Jan 2022 11:08:22 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:22 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id B43FE220149; Mon, 31 Jan 2022 12:08:21 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 10/41] target/ppc: Fix test on mmu_model in hreg_compute_hflags_value() Date: Mon, 31 Jan 2022 12:07:40 +0100 Message-Id: <20220131110811.619053-11-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: -P8_P0SX5Z_CBIQxdNz861Xh5Pz7YBDV X-Proofpoint-GUID: -P8_P0SX5Z_CBIQxdNz861Xh5Pz7YBDV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 suspectscore=0 phishscore=0 impostorscore=0 malwarescore=0 mlxlogscore=531 bulkscore=0 adultscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643630180912100007 Content-Type: text/plain; charset="utf-8" POWERPC_MMU_BOOKE is not a mask and should not be tested with a bitwise AND operator. It went unnoticed because it only impacts the 601 CPU implementation for which we don't have a known firmware image. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson Message-Id: <20220124081609.3672341-1-clg@kaod.org> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/helper_regs.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 7dca585dddeb..5b12cb03c961 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -156,7 +156,8 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *= env) */ unsigned immu_idx, dmmu_idx; dmmu_idx =3D msr & (1 << MSR_PR) ? 0 : 1; - if (env->mmu_model & POWERPC_MMU_BOOKE) { + if (env->mmu_model =3D=3D POWERPC_MMU_BOOKE || + env->mmu_model =3D=3D POWERPC_MMU_BOOKE206) { dmmu_idx |=3D msr & (1 << MSR_GS) ? 4 : 0; immu_idx =3D dmmu_idx; immu_idx |=3D msr & (1 << MSR_IS) ? 2 : 0; @@ -237,7 +238,8 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value= , int alter_hv) ((value >> MSR_DR) & 1) !=3D msr_dr) { cpu_interrupt_exittb(cs); } - if ((env->mmu_model & POWERPC_MMU_BOOKE) && + if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE || + env->mmu_model =3D=3D POWERPC_MMU_BOOKE206) && ((value >> MSR_GS) & 1) !=3D msr_gs) { cpu_interrupt_exittb(cs); } --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643629112083270.6860326946568; Mon, 31 Jan 2022 03:38:32 -0800 (PST) Received: from localhost ([::1]:60136 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEV0x-0002I9-CC for importer@patchew.org; Mon, 31 Jan 2022 06:38:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34174) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYf-000611-7C; Mon, 31 Jan 2022 06:09:19 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:31894 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYb-000557-Of; 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Mon, 31 Jan 2022 11:08:27 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 20VAwbn340829420 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 31 Jan 2022 10:58:37 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EEBDCA4071; Mon, 31 Jan 2022 11:08:23 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 85869A406A; Mon, 31 Jan 2022 11:08:23 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:23 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 7BD072201C1; Mon, 31 Jan 2022 12:08:22 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 11/41] target/ppc: Put do_rfi under a TCG-only block Date: Mon, 31 Jan 2022 12:07:41 +0100 Message-Id: <20220131110811.619053-12-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: fMS3gLoqyYeXfDkg6fhOjf5G5Boz9tzC X-Proofpoint-ORIG-GUID: TfKfP6SHFc-G2pH9lhTjQ0NwoXG1qIox X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 clxscore=1034 priorityscore=1501 bulkscore=0 spamscore=0 mlxlogscore=524 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.158.5; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, KHOP_HELO_FCRDNS=0.369, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Fabiano Rosas , Daniel Henrique Barboza , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643629114404100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas The --disable-tcg build broke when do_rfi stopped being inlined. Fixes: 62e79ef914 ("target/ppc: Remove static inline") Signed-off-by: Fabiano Rosas Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Message-Id: <20220124191547.1008391-1-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 980f62fd7964..883fb13cfef9 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1155,7 +1155,6 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_= t insn) (env->spr[SPR_PSSCR] & PSSCR_EC); } #endif /* defined(TARGET_PPC64) */ -#endif /* CONFIG_TCG */ =20 static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr) { @@ -1192,7 +1191,6 @@ static void do_rfi(CPUPPCState *env, target_ulong nip= , target_ulong msr) check_tlb_flush(env, false); } =20 -#ifdef CONFIG_TCG void helper_rfi(CPUPPCState *env) { do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful); --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164363001131270.94734879046723; Mon, 31 Jan 2022 03:53:31 -0800 (PST) Received: from localhost ([::1]:59384 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEVFS-0004N0-II for importer@patchew.org; Mon, 31 Jan 2022 06:53:30 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34378) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYk-00064w-7f; Mon, 31 Jan 2022 06:09:27 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:44838 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYe-00054y-2O; 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Mon, 31 Jan 2022 11:08:24 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A4F4B4C059; Mon, 31 Jan 2022 11:08:24 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 505974C044; Mon, 31 Jan 2022 11:08:24 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av22.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:24 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 6FB47220149; Mon, 31 Jan 2022 12:08:23 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 12/41] hw/ppc/vof: Add missing includes Date: Mon, 31 Jan 2022 12:07:42 +0100 Message-Id: <20220131110811.619053-13-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: zr-YyPlolfH7LsaY6d-nmAh1KW6OihgG X-Proofpoint-ORIG-GUID: zr-YyPlolfH7LsaY6d-nmAh1KW6OihgG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 mlxscore=0 impostorscore=0 clxscore=1034 phishscore=0 malwarescore=0 adultscore=0 bulkscore=0 spamscore=0 mlxlogscore=773 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.158.5; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, KHOP_HELO_FCRDNS=0.369, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643630013543100003 Content-Type: text/plain; charset="utf-8" From: Philippe Mathieu-Daud=C3=A9 vof.h requires "qom/object.h" for DECLARE_CLASS_CHECKERS(), "exec/memory.h" for address_space_read/write(), "exec/address-spaces.h" for address_space_memory and more importantly "cpu.h" for target_ulong. vof.c doesn't need "exec/ram_addr.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220122003104.84391-1-f4bug@amsat.org> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/vof.h | 5 +++++ hw/ppc/vof.c | 1 - 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/include/hw/ppc/vof.h b/include/hw/ppc/vof.h index 97fdef758bf2..f8c0effcaf88 100644 --- a/include/hw/ppc/vof.h +++ b/include/hw/ppc/vof.h @@ -6,6 +6,11 @@ #ifndef HW_VOF_H #define HW_VOF_H =20 +#include "qom/object.h" +#include "exec/address-spaces.h" +#include "exec/memory.h" +#include "cpu.h" + typedef struct Vof { uint64_t top_addr; /* copied from rma_size */ GArray *claimed; /* array of SpaprOfClaimed */ diff --git a/hw/ppc/vof.c b/hw/ppc/vof.c index 73adc44ec212..2b63a6287561 100644 --- a/hw/ppc/vof.c +++ b/hw/ppc/vof.c @@ -16,7 +16,6 @@ #include "qemu/units.h" #include "qemu/log.h" #include "qapi/error.h" -#include "exec/ram_addr.h" #include "exec/address-spaces.h" #include "hw/ppc/vof.h" #include "hw/ppc/fdt.h" --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 31 Jan 2022 11:08:27 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06avi18878370.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 20VB8PM447382826 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 31 Jan 2022 11:08:25 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AAAB9AE051; Mon, 31 Jan 2022 11:08:25 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 42307AE05A; Mon, 31 Jan 2022 11:08:25 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av26.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:25 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 3FC0D2201C1; Mon, 31 Jan 2022 12:08:24 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 13/41] ppc/ppc405: Fix TLB flushing Date: Mon, 31 Jan 2022 12:07:43 +0100 Message-Id: <20220131110811.619053-14-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 4uv9Df0UdncPyHVPk59hPkRmZbOaP1Qz X-Proofpoint-ORIG-GUID: nJ7fQuRGlw0zCYoz96t49TEw2ywlN_Nv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1034 impostorscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=900 priorityscore=1501 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Fabiano Rosas , Richard Henderson , Christophe Leroy , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643630034338100001 Content-Type: text/plain; charset="utf-8" Commit cd0c6f473532 did not take into account 405 CPUs when adding support to batching of TCG tlb flushes. Set the TLB_NEED_LOCAL_FLUSH flag when the SPR_40x_PID is set or a TLB updated. Cc: Thomas Huth Cc: Christophe Leroy Cc: Fabiano Rosas Reviewed-by: Fabiano Rosas Fixes: cd0c6f473532 ("ppc: Do some batching of TCG tlb flushes") Signed-off-by: C=C3=A9dric Le Goater Message-Id: <20220113180352.1234512-1-clg@kaod.org> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/helper.h | 1 + target/ppc/mmu_helper.c | 12 +++++++++++- target/ppc/translate.c | 2 +- 3 files changed, 13 insertions(+), 2 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index d318837ea5cc..bdbbd5e1d90f 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -707,6 +707,7 @@ DEF_HELPER_FLAGS_1(load_40x_pit, TCG_CALL_NO_RWG, tl, e= nv) DEF_HELPER_FLAGS_2(store_40x_pit, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(store_40x_tcr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(store_40x_tsr, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_2(store_40x_pid, void, env, tl) DEF_HELPER_2(store_40x_dbcr0, void, env, tl) DEF_HELPER_2(store_40x_sler, void, env, tl) DEF_HELPER_FLAGS_2(store_booke_tcr, TCG_CALL_NO_RWG, void, env, tl) diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 59df6952aea1..a2a52a12c3a4 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -664,6 +664,14 @@ static inline int booke_page_size_to_tlb(target_ulong = page_size) #define PPC4XX_TLBLO_ATTR_MASK 0x000000FF #define PPC4XX_TLBLO_RPN_MASK 0xFFFFFC00 =20 +void helper_store_40x_pid(CPUPPCState *env, target_ulong val) +{ + if (env->spr[SPR_40x_PID] !=3D val) { + env->spr[SPR_40x_PID] =3D val; + env->tlb_need_flush |=3D TLB_NEED_LOCAL_FLUSH; + } +} + target_ulong helper_4xx_tlbre_hi(CPUPPCState *env, target_ulong entry) { ppcemb_tlb_t *tlb; @@ -681,7 +689,7 @@ target_ulong helper_4xx_tlbre_hi(CPUPPCState *env, targ= et_ulong entry) size =3D PPC4XX_TLBHI_SIZE_DEFAULT; } ret |=3D size << PPC4XX_TLBHI_SIZE_SHIFT; - env->spr[SPR_40x_PID] =3D tlb->PID; + helper_store_40x_pid(env, tlb->PID); return ret; } =20 @@ -794,6 +802,8 @@ void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong= entry, tlb->prot & PAGE_WRITE ? 'w' : '-', tlb->prot & PAGE_EXEC ? 'x' : '-', tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID); + + env->tlb_need_flush |=3D TLB_NEED_LOCAL_FLUSH; } =20 target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 9d2adc0caee0..d61c6f0e8f91 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -894,7 +894,7 @@ void spr_write_40x_pid(DisasContext *ctx, int sprn, int= gprn) { TCGv t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); - gen_store_spr(SPR_40x_PID, t0); + gen_helper_store_40x_pid(cpu_env, t0); tcg_temp_free(t0); } =20 --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643628289457315.0996575663107; Mon, 31 Jan 2022 03:24:49 -0800 (PST) Received: from localhost ([::1]:36696 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEUng-0002Di-IY for importer@patchew.org; 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Mon, 31 Jan 2022 12:08:25 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 14/41] target/ppc: 405: Rename MSR_POW to MSR_WE Date: Mon, 31 Jan 2022 12:07:44 +0100 Message-Id: <20220131110811.619053-15-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: tSSKnlV4wYNO23UWNL3FQBw3rEffSFL6 X-Proofpoint-ORIG-GUID: tSSKnlV4wYNO23UWNL3FQBw3rEffSFL6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 bulkscore=0 adultscore=0 impostorscore=0 mlxlogscore=470 malwarescore=0 phishscore=0 suspectscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , David Gibson , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643628291282100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Bit 13 is the Wait State Enable bit. Give it its proper name. As far as I can see we don't do anything with MSR_POW for the 405, so this change has no effect. Suggested-by: David Gibson Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220118184448.852996-2-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/cpu.h | 1 + target/ppc/cpu_init.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2560b70c5f10..66e13075c3df 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -327,6 +327,7 @@ typedef enum { #define MSR_S 22 /* Secure state = */ #define MSR_KEY 19 /* key bit on 603e = */ #define MSR_POW 18 /* Power management = */ +#define MSR_WE 18 /* Wait State Enable on 405 = */ #define MSR_TGPR 17 /* TGPR usage on 602/603 x = */ #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x = */ #define MSR_ILE 16 /* Interrupt little-endian mode = */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index e30e86fe9d04..e63705b1c6b2 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2535,7 +2535,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; - pcc->msr_mask =3D (1ull << MSR_POW) | + pcc->msr_mask =3D (1ull << MSR_WE) | (1ull << MSR_CE) | (1ull << MSR_EE) | (1ull << MSR_PR) | --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643631140153841.9280245746181; Mon, 31 Jan 2022 04:12:20 -0800 (PST) Received: from localhost ([::1]:57724 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEVXf-0006ZK-9j for importer@patchew.org; Mon, 31 Jan 2022 07:12:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34486) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYz-0006B4-R0; Mon, 31 Jan 2022 06:09:41 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:18256) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYx-00054a-Te; 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Mon, 31 Jan 2022 11:08:27 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 40A61AE055; Mon, 31 Jan 2022 11:08:27 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E1EDEAE045; Mon, 31 Jan 2022 11:08:26 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av26.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:26 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 0887C2201C1; Mon, 31 Jan 2022 12:08:25 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 15/41] target/ppc: 405: Add missing MSR_ME bit Date: Mon, 31 Jan 2022 12:07:45 +0100 Message-Id: <20220131110811.619053-16-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: laew-Es5NBRBemTT71vTKt6kgbWlJN5O X-Proofpoint-GUID: laew-Es5NBRBemTT71vTKt6kgbWlJN5O X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=796 lowpriorityscore=0 suspectscore=0 malwarescore=0 mlxscore=0 bulkscore=0 clxscore=1034 phishscore=0 impostorscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643631142643100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas The 405 MSR has the Machine Check Enable bit. We're making use of it when dispatching Machine Check, so add the bit to the msr_mask. Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220118184448.852996-3-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/cpu_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index e63705b1c6b2..23a13036b211 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2540,6 +2540,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data) (1ull << MSR_EE) | (1ull << MSR_PR) | (1ull << MSR_FP) | + (1ull << MSR_ME) | (1ull << MSR_DWE) | (1ull << MSR_DE) | (1ull << MSR_IR) | --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643629405601856.1809884769743; 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Mon, 31 Jan 2022 11:08:27 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:27 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id CCD94220149; Mon, 31 Jan 2022 12:08:26 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 16/41] target/ppc: Introduce powerpc_excp_40x Date: Mon, 31 Jan 2022 12:07:46 +0100 Message-Id: <20220131110811.619053-17-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 15NTA58HgDwXbP96YuCJjTg2k6TfMQFu X-Proofpoint-GUID: 15NTA58HgDwXbP96YuCJjTg2k6TfMQFu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 suspectscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 malwarescore=0 impostorscore=0 phishscore=0 mlxscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643629408671100003 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Introduce a new powerpc_excp function specific for 40x CPUs. This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Richard Henderson Message-Id: <20220118184448.852996-4-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 474 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 474 insertions(+) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 883fb13cfef9..5dc948aec2bb 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -392,6 +392,477 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu, check_tlb_flush(env, false); } =20 +static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) +{ + CPUState *cs =3D CPU(cpu); + CPUPPCState *env =3D &cpu->env; + int excp_model =3D env->excp_model; + target_ulong msr, new_msr, vector; + int srr0, srr1, lev =3D -1; + + if (excp <=3D POWERPC_EXCP_NONE || excp >=3D POWERPC_EXCP_NB) { + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); + } + + qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx + " =3D> %s (%d) error=3D%02x\n", env->nip, powerpc_excp_n= ame(excp), + excp, env->error_code); + + /* new srr1 value excluding must-be-zero bits */ + if (excp_model =3D=3D POWERPC_EXCP_BOOKE) { + msr =3D env->msr; + } else { + msr =3D env->msr & ~0x783f0000ULL; + } + + /* + * new interrupt handler msr preserves existing HV and ME unless + * explicitly overriden + */ + new_msr =3D env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); + + /* target registers */ + srr0 =3D SPR_SRR0; + srr1 =3D SPR_SRR1; + + /* + * check for special resume at 0x100 from doze/nap/sleep/winkle on + * P7/P8/P9 + */ + if (env->resume_as_sreset) { + excp =3D powerpc_reset_wakeup(cs, env, excp, &msr); + } + + /* + * Hypervisor emulation assistance interrupt only exists on server + * arch 2.05 server or later. We also don't want to generate it if + * we don't have HVB in msr_mask (PAPR mode). + */ + if (excp =3D=3D POWERPC_EXCP_HV_EMU +#if defined(TARGET_PPC64) + && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB)) +#endif /* defined(TARGET_PPC64) */ + + ) { + excp =3D POWERPC_EXCP_PROGRAM; + } + +#ifdef TARGET_PPC64 + /* + * SPEU and VPU share the same IVOR but they exist in different + * processors. SPEU is e500v1/2 only and VPU is e6500 only. + */ + if (excp_model =3D=3D POWERPC_EXCP_BOOKE && excp =3D=3D POWERPC_EXCP_V= PU) { + excp =3D POWERPC_EXCP_SPEU; + } +#endif + + vector =3D env->excp_vectors[excp]; + if (vector =3D=3D (target_ulong)-1ULL) { + cpu_abort(cs, "Raised an exception without defined vector %d\n", + excp); + } + + vector |=3D env->excp_prefix; + + switch (excp) { + case POWERPC_EXCP_CRITICAL: /* Critical input = */ + switch (excp_model) { + case POWERPC_EXCP_40x: + srr0 =3D SPR_40x_SRR2; + srr1 =3D SPR_40x_SRR3; + break; + case POWERPC_EXCP_BOOKE: + srr0 =3D SPR_BOOKE_CSRR0; + srr1 =3D SPR_BOOKE_CSRR1; + break; + case POWERPC_EXCP_G2: + break; + default: + goto excp_invalid; + } + break; + case POWERPC_EXCP_MCHECK: /* Machine check exception = */ + if (msr_me =3D=3D 0) { + /* + * Machine check exception is not enabled. Enter + * checkstop state. + */ + fprintf(stderr, "Machine check while not allowed. " + "Entering checkstop state\n"); + if (qemu_log_separate()) { + qemu_log("Machine check while not allowed. " + "Entering checkstop state\n"); + } + cs->halted =3D 1; + cpu_interrupt_exittb(cs); + } + if (env->msr_mask & MSR_HVB) { + /* + * ISA specifies HV, but can be delivered to guest with HV + * clear (e.g., see FWNMI in PAPR). + */ + new_msr |=3D (target_ulong)MSR_HVB; + } + + /* machine check exceptions don't have ME set */ + new_msr &=3D ~((target_ulong)1 << MSR_ME); + + /* XXX: should also have something loaded in DAR / DSISR */ + switch (excp_model) { + case POWERPC_EXCP_40x: + srr0 =3D SPR_40x_SRR2; + srr1 =3D SPR_40x_SRR3; + break; + case POWERPC_EXCP_BOOKE: + /* FIXME: choose one or the other based on CPU type */ + srr0 =3D SPR_BOOKE_MCSRR0; + srr1 =3D SPR_BOOKE_MCSRR1; + + env->spr[SPR_BOOKE_CSRR0] =3D env->nip; + env->spr[SPR_BOOKE_CSRR1] =3D msr; + break; + default: + break; + } + break; + case POWERPC_EXCP_DSI: /* Data storage exception = */ + trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); + break; + case POWERPC_EXCP_ISI: /* Instruction storage exception = */ + trace_ppc_excp_isi(msr, env->nip); + msr |=3D env->error_code; + break; + case POWERPC_EXCP_EXTERNAL: /* External input = */ + { + bool lpes0; + + cs =3D CPU(cpu); + + /* + * Exception targeting modifiers + * + * LPES0 is supported on POWER7/8/9 + * LPES1 is not supported (old iSeries mode) + * + * On anything else, we behave as if LPES0 is 1 + * (externals don't alter MSR:HV) + */ +#if defined(TARGET_PPC64) + if (excp_model =3D=3D POWERPC_EXCP_POWER7 || + excp_model =3D=3D POWERPC_EXCP_POWER8 || + excp_model =3D=3D POWERPC_EXCP_POWER9 || + excp_model =3D=3D POWERPC_EXCP_POWER10) { + lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); + } else +#endif /* defined(TARGET_PPC64) */ + { + lpes0 =3D true; + } + + if (!lpes0) { + new_msr |=3D (target_ulong)MSR_HVB; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); + srr0 =3D SPR_HSRR0; + srr1 =3D SPR_HSRR1; + } + if (env->mpic_proxy) { + /* IACK the IRQ on delivery */ + env->spr[SPR_BOOKE_EPR] =3D ldl_phys(cs->as, env->mpic_iack); + } + break; + } + case POWERPC_EXCP_ALIGN: /* Alignment exception = */ + /* Get rS/rD and rA from faulting opcode */ + /* + * Note: the opcode fields will not be set properly for a + * direct store load/store, but nobody cares as nobody + * actually uses direct store segments. + */ + env->spr[SPR_DSISR] |=3D (env->error_code & 0x03FF0000) >> 16; + break; + case POWERPC_EXCP_PROGRAM: /* Program exception = */ + switch (env->error_code & ~0xF) { + case POWERPC_EXCP_FP: + if ((msr_fe0 =3D=3D 0 && msr_fe1 =3D=3D 0) || msr_fp =3D=3D 0)= { + trace_ppc_excp_fp_ignore(); + cs->exception_index =3D POWERPC_EXCP_NONE; + env->error_code =3D 0; + return; + } + + /* + * FP exceptions always have NIP pointing to the faulting + * instruction, so always use store_next and claim we are + * precise in the MSR. + */ + msr |=3D 0x00100000; + env->spr[SPR_BOOKE_ESR] =3D ESR_FP; + break; + case POWERPC_EXCP_INVAL: + trace_ppc_excp_inval(env->nip); + msr |=3D 0x00080000; + env->spr[SPR_BOOKE_ESR] =3D ESR_PIL; + break; + case POWERPC_EXCP_PRIV: + msr |=3D 0x00040000; + env->spr[SPR_BOOKE_ESR] =3D ESR_PPR; + break; + case POWERPC_EXCP_TRAP: + msr |=3D 0x00020000; + env->spr[SPR_BOOKE_ESR] =3D ESR_PTR; + break; + default: + /* Should never occur */ + cpu_abort(cs, "Invalid program exception %d. Aborting\n", + env->error_code); + break; + } + break; + case POWERPC_EXCP_SYSCALL: /* System call exception = */ + lev =3D env->error_code; + + if ((lev =3D=3D 1) && cpu->vhyp) { + dump_hcall(env); + } else { + dump_syscall(env); + } + + /* + * We need to correct the NIP which in this case is supposed + * to point to the next instruction + */ + env->nip +=3D 4; + + /* "PAPR mode" built-in hypercall emulation */ + if ((lev =3D=3D 1) && cpu->vhyp) { + PPCVirtualHypervisorClass *vhc =3D + PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); + vhc->hypercall(cpu->vhyp, cpu); + return; + } + if (lev =3D=3D 1) { + new_msr |=3D (target_ulong)MSR_HVB; + } + break; + case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception = */ + lev =3D env->error_code; + dump_syscall(env); + env->nip +=3D 4; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_EE); + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); + + vector +=3D lev * 0x20; + + env->lr =3D env->nip; + env->ctr =3D msr; + break; + case POWERPC_EXCP_FPU: /* Floating-point unavailable exception = */ + case POWERPC_EXCP_APU: /* Auxiliary processor unavailable = */ + case POWERPC_EXCP_DECR: /* Decrementer exception = */ + break; + case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt = */ + /* FIT on 4xx */ + trace_ppc_excp_print("FIT"); + break; + case POWERPC_EXCP_WDT: /* Watchdog timer interrupt = */ + trace_ppc_excp_print("WDT"); + switch (excp_model) { + case POWERPC_EXCP_BOOKE: + srr0 =3D SPR_BOOKE_CSRR0; + srr1 =3D SPR_BOOKE_CSRR1; + break; + default: + break; + } + break; + case POWERPC_EXCP_DTLB: /* Data TLB error = */ + case POWERPC_EXCP_ITLB: /* Instruction TLB error = */ + break; + case POWERPC_EXCP_DEBUG: /* Debug interrupt = */ + if (env->flags & POWERPC_FLAG_DE) { + /* FIXME: choose one or the other based on CPU type */ + srr0 =3D SPR_BOOKE_DSRR0; + srr1 =3D SPR_BOOKE_DSRR1; + + env->spr[SPR_BOOKE_CSRR0] =3D env->nip; + env->spr[SPR_BOOKE_CSRR1] =3D msr; + + /* DBSR already modified by caller */ + } else { + cpu_abort(cs, "Debug exception triggered on unsupported model\= n"); + } + break; + case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/V= PU */ + env->spr[SPR_BOOKE_ESR] =3D ESR_SPV; + break; + case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt = */ + break; + case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt = */ + srr0 =3D SPR_BOOKE_CSRR0; + srr1 =3D SPR_BOOKE_CSRR1; + break; + case POWERPC_EXCP_RESET: /* System reset exception = */ + /* A power-saving exception sets ME, otherwise it is unchanged */ + if (msr_pow) { + /* indicate that we resumed from power save mode */ + msr |=3D 0x10000; + new_msr |=3D ((target_ulong)1 << MSR_ME); + } + if (env->msr_mask & MSR_HVB) { + /* + * ISA specifies HV, but can be delivered to guest with HV + * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU). + */ + new_msr |=3D (target_ulong)MSR_HVB; + } else { + if (msr_pow) { + cpu_abort(cs, "Trying to deliver power-saving system reset= " + "exception %d with no HV support\n", excp); + } + } + break; + case POWERPC_EXCP_DSEG: /* Data segment exception = */ + case POWERPC_EXCP_ISEG: /* Instruction segment exception = */ + case POWERPC_EXCP_TRACE: /* Trace exception = */ + break; + case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excepti= on */ + msr |=3D env->error_code; + /* fall through */ + case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception = */ + case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception = */ + case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception = */ + case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excepti= on */ + case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt = */ + case POWERPC_EXCP_HV_EMU: + case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization = */ + srr0 =3D SPR_HSRR0; + srr1 =3D SPR_HSRR1; + new_msr |=3D (target_ulong)MSR_HVB; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); + break; + case POWERPC_EXCP_VPU: /* Vector unavailable exception = */ + case POWERPC_EXCP_VSXU: /* VSX unavailable exception = */ + case POWERPC_EXCP_FU: /* Facility unavailable exception = */ +#ifdef TARGET_PPC64 + env->spr[SPR_FSCR] |=3D ((target_ulong)env->error_code << 56); +#endif + break; + case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Except= ion */ +#ifdef TARGET_PPC64 + env->spr[SPR_HFSCR] |=3D ((target_ulong)env->error_code << FSCR_IC= _POS); + srr0 =3D SPR_HSRR0; + srr1 =3D SPR_HSRR1; + new_msr |=3D (target_ulong)MSR_HVB; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); +#endif + break; + case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt = */ + trace_ppc_excp_print("PIT"); + break; + case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error = */ + case POWERPC_EXCP_DLTLB: /* Data load TLB miss = */ + case POWERPC_EXCP_DSTLB: /* Data store TLB miss = */ + switch (excp_model) { + case POWERPC_EXCP_602: + case POWERPC_EXCP_603: + case POWERPC_EXCP_G2: + /* Swap temporary saved registers with GPRs */ + if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { + new_msr |=3D (target_ulong)1 << MSR_TGPR; + hreg_swap_gpr_tgpr(env); + } + /* fall through */ + case POWERPC_EXCP_7x5: + ppc_excp_debug_sw_tlb(env, excp); + + msr |=3D env->crf[0] << 28; + msr |=3D env->error_code; /* key, D/I, S/L bits */ + /* Set way using a LRU mechanism */ + msr |=3D ((env->last_way + 1) & (env->nb_ways - 1)) << 17; + break; + default: + cpu_abort(cs, "Invalid TLB miss exception\n"); + break; + } + break; + case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt= */ + case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrup= t */ + case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt= */ + case POWERPC_EXCP_IO: /* IO error exception = */ + case POWERPC_EXCP_RUNM: /* Run mode exception = */ + case POWERPC_EXCP_EMUL: /* Emulation trap exception = */ + case POWERPC_EXCP_FPA: /* Floating-point assist exception = */ + case POWERPC_EXCP_DABR: /* Data address breakpoint = */ + case POWERPC_EXCP_IABR: /* Instruction address breakpoint = */ + case POWERPC_EXCP_SMI: /* System management interrupt = */ + case POWERPC_EXCP_THERM: /* Thermal interrupt = */ + case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt= */ + case POWERPC_EXCP_VPUA: /* Vector assist exception = */ + case POWERPC_EXCP_SOFTP: /* Soft patch exception = */ + case POWERPC_EXCP_MAINT: /* Maintenance exception = */ + case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint = */ + case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint = */ + cpu_abort(cs, "%s exception not implemented\n", + powerpc_excp_name(excp)); + break; + default: + excp_invalid: + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); + break; + } + + /* Sanity check */ + if (!(env->msr_mask & MSR_HVB)) { + if (new_msr & MSR_HVB) { + cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with " + "no HV support\n", excp); + } + if (srr0 =3D=3D SPR_HSRR0) { + cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with " + "no HV support\n", excp); + } + } + + /* + * Sort out endianness of interrupt, this differs depending on the + * CPU, the HV mode, etc... + */ + if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { + new_msr |=3D (target_ulong)1 << MSR_LE; + } + +#if defined(TARGET_PPC64) + if (excp_model =3D=3D POWERPC_EXCP_BOOKE) { + if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) { + /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */ + new_msr |=3D (target_ulong)1 << MSR_CM; + } else { + vector =3D (uint32_t)vector; + } + } else { + if (!msr_isf && !mmu_is_64bit(env->mmu_model)) { + vector =3D (uint32_t)vector; + } else { + new_msr |=3D (target_ulong)1 << MSR_SF; + } + } +#endif + + if (excp !=3D POWERPC_EXCP_SYSCALL_VECTORED) { + /* Save PC */ + env->spr[srr0] =3D env->nip; + + /* Save MSR */ + env->spr[srr1] =3D msr; + } + + /* This can update new_msr and vector if AIL applies */ + ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector); + + powerpc_set_excp_state(cpu, vector, new_msr); +} + /* * Note that this function should be greatly optimized when called * with a constant excp, from ppc_hw_interrupt @@ -872,6 +1343,9 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp) CPUPPCState *env =3D &cpu->env; =20 switch (env->excp_model) { + case POWERPC_EXCP_40x: + powerpc_excp_40x(cpu, excp); + break; default: powerpc_excp_legacy(cpu, excp); } --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643635178708671.3361330507689; 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Mon, 31 Jan 2022 11:08:28 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av23.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:28 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id B273B2201C1; Mon, 31 Jan 2022 12:08:27 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 17/41] target/ppc: Simplify powerpc_excp_40x Date: Mon, 31 Jan 2022 12:07:47 +0100 Message-Id: <20220131110811.619053-18-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: WgwgoMEC9La_HY-hEB2V7JR1ihrMEgb6 X-Proofpoint-GUID: WgwgoMEC9La_HY-hEB2V7JR1ihrMEgb6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=376 spamscore=0 lowpriorityscore=0 adultscore=0 clxscore=1034 priorityscore=1501 bulkscore=0 phishscore=0 suspectscore=0 malwarescore=0 mlxscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , David Gibson , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643635181170100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Differences from the generic powerpc_excp code: - Not BookE, so some MSR bits are cleared at interrupt dispatch; - No MSR_HV or MSR_LE; - No power saving states; - No Hypervisor Emulation Assistance; - Not 64 bits; - No System call vectored; - No Interrupts Little Endian; - No Alternate Interrupt Location. Exceptions used: POWERPC_EXCP_ALIGN POWERPC_EXCP_CRITICAL POWERPC_EXCP_DEBUG POWERPC_EXCP_DSI POWERPC_EXCP_DTLB POWERPC_EXCP_EXTERNAL POWERPC_EXCP_FIT POWERPC_EXCP_ISI POWERPC_EXCP_ITLB POWERPC_EXCP_MCHECK POWERPC_EXCP_PIT POWERPC_EXCP_PROGRAM POWERPC_EXCP_SYSCALL POWERPC_EXCP_WDT Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson Message-Id: <20220118184448.852996-5-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 205 ++------------------------------------- 1 file changed, 10 insertions(+), 195 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 5dc948aec2bb..341a765bd49d 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -409,54 +409,26 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int exc= p) excp, env->error_code); =20 /* new srr1 value excluding must-be-zero bits */ - if (excp_model =3D=3D POWERPC_EXCP_BOOKE) { - msr =3D env->msr; - } else { - msr =3D env->msr & ~0x783f0000ULL; - } + msr =3D env->msr & ~0x783f0000ULL; =20 /* - * new interrupt handler msr preserves existing HV and ME unless - * explicitly overriden + * new interrupt handler msr preserves existing ME unless + * explicitly overriden. */ - new_msr =3D env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); + new_msr =3D env->msr & (((target_ulong)1 << MSR_ME)); =20 /* target registers */ srr0 =3D SPR_SRR0; srr1 =3D SPR_SRR1; =20 - /* - * check for special resume at 0x100 from doze/nap/sleep/winkle on - * P7/P8/P9 - */ - if (env->resume_as_sreset) { - excp =3D powerpc_reset_wakeup(cs, env, excp, &msr); - } - /* * Hypervisor emulation assistance interrupt only exists on server - * arch 2.05 server or later. We also don't want to generate it if - * we don't have HVB in msr_mask (PAPR mode). + * arch 2.05 server or later. */ - if (excp =3D=3D POWERPC_EXCP_HV_EMU -#if defined(TARGET_PPC64) - && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB)) -#endif /* defined(TARGET_PPC64) */ - - ) { + if (excp =3D=3D POWERPC_EXCP_HV_EMU) { excp =3D POWERPC_EXCP_PROGRAM; } =20 -#ifdef TARGET_PPC64 - /* - * SPEU and VPU share the same IVOR but they exist in different - * processors. SPEU is e500v1/2 only and VPU is e6500 only. - */ - if (excp_model =3D=3D POWERPC_EXCP_BOOKE && excp =3D=3D POWERPC_EXCP_V= PU) { - excp =3D POWERPC_EXCP_SPEU; - } -#endif - vector =3D env->excp_vectors[excp]; if (vector =3D=3D (target_ulong)-1ULL) { cpu_abort(cs, "Raised an exception without defined vector %d\n", @@ -645,24 +617,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) new_msr |=3D (target_ulong)MSR_HVB; } break; - case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception = */ - lev =3D env->error_code; - dump_syscall(env); - env->nip +=3D 4; - new_msr |=3D env->msr & ((target_ulong)1 << MSR_EE); - new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); - - vector +=3D lev * 0x20; - - env->lr =3D env->nip; - env->ctr =3D msr; - break; - case POWERPC_EXCP_FPU: /* Floating-point unavailable exception = */ - case POWERPC_EXCP_APU: /* Auxiliary processor unavailable = */ - case POWERPC_EXCP_DECR: /* Decrementer exception = */ - break; case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt = */ - /* FIT on 4xx */ trace_ppc_excp_print("FIT"); break; case POWERPC_EXCP_WDT: /* Watchdog timer interrupt = */ @@ -693,119 +648,9 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int exc= p) cpu_abort(cs, "Debug exception triggered on unsupported model\= n"); } break; - case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/V= PU */ - env->spr[SPR_BOOKE_ESR] =3D ESR_SPV; - break; - case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt = */ - break; - case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt = */ - srr0 =3D SPR_BOOKE_CSRR0; - srr1 =3D SPR_BOOKE_CSRR1; - break; - case POWERPC_EXCP_RESET: /* System reset exception = */ - /* A power-saving exception sets ME, otherwise it is unchanged */ - if (msr_pow) { - /* indicate that we resumed from power save mode */ - msr |=3D 0x10000; - new_msr |=3D ((target_ulong)1 << MSR_ME); - } - if (env->msr_mask & MSR_HVB) { - /* - * ISA specifies HV, but can be delivered to guest with HV - * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU). - */ - new_msr |=3D (target_ulong)MSR_HVB; - } else { - if (msr_pow) { - cpu_abort(cs, "Trying to deliver power-saving system reset= " - "exception %d with no HV support\n", excp); - } - } - break; - case POWERPC_EXCP_DSEG: /* Data segment exception = */ - case POWERPC_EXCP_ISEG: /* Instruction segment exception = */ - case POWERPC_EXCP_TRACE: /* Trace exception = */ - break; - case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excepti= on */ - msr |=3D env->error_code; - /* fall through */ - case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception = */ - case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception = */ - case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception = */ - case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excepti= on */ - case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt = */ - case POWERPC_EXCP_HV_EMU: - case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization = */ - srr0 =3D SPR_HSRR0; - srr1 =3D SPR_HSRR1; - new_msr |=3D (target_ulong)MSR_HVB; - new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); - break; - case POWERPC_EXCP_VPU: /* Vector unavailable exception = */ - case POWERPC_EXCP_VSXU: /* VSX unavailable exception = */ - case POWERPC_EXCP_FU: /* Facility unavailable exception = */ -#ifdef TARGET_PPC64 - env->spr[SPR_FSCR] |=3D ((target_ulong)env->error_code << 56); -#endif - break; - case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Except= ion */ -#ifdef TARGET_PPC64 - env->spr[SPR_HFSCR] |=3D ((target_ulong)env->error_code << FSCR_IC= _POS); - srr0 =3D SPR_HSRR0; - srr1 =3D SPR_HSRR1; - new_msr |=3D (target_ulong)MSR_HVB; - new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); -#endif - break; case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt = */ trace_ppc_excp_print("PIT"); break; - case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error = */ - case POWERPC_EXCP_DLTLB: /* Data load TLB miss = */ - case POWERPC_EXCP_DSTLB: /* Data store TLB miss = */ - switch (excp_model) { - case POWERPC_EXCP_602: - case POWERPC_EXCP_603: - case POWERPC_EXCP_G2: - /* Swap temporary saved registers with GPRs */ - if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { - new_msr |=3D (target_ulong)1 << MSR_TGPR; - hreg_swap_gpr_tgpr(env); - } - /* fall through */ - case POWERPC_EXCP_7x5: - ppc_excp_debug_sw_tlb(env, excp); - - msr |=3D env->crf[0] << 28; - msr |=3D env->error_code; /* key, D/I, S/L bits */ - /* Set way using a LRU mechanism */ - msr |=3D ((env->last_way + 1) & (env->nb_ways - 1)) << 17; - break; - default: - cpu_abort(cs, "Invalid TLB miss exception\n"); - break; - } - break; - case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt= */ - case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrup= t */ - case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt= */ - case POWERPC_EXCP_IO: /* IO error exception = */ - case POWERPC_EXCP_RUNM: /* Run mode exception = */ - case POWERPC_EXCP_EMUL: /* Emulation trap exception = */ - case POWERPC_EXCP_FPA: /* Floating-point assist exception = */ - case POWERPC_EXCP_DABR: /* Data address breakpoint = */ - case POWERPC_EXCP_IABR: /* Instruction address breakpoint = */ - case POWERPC_EXCP_SMI: /* System management interrupt = */ - case POWERPC_EXCP_THERM: /* Thermal interrupt = */ - case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt= */ - case POWERPC_EXCP_VPUA: /* Vector assist exception = */ - case POWERPC_EXCP_SOFTP: /* Soft patch exception = */ - case POWERPC_EXCP_MAINT: /* Maintenance exception = */ - case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint = */ - case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint = */ - cpu_abort(cs, "%s exception not implemented\n", - powerpc_excp_name(excp)); - break; default: excp_invalid: cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); @@ -824,41 +669,11 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int exc= p) } } =20 - /* - * Sort out endianness of interrupt, this differs depending on the - * CPU, the HV mode, etc... - */ - if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { - new_msr |=3D (target_ulong)1 << MSR_LE; - } - -#if defined(TARGET_PPC64) - if (excp_model =3D=3D POWERPC_EXCP_BOOKE) { - if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) { - /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */ - new_msr |=3D (target_ulong)1 << MSR_CM; - } else { - vector =3D (uint32_t)vector; - } - } else { - if (!msr_isf && !mmu_is_64bit(env->mmu_model)) { - vector =3D (uint32_t)vector; - } else { - new_msr |=3D (target_ulong)1 << MSR_SF; - } - } -#endif - - if (excp !=3D POWERPC_EXCP_SYSCALL_VECTORED) { - /* Save PC */ - env->spr[srr0] =3D env->nip; - - /* Save MSR */ - env->spr[srr1] =3D msr; - } + /* Save PC */ + env->spr[srr0] =3D env->nip; =20 - /* This can update new_msr and vector if AIL applies */ - ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector); + /* Save MSR */ + env->spr[srr1] =3D msr; =20 powerpc_set_excp_state(cpu, vector, new_msr); } --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643630510224454.5120482431189; Mon, 31 Jan 2022 04:01:50 -0800 (PST) Received: from localhost ([::1]:47568 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEVNU-0007Fv-K1 for importer@patchew.org; Mon, 31 Jan 2022 07:01:48 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34282) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYh-00061e-IG; Mon, 31 Jan 2022 06:09:20 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:33092) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYd-000559-I9; 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Mon, 31 Jan 2022 11:08:30 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DA11E4206E; Mon, 31 Jan 2022 11:08:29 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7B04342075; Mon, 31 Jan 2022 11:08:29 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av24.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:29 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 8DD47220149; Mon, 31 Jan 2022 12:08:28 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 18/41] target/ppc: 405: Critical exceptions cleanup Date: Mon, 31 Jan 2022 12:07:48 +0100 Message-Id: <20220131110811.619053-19-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: tfXBkSoPuMDcJtu7JeEf9jAMFSlOip5M X-Proofpoint-ORIG-GUID: tfXBkSoPuMDcJtu7JeEf9jAMFSlOip5M X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 mlxlogscore=645 lowpriorityscore=0 malwarescore=0 mlxscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.158.5; envelope-from=clg@kaod.org; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , David Gibson , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643630512601100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas In powerpc_excp_40x the Critical exception is now for 405 only, so we can remove the BookE and G2 blocks. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson Reviewed-by: Richard Henderson Message-Id: <20220118184448.852996-6-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 341a765bd49d..aafc381eb0e6 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -439,20 +439,8 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) =20 switch (excp) { case POWERPC_EXCP_CRITICAL: /* Critical input = */ - switch (excp_model) { - case POWERPC_EXCP_40x: - srr0 =3D SPR_40x_SRR2; - srr1 =3D SPR_40x_SRR3; - break; - case POWERPC_EXCP_BOOKE: - srr0 =3D SPR_BOOKE_CSRR0; - srr1 =3D SPR_BOOKE_CSRR1; - break; - case POWERPC_EXCP_G2: - break; - default: - goto excp_invalid; - } + srr0 =3D SPR_40x_SRR2; + srr1 =3D SPR_40x_SRR3; break; case POWERPC_EXCP_MCHECK: /* Machine check exception = */ if (msr_me =3D=3D 0) { @@ -652,7 +640,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) trace_ppc_excp_print("PIT"); break; default: - excp_invalid: cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); break; } --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643628256078770.5884107196619; Mon, 31 Jan 2022 03:24:16 -0800 (PST) Received: from localhost ([::1]:33810 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEUn9-0000Dj-9t for importer@patchew.org; Mon, 31 Jan 2022 06:24:15 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34154) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYe-000610-NK; Mon, 31 Jan 2022 06:09:19 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:49870 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYb-00055J-Qb; Mon, 31 Jan 2022 06:09:16 -0500 Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 20VAtAg0027293; Mon, 31 Jan 2022 11:08:35 GMT Received: from ppma03fra.de.ibm.com (6b.4a.5195.ip4.static.sl-reverse.com [149.81.74.107]) by mx0b-001b2d01.pphosted.com with ESMTP id 3dwexp8eb4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 31 Jan 2022 11:08:35 +0000 Received: from pps.filterd (ppma03fra.de.ibm.com [127.0.0.1]) by ppma03fra.de.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 20VB2KmW018014; Mon, 31 Jan 2022 11:08:33 GMT Received: from b06avi18626390.portsmouth.uk.ibm.com (b06avi18626390.portsmouth.uk.ibm.com [9.149.26.192]) by ppma03fra.de.ibm.com with ESMTP id 3dvw799ugf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 31 Jan 2022 11:08:32 +0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 20VAwi9348497124 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 31 Jan 2022 10:58:44 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A3CC152071; Mon, 31 Jan 2022 11:08:30 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av21.portsmouth.uk.ibm.com (Postfix) with SMTP id 45E385206D; Mon, 31 Jan 2022 11:08:30 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 636EB2201C1; Mon, 31 Jan 2022 12:08:29 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 19/41] target/ppc: 405: Machine check exception cleanup Date: Mon, 31 Jan 2022 12:07:49 +0100 Message-Id: <20220131110811.619053-20-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: zJi7X48Kk5CytD8s5weJiesS7YCTdCRd X-Proofpoint-ORIG-GUID: zJi7X48Kk5CytD8s5weJiesS7YCTdCRd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 mlxscore=0 impostorscore=0 clxscore=1034 phishscore=0 malwarescore=0 adultscore=0 bulkscore=0 spamscore=0 mlxlogscore=667 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.158.5; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, KHOP_HELO_FCRDNS=0.369, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , David Gibson , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643628258195100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas powerpc_excp_40x applies only to the 405, so remove HV code and references to BookE. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson Message-Id: <20220118184448.852996-7-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 26 ++------------------------ 1 file changed, 2 insertions(+), 24 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index aafc381eb0e6..3894d366854d 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -457,34 +457,12 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int exc= p) cs->halted =3D 1; cpu_interrupt_exittb(cs); } - if (env->msr_mask & MSR_HVB) { - /* - * ISA specifies HV, but can be delivered to guest with HV - * clear (e.g., see FWNMI in PAPR). - */ - new_msr |=3D (target_ulong)MSR_HVB; - } =20 /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); =20 - /* XXX: should also have something loaded in DAR / DSISR */ - switch (excp_model) { - case POWERPC_EXCP_40x: - srr0 =3D SPR_40x_SRR2; - srr1 =3D SPR_40x_SRR3; - break; - case POWERPC_EXCP_BOOKE: - /* FIXME: choose one or the other based on CPU type */ - srr0 =3D SPR_BOOKE_MCSRR0; - srr1 =3D SPR_BOOKE_MCSRR1; - - env->spr[SPR_BOOKE_CSRR0] =3D env->nip; - env->spr[SPR_BOOKE_CSRR1] =3D msr; - break; - default: - break; - } + srr0 =3D SPR_40x_SRR2; + srr1 =3D SPR_40x_SRR3; break; case POWERPC_EXCP_DSI: /* Data storage exception = */ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643630851397175.4993263552177; Mon, 31 Jan 2022 04:07:31 -0800 (PST) Received: from localhost ([::1]:49552 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEVSy-0000Nw-60 for importer@patchew.org; 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Mon, 31 Jan 2022 12:08:30 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 20/41] target/ppc: 405: External exception cleanup Date: Mon, 31 Jan 2022 12:07:50 +0100 Message-Id: <20220131110811.619053-21-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 1To43vrVTOIi88SKp2SMWhya9f1SiNby X-Proofpoint-ORIG-GUID: 1To43vrVTOIi88SKp2SMWhya9f1SiNby X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 mlxlogscore=840 clxscore=1034 bulkscore=0 priorityscore=1501 adultscore=0 spamscore=0 suspectscore=0 mlxscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , David Gibson , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643630853836100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas 405 has no MSR_HV and EPR is BookE only so we can remove it all. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson Message-Id: <20220118184448.852996-8-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 37 ------------------------------------- 1 file changed, 37 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 3894d366854d..069288a5c861 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -472,44 +472,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) msr |=3D env->error_code; break; case POWERPC_EXCP_EXTERNAL: /* External input = */ - { - bool lpes0; - - cs =3D CPU(cpu); - - /* - * Exception targeting modifiers - * - * LPES0 is supported on POWER7/8/9 - * LPES1 is not supported (old iSeries mode) - * - * On anything else, we behave as if LPES0 is 1 - * (externals don't alter MSR:HV) - */ -#if defined(TARGET_PPC64) - if (excp_model =3D=3D POWERPC_EXCP_POWER7 || - excp_model =3D=3D POWERPC_EXCP_POWER8 || - excp_model =3D=3D POWERPC_EXCP_POWER9 || - excp_model =3D=3D POWERPC_EXCP_POWER10) { - lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); - } else -#endif /* defined(TARGET_PPC64) */ - { - lpes0 =3D true; - } - - if (!lpes0) { - new_msr |=3D (target_ulong)MSR_HVB; - new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); - srr0 =3D SPR_HSRR0; - srr1 =3D SPR_HSRR1; - } - if (env->mpic_proxy) { - /* IACK the IRQ on delivery */ - env->spr[SPR_BOOKE_EPR] =3D ldl_phys(cs->as, env->mpic_iack); - } break; - } case POWERPC_EXCP_ALIGN: /* Alignment exception = */ /* Get rS/rD and rA from faulting opcode */ /* --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643629100776177.34779076912844; Mon, 31 Jan 2022 03:38:20 -0800 (PST) Received: from localhost ([::1]:59158 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEV0m-0001dD-1S for importer@patchew.org; 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Mon, 31 Jan 2022 12:08:30 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 21/41] target/ppc: 405: System call exception cleanup Date: Mon, 31 Jan 2022 12:07:51 +0100 Message-Id: <20220131110811.619053-22-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: RXaOH4Gx1ngI8DQ7gilWnhNu66qBm_-N X-Proofpoint-ORIG-GUID: RXaOH4Gx1ngI8DQ7gilWnhNu66qBm_-N X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1034 impostorscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=534 priorityscore=1501 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643629102808100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas There's no sc 1. Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Richard Henderson Message-Id: <20220118184448.852996-9-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 21 ++------------------- 1 file changed, 2 insertions(+), 19 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 069288a5c861..1f915f607d8f 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -398,7 +398,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) CPUPPCState *env =3D &cpu->env; int excp_model =3D env->excp_model; target_ulong msr, new_msr, vector; - int srr0, srr1, lev =3D -1; + int srr0, srr1; =20 if (excp <=3D POWERPC_EXCP_NONE || excp >=3D POWERPC_EXCP_NB) { cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); @@ -521,30 +521,13 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int exc= p) } break; case POWERPC_EXCP_SYSCALL: /* System call exception = */ - lev =3D env->error_code; - - if ((lev =3D=3D 1) && cpu->vhyp) { - dump_hcall(env); - } else { - dump_syscall(env); - } + dump_syscall(env); =20 /* * We need to correct the NIP which in this case is supposed * to point to the next instruction */ env->nip +=3D 4; - - /* "PAPR mode" built-in hypercall emulation */ - if ((lev =3D=3D 1) && cpu->vhyp) { - PPCVirtualHypervisorClass *vhc =3D - PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); - vhc->hypercall(cpu->vhyp, cpu); - return; - } - if (lev =3D=3D 1) { - new_msr |=3D (target_ulong)MSR_HVB; - } break; case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt = */ trace_ppc_excp_print("FIT"); --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643629435812539.4577950940843; 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Mon, 31 Jan 2022 11:08:32 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id C6DB3220149; Mon, 31 Jan 2022 12:08:31 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 22/41] target/ppc: 405: Alignment exception cleanup Date: Mon, 31 Jan 2022 12:07:52 +0100 Message-Id: <20220131110811.619053-23-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: NcxjZilHIJdMOpdQeivyPi0WjShmnjH8 X-Proofpoint-GUID: NcxjZilHIJdMOpdQeivyPi0WjShmnjH8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 suspectscore=0 phishscore=0 impostorscore=0 malwarescore=0 mlxlogscore=861 bulkscore=0 adultscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643629437094100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas There is no DSISR in the 405. It uses DEAR which we already set earlier at ppc_cpu_do_unaligned_access. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 1f915f607d8f..55f6b0e98100 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -474,13 +474,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_EXTERNAL: /* External input = */ break; case POWERPC_EXCP_ALIGN: /* Alignment exception = */ - /* Get rS/rD and rA from faulting opcode */ - /* - * Note: the opcode fields will not be set properly for a - * direct store load/store, but nobody cares as nobody - * actually uses direct store segments. - */ - env->spr[SPR_DSISR] |=3D (env->error_code & 0x03FF0000) >> 16; break; case POWERPC_EXCP_PROGRAM: /* Program exception = */ switch (env->error_code & ~0xF) { --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 31 Jan 2022 11:08:33 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7B5B64206E; Mon, 31 Jan 2022 11:08:33 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av24.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:33 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 8CF4E2201C1; Mon, 31 Jan 2022 12:08:32 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 23/41] target/ppc: 405: Debug exception cleanup Date: Mon, 31 Jan 2022 12:07:53 +0100 Message-Id: <20220131110811.619053-24-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: AnYKU8BmwVtI1XmglDPDRZhWiPRvi208 X-Proofpoint-GUID: AnYKU8BmwVtI1XmglDPDRZhWiPRvi208 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 clxscore=1034 priorityscore=1501 phishscore=0 spamscore=0 lowpriorityscore=0 mlxlogscore=461 bulkscore=0 suspectscore=0 impostorscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.158.5; envelope-from=clg@kaod.org; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , David Gibson , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643629981598100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas The current Debug exception dispatch is the BookE one, so it is different from the 405. We effectively don't support the 405 Debug exception. This patch removes the BookE code and moves the DEBUG into the "not implemented" block. Note that there is in theory a functional change here since we now abort when a Debug exception happens. However, given how it was never implemented, I don't believe this to have ever been dispatched for the 405. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson Message-Id: <20220118184448.852996-11-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 55f6b0e98100..89fc40bb7366 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -539,23 +539,13 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int exc= p) case POWERPC_EXCP_DTLB: /* Data TLB error = */ case POWERPC_EXCP_ITLB: /* Instruction TLB error = */ break; - case POWERPC_EXCP_DEBUG: /* Debug interrupt = */ - if (env->flags & POWERPC_FLAG_DE) { - /* FIXME: choose one or the other based on CPU type */ - srr0 =3D SPR_BOOKE_DSRR0; - srr1 =3D SPR_BOOKE_DSRR1; - - env->spr[SPR_BOOKE_CSRR0] =3D env->nip; - env->spr[SPR_BOOKE_CSRR1] =3D msr; - - /* DBSR already modified by caller */ - } else { - cpu_abort(cs, "Debug exception triggered on unsupported model\= n"); - } - break; case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt = */ trace_ppc_excp_print("PIT"); break; + case POWERPC_EXCP_DEBUG: /* Debug interrupt = */ + cpu_abort(cs, "%s exception not implemented\n", + powerpc_excp_name(excp)); + break; default: cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); break; --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643631730206872.8442694306485; Mon, 31 Jan 2022 04:22:10 -0800 (PST) Received: from localhost ([::1]:42094 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEVhB-0007iR-5H for importer@patchew.org; Mon, 31 Jan 2022 07:22:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34534) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUZ0-0006BB-Re; Mon, 31 Jan 2022 06:09:41 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:1182) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYy-00055Z-2v; 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Mon, 31 Jan 2022 11:08:34 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9F02BAE045; Mon, 31 Jan 2022 11:08:34 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4C0AEAE051; Mon, 31 Jan 2022 11:08:34 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av26.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:34 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 6498B220149; Mon, 31 Jan 2022 12:08:33 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 24/41] target/ppc: 405: Data Storage exception cleanup Date: Mon, 31 Jan 2022 12:07:54 +0100 Message-Id: <20220131110811.619053-25-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: d2ZI07bItv3MtB7feOdkhe4QmWgPLKaV X-Proofpoint-ORIG-GUID: d2ZI07bItv3MtB7feOdkhe4QmWgPLKaV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1034 impostorscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=890 priorityscore=1501 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643631732205100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas The 405 has no DSISR or DAR, so convert the trace entry to use ESR and DEAR instead. Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater [ clg : - changed registers to ESR and DEAR. - updated commit log ] Message-Id: <20220118184448.852996-12-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 89fc40bb7366..deba12f4f367 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -465,7 +465,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) srr1 =3D SPR_40x_SRR3; break; case POWERPC_EXCP_DSI: /* Data storage exception = */ - trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); + trace_ppc_excp_dsi(env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); break; case POWERPC_EXCP_ISI: /* Instruction storage exception = */ trace_ppc_excp_isi(msr, env->nip); --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643629366369619.6377202206232; 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Mon, 31 Jan 2022 11:08:35 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av22.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:35 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 35B0F2201C1; Mon, 31 Jan 2022 12:08:34 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 25/41] target/ppc: 405: Instruction storage interrupt cleanup Date: Mon, 31 Jan 2022 12:07:55 +0100 Message-Id: <20220131110811.619053-26-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 1f-EbhADX3MqWj4xpqBGJoPBkvISmU1g X-Proofpoint-GUID: 1f-EbhADX3MqWj4xpqBGJoPBkvISmU1g X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 suspectscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1034 spamscore=0 mlxlogscore=677 malwarescore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.158.5; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, KHOP_HELO_FCRDNS=0.369, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643629368052100005 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas The 405 ISI does not set SRR1 with any exception syndrome bits, only a clean copy of the MSR. Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater [ clg : Fixed removal which was done in the wrong routine ] Message-Id: <20220118184448.852996-13-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index deba12f4f367..7d89bd0651d8 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -469,7 +469,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) break; case POWERPC_EXCP_ISI: /* Instruction storage exception = */ trace_ppc_excp_isi(msr, env->nip); - msr |=3D env->error_code; break; case POWERPC_EXCP_EXTERNAL: /* External input = */ break; --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643629133990962.7868711711807; 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Mon, 31 Jan 2022 11:08:35 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 0660D220149; Mon, 31 Jan 2022 12:08:34 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 26/41] target/ppc: 405: Program exception cleanup Date: Mon, 31 Jan 2022 12:07:56 +0100 Message-Id: <20220131110811.619053-27-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: MoOKWRw9dcs90Ug8zme_DISOy94Pw0Rg X-Proofpoint-ORIG-GUID: MoOKWRw9dcs90Ug8zme_DISOy94Pw0Rg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 clxscore=1034 priorityscore=1501 bulkscore=0 spamscore=0 mlxlogscore=817 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.158.5; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, KHOP_HELO_FCRDNS=0.369, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643629136217100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas The 405 Program Interrupt does not set SRR1 with any diagnostic bits, just a clean copy of the MSR. We're using the BookE Exception Syndrome Register which is different from the 405. Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater [ clg: restored SPR_40x_ESR settings ] Message-Id: <20220118184448.852996-14-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 7d89bd0651d8..b528457d9298 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -483,30 +483,19 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int exc= p) env->error_code =3D 0; return; } - - /* - * FP exceptions always have NIP pointing to the faulting - * instruction, so always use store_next and claim we are - * precise in the MSR. - */ - msr |=3D 0x00100000; - env->spr[SPR_BOOKE_ESR] =3D ESR_FP; + env->spr[SPR_40x_ESR] =3D ESR_FP; break; case POWERPC_EXCP_INVAL: trace_ppc_excp_inval(env->nip); - msr |=3D 0x00080000; - env->spr[SPR_BOOKE_ESR] =3D ESR_PIL; + env->spr[SPR_40x_ESR] =3D ESR_PIL; break; case POWERPC_EXCP_PRIV: - msr |=3D 0x00040000; - env->spr[SPR_BOOKE_ESR] =3D ESR_PPR; + env->spr[SPR_40x_ESR] =3D ESR_PPR; break; case POWERPC_EXCP_TRAP: - msr |=3D 0x00020000; - env->spr[SPR_BOOKE_ESR] =3D ESR_PTR; + env->spr[SPR_40x_ESR] =3D ESR_PTR; break; default: - /* Should never occur */ cpu_abort(cs, "Invalid program exception %d. Aborting\n", env->error_code); break; --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16436309916471001.484863246803; Mon, 31 Jan 2022 04:09:51 -0800 (PST) Received: from localhost ([::1]:54200 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEVVG-00043r-VH for importer@patchew.org; Mon, 31 Jan 2022 07:09:50 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34294) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYh-00062j-Rt; Mon, 31 Jan 2022 06:09:21 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:53958) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYd-00055x-NJ; Mon, 31 Jan 2022 06:09:19 -0500 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 20VAbx5j017184; Mon, 31 Jan 2022 11:08:42 GMT Received: from ppma04ams.nl.ibm.com (63.31.33a9.ip4.static.sl-reverse.com [169.51.49.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 3dx33wtjm9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 31 Jan 2022 11:08:41 +0000 Received: from pps.filterd (ppma04ams.nl.ibm.com [127.0.0.1]) by ppma04ams.nl.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 20VB2Bqd006678; Mon, 31 Jan 2022 11:08:39 GMT Received: from b06cxnps3074.portsmouth.uk.ibm.com (d06relay09.portsmouth.uk.ibm.com [9.149.109.194]) by ppma04ams.nl.ibm.com with ESMTP id 3dvw79afy7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 31 Jan 2022 11:08:39 +0000 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 20VB8bAf46465368 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 31 Jan 2022 11:08:37 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F21534207C; Mon, 31 Jan 2022 11:08:36 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9D00142078; Mon, 31 Jan 2022 11:08:36 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av24.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:36 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id C09DB2201C1; Mon, 31 Jan 2022 12:08:35 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 27/41] target/ppc: 405: Watchdog timer exception cleanup Date: Mon, 31 Jan 2022 12:07:57 +0100 Message-Id: <20220131110811.619053-28-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: bPV9Vgaegn3uxSKWwkqm0qltmly_GMMC X-Proofpoint-ORIG-GUID: bPV9Vgaegn3uxSKWwkqm0qltmly_GMMC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 bulkscore=0 adultscore=0 impostorscore=0 mlxlogscore=788 malwarescore=0 phishscore=0 suspectscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643630994208100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Remove references to BookE. Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220118184448.852996-15-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b528457d9298..c3ff798d9d39 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -396,7 +396,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; - int excp_model =3D env->excp_model; target_ulong msr, new_msr, vector; int srr0, srr1; =20 @@ -515,14 +514,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) break; case POWERPC_EXCP_WDT: /* Watchdog timer interrupt = */ trace_ppc_excp_print("WDT"); - switch (excp_model) { - case POWERPC_EXCP_BOOKE: - srr0 =3D SPR_BOOKE_CSRR0; - srr1 =3D SPR_BOOKE_CSRR1; - break; - default: - break; - } break; case POWERPC_EXCP_DTLB: /* Data TLB error = */ case POWERPC_EXCP_ITLB: /* Instruction TLB error = */ --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 31 Jan 2022 11:08:37 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 78110A4071; Mon, 31 Jan 2022 11:08:37 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:37 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 89D2B220149; Mon, 31 Jan 2022 12:08:36 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 28/41] target/ppc: Introduce powerpc_excp_books Date: Mon, 31 Jan 2022 12:07:58 +0100 Message-Id: <20220131110811.619053-29-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: hcyquZWoFji-OfXdtgP8OTWHfwulqYPu X-Proofpoint-ORIG-GUID: hcyquZWoFji-OfXdtgP8OTWHfwulqYPu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 bulkscore=0 adultscore=0 impostorscore=0 mlxlogscore=999 malwarescore=0 phishscore=0 suspectscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643632576361100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Introduce a new powerpc_excp function specific for BookS CPUs. This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220124184605.999353-2-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 478 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 478 insertions(+) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index c3ff798d9d39..a2a605f8f59e 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -551,6 +551,477 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int exc= p) powerpc_set_excp_state(cpu, vector, new_msr); } =20 +static void powerpc_excp_books(PowerPCCPU *cpu, int excp) +{ + CPUState *cs =3D CPU(cpu); + CPUPPCState *env =3D &cpu->env; + int excp_model =3D env->excp_model; + target_ulong msr, new_msr, vector; + int srr0, srr1, lev =3D -1; + + if (excp <=3D POWERPC_EXCP_NONE || excp >=3D POWERPC_EXCP_NB) { + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); + } + + qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx + " =3D> %s (%d) error=3D%02x\n", env->nip, powerpc_excp_n= ame(excp), + excp, env->error_code); + + /* new srr1 value excluding must-be-zero bits */ + if (excp_model =3D=3D POWERPC_EXCP_BOOKE) { + msr =3D env->msr; + } else { + msr =3D env->msr & ~0x783f0000ULL; + } + + /* + * new interrupt handler msr preserves existing HV and ME unless + * explicitly overriden + */ + new_msr =3D env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); + + /* target registers */ + srr0 =3D SPR_SRR0; + srr1 =3D SPR_SRR1; + + /* + * check for special resume at 0x100 from doze/nap/sleep/winkle on + * P7/P8/P9 + */ + if (env->resume_as_sreset) { + excp =3D powerpc_reset_wakeup(cs, env, excp, &msr); + } + + /* + * Hypervisor emulation assistance interrupt only exists on server + * arch 2.05 server or later. We also don't want to generate it if + * we don't have HVB in msr_mask (PAPR mode). + */ + if (excp =3D=3D POWERPC_EXCP_HV_EMU +#if defined(TARGET_PPC64) + && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB)) +#endif /* defined(TARGET_PPC64) */ + + ) { + excp =3D POWERPC_EXCP_PROGRAM; + } + +#ifdef TARGET_PPC64 + /* + * SPEU and VPU share the same IVOR but they exist in different + * processors. SPEU is e500v1/2 only and VPU is e6500 only. + */ + if (excp_model =3D=3D POWERPC_EXCP_BOOKE && excp =3D=3D POWERPC_EXCP_V= PU) { + excp =3D POWERPC_EXCP_SPEU; + } +#endif + + vector =3D env->excp_vectors[excp]; + if (vector =3D=3D (target_ulong)-1ULL) { + cpu_abort(cs, "Raised an exception without defined vector %d\n", + excp); + } + + vector |=3D env->excp_prefix; + + switch (excp) { + case POWERPC_EXCP_CRITICAL: /* Critical input = */ + switch (excp_model) { + case POWERPC_EXCP_40x: + srr0 =3D SPR_40x_SRR2; + srr1 =3D SPR_40x_SRR3; + break; + case POWERPC_EXCP_BOOKE: + srr0 =3D SPR_BOOKE_CSRR0; + srr1 =3D SPR_BOOKE_CSRR1; + break; + case POWERPC_EXCP_G2: + break; + default: + goto excp_invalid; + } + break; + case POWERPC_EXCP_MCHECK: /* Machine check exception = */ + if (msr_me =3D=3D 0) { + /* + * Machine check exception is not enabled. Enter + * checkstop state. + */ + fprintf(stderr, "Machine check while not allowed. " + "Entering checkstop state\n"); + if (qemu_log_separate()) { + qemu_log("Machine check while not allowed. " + "Entering checkstop state\n"); + } + cs->halted =3D 1; + cpu_interrupt_exittb(cs); + } + if (env->msr_mask & MSR_HVB) { + /* + * ISA specifies HV, but can be delivered to guest with HV + * clear (e.g., see FWNMI in PAPR). + */ + new_msr |=3D (target_ulong)MSR_HVB; + } + + /* machine check exceptions don't have ME set */ + new_msr &=3D ~((target_ulong)1 << MSR_ME); + + /* XXX: should also have something loaded in DAR / DSISR */ + switch (excp_model) { + case POWERPC_EXCP_40x: + srr0 =3D SPR_40x_SRR2; + srr1 =3D SPR_40x_SRR3; + break; + case POWERPC_EXCP_BOOKE: + /* FIXME: choose one or the other based on CPU type */ + srr0 =3D SPR_BOOKE_MCSRR0; + srr1 =3D SPR_BOOKE_MCSRR1; + + env->spr[SPR_BOOKE_CSRR0] =3D env->nip; + env->spr[SPR_BOOKE_CSRR1] =3D msr; + break; + default: + break; + } + break; + case POWERPC_EXCP_DSI: /* Data storage exception = */ + trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); + break; + case POWERPC_EXCP_ISI: /* Instruction storage exception = */ + trace_ppc_excp_isi(msr, env->nip); + msr |=3D env->error_code; + break; + case POWERPC_EXCP_EXTERNAL: /* External input = */ + { + bool lpes0; + + cs =3D CPU(cpu); + + /* + * Exception targeting modifiers + * + * LPES0 is supported on POWER7/8/9 + * LPES1 is not supported (old iSeries mode) + * + * On anything else, we behave as if LPES0 is 1 + * (externals don't alter MSR:HV) + */ +#if defined(TARGET_PPC64) + if (excp_model =3D=3D POWERPC_EXCP_POWER7 || + excp_model =3D=3D POWERPC_EXCP_POWER8 || + excp_model =3D=3D POWERPC_EXCP_POWER9 || + excp_model =3D=3D POWERPC_EXCP_POWER10) { + lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); + } else +#endif /* defined(TARGET_PPC64) */ + { + lpes0 =3D true; + } + + if (!lpes0) { + new_msr |=3D (target_ulong)MSR_HVB; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); + srr0 =3D SPR_HSRR0; + srr1 =3D SPR_HSRR1; + } + if (env->mpic_proxy) { + /* IACK the IRQ on delivery */ + env->spr[SPR_BOOKE_EPR] =3D ldl_phys(cs->as, env->mpic_iack); + } + break; + } + case POWERPC_EXCP_ALIGN: /* Alignment exception = */ + /* Get rS/rD and rA from faulting opcode */ + /* + * Note: the opcode fields will not be set properly for a + * direct store load/store, but nobody cares as nobody + * actually uses direct store segments. + */ + env->spr[SPR_DSISR] |=3D (env->error_code & 0x03FF0000) >> 16; + break; + case POWERPC_EXCP_PROGRAM: /* Program exception = */ + switch (env->error_code & ~0xF) { + case POWERPC_EXCP_FP: + if ((msr_fe0 =3D=3D 0 && msr_fe1 =3D=3D 0) || msr_fp =3D=3D 0)= { + trace_ppc_excp_fp_ignore(); + cs->exception_index =3D POWERPC_EXCP_NONE; + env->error_code =3D 0; + return; + } + + /* + * FP exceptions always have NIP pointing to the faulting + * instruction, so always use store_next and claim we are + * precise in the MSR. + */ + msr |=3D 0x00100000; + env->spr[SPR_BOOKE_ESR] =3D ESR_FP; + break; + case POWERPC_EXCP_INVAL: + trace_ppc_excp_inval(env->nip); + msr |=3D 0x00080000; + env->spr[SPR_BOOKE_ESR] =3D ESR_PIL; + break; + case POWERPC_EXCP_PRIV: + msr |=3D 0x00040000; + env->spr[SPR_BOOKE_ESR] =3D ESR_PPR; + break; + case POWERPC_EXCP_TRAP: + msr |=3D 0x00020000; + env->spr[SPR_BOOKE_ESR] =3D ESR_PTR; + break; + default: + /* Should never occur */ + cpu_abort(cs, "Invalid program exception %d. Aborting\n", + env->error_code); + break; + } + break; + case POWERPC_EXCP_SYSCALL: /* System call exception = */ + lev =3D env->error_code; + + if ((lev =3D=3D 1) && cpu->vhyp) { + dump_hcall(env); + } else { + dump_syscall(env); + } + + /* + * We need to correct the NIP which in this case is supposed + * to point to the next instruction + */ + env->nip +=3D 4; + + /* "PAPR mode" built-in hypercall emulation */ + if ((lev =3D=3D 1) && cpu->vhyp) { + PPCVirtualHypervisorClass *vhc =3D + PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); + vhc->hypercall(cpu->vhyp, cpu); + return; + } + if (lev =3D=3D 1) { + new_msr |=3D (target_ulong)MSR_HVB; + } + break; + case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception = */ + lev =3D env->error_code; + dump_syscall(env); + env->nip +=3D 4; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_EE); + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); + + vector +=3D lev * 0x20; + + env->lr =3D env->nip; + env->ctr =3D msr; + break; + case POWERPC_EXCP_FPU: /* Floating-point unavailable exception = */ + case POWERPC_EXCP_APU: /* Auxiliary processor unavailable = */ + case POWERPC_EXCP_DECR: /* Decrementer exception = */ + break; + case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt = */ + /* FIT on 4xx */ + trace_ppc_excp_print("FIT"); + break; + case POWERPC_EXCP_WDT: /* Watchdog timer interrupt = */ + trace_ppc_excp_print("WDT"); + switch (excp_model) { + case POWERPC_EXCP_BOOKE: + srr0 =3D SPR_BOOKE_CSRR0; + srr1 =3D SPR_BOOKE_CSRR1; + break; + default: + break; + } + break; + case POWERPC_EXCP_DTLB: /* Data TLB error = */ + case POWERPC_EXCP_ITLB: /* Instruction TLB error = */ + break; + case POWERPC_EXCP_DEBUG: /* Debug interrupt = */ + if (env->flags & POWERPC_FLAG_DE) { + /* FIXME: choose one or the other based on CPU type */ + srr0 =3D SPR_BOOKE_DSRR0; + srr1 =3D SPR_BOOKE_DSRR1; + + env->spr[SPR_BOOKE_CSRR0] =3D env->nip; + env->spr[SPR_BOOKE_CSRR1] =3D msr; + + /* DBSR already modified by caller */ + } else { + cpu_abort(cs, "Debug exception triggered on unsupported model\= n"); + } + break; + case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/V= PU */ + env->spr[SPR_BOOKE_ESR] =3D ESR_SPV; + break; + case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt = */ + break; + case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt = */ + srr0 =3D SPR_BOOKE_CSRR0; + srr1 =3D SPR_BOOKE_CSRR1; + break; + case POWERPC_EXCP_RESET: /* System reset exception = */ + /* A power-saving exception sets ME, otherwise it is unchanged */ + if (msr_pow) { + /* indicate that we resumed from power save mode */ + msr |=3D 0x10000; + new_msr |=3D ((target_ulong)1 << MSR_ME); + } + if (env->msr_mask & MSR_HVB) { + /* + * ISA specifies HV, but can be delivered to guest with HV + * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU). + */ + new_msr |=3D (target_ulong)MSR_HVB; + } else { + if (msr_pow) { + cpu_abort(cs, "Trying to deliver power-saving system reset= " + "exception %d with no HV support\n", excp); + } + } + break; + case POWERPC_EXCP_DSEG: /* Data segment exception = */ + case POWERPC_EXCP_ISEG: /* Instruction segment exception = */ + case POWERPC_EXCP_TRACE: /* Trace exception = */ + break; + case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excepti= on */ + msr |=3D env->error_code; + /* fall through */ + case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception = */ + case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception = */ + case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception = */ + case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excepti= on */ + case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt = */ + case POWERPC_EXCP_HV_EMU: + case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization = */ + srr0 =3D SPR_HSRR0; + srr1 =3D SPR_HSRR1; + new_msr |=3D (target_ulong)MSR_HVB; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); + break; + case POWERPC_EXCP_VPU: /* Vector unavailable exception = */ + case POWERPC_EXCP_VSXU: /* VSX unavailable exception = */ + case POWERPC_EXCP_FU: /* Facility unavailable exception = */ +#ifdef TARGET_PPC64 + env->spr[SPR_FSCR] |=3D ((target_ulong)env->error_code << 56); +#endif + break; + case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Except= ion */ +#ifdef TARGET_PPC64 + env->spr[SPR_HFSCR] |=3D ((target_ulong)env->error_code << FSCR_IC= _POS); + srr0 =3D SPR_HSRR0; + srr1 =3D SPR_HSRR1; + new_msr |=3D (target_ulong)MSR_HVB; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); +#endif + break; + case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt = */ + trace_ppc_excp_print("PIT"); + break; + case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error = */ + case POWERPC_EXCP_DLTLB: /* Data load TLB miss = */ + case POWERPC_EXCP_DSTLB: /* Data store TLB miss = */ + switch (excp_model) { + case POWERPC_EXCP_602: + case POWERPC_EXCP_603: + case POWERPC_EXCP_G2: + /* Swap temporary saved registers with GPRs */ + if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { + new_msr |=3D (target_ulong)1 << MSR_TGPR; + hreg_swap_gpr_tgpr(env); + } + /* fall through */ + case POWERPC_EXCP_7x5: + ppc_excp_debug_sw_tlb(env, excp); + + msr |=3D env->crf[0] << 28; + msr |=3D env->error_code; /* key, D/I, S/L bits */ + /* Set way using a LRU mechanism */ + msr |=3D ((env->last_way + 1) & (env->nb_ways - 1)) << 17; + break; + default: + cpu_abort(cs, "Invalid TLB miss exception\n"); + break; + } + break; + case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt= */ + case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrup= t */ + case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt= */ + case POWERPC_EXCP_IO: /* IO error exception = */ + case POWERPC_EXCP_RUNM: /* Run mode exception = */ + case POWERPC_EXCP_EMUL: /* Emulation trap exception = */ + case POWERPC_EXCP_FPA: /* Floating-point assist exception = */ + case POWERPC_EXCP_DABR: /* Data address breakpoint = */ + case POWERPC_EXCP_IABR: /* Instruction address breakpoint = */ + case POWERPC_EXCP_SMI: /* System management interrupt = */ + case POWERPC_EXCP_THERM: /* Thermal interrupt = */ + case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt= */ + case POWERPC_EXCP_VPUA: /* Vector assist exception = */ + case POWERPC_EXCP_SOFTP: /* Soft patch exception = */ + case POWERPC_EXCP_MAINT: /* Maintenance exception = */ + case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint = */ + case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint = */ + cpu_abort(cs, "%s exception not implemented\n", + powerpc_excp_name(excp)); + break; + default: + excp_invalid: + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); + break; + } + + /* Sanity check */ + if (!(env->msr_mask & MSR_HVB)) { + if (new_msr & MSR_HVB) { + cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with " + "no HV support\n", excp); + } + if (srr0 =3D=3D SPR_HSRR0) { + cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with " + "no HV support\n", excp); + } + } + + /* + * Sort out endianness of interrupt, this differs depending on the + * CPU, the HV mode, etc... + */ + if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { + new_msr |=3D (target_ulong)1 << MSR_LE; + } + +#if defined(TARGET_PPC64) + if (excp_model =3D=3D POWERPC_EXCP_BOOKE) { + if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) { + /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */ + new_msr |=3D (target_ulong)1 << MSR_CM; + } else { + vector =3D (uint32_t)vector; + } + } else { + if (!msr_isf && !mmu_is_64bit(env->mmu_model)) { + vector =3D (uint32_t)vector; + } else { + new_msr |=3D (target_ulong)1 << MSR_SF; + } + } +#endif + + if (excp !=3D POWERPC_EXCP_SYSCALL_VECTORED) { + /* Save PC */ + env->spr[srr0] =3D env->nip; + + /* Save MSR */ + env->spr[srr1] =3D msr; + } + + /* This can update new_msr and vector if AIL applies */ + ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector); + + powerpc_set_excp_state(cpu, vector, new_msr); +} + /* * Note that this function should be greatly optimized when called * with a constant excp, from ppc_hw_interrupt @@ -1034,6 +1505,13 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_40x: powerpc_excp_40x(cpu, excp); break; + case POWERPC_EXCP_970: + case POWERPC_EXCP_POWER7: + case POWERPC_EXCP_POWER8: + case POWERPC_EXCP_POWER9: + case POWERPC_EXCP_POWER10: + powerpc_excp_books(cpu, excp); + break; default: powerpc_excp_legacy(cpu, excp); } --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643629697205628.5847666641637; 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Mon, 31 Jan 2022 11:08:38 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 62D722201C1; Mon, 31 Jan 2022 12:08:37 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 29/41] target/ppc: Simplify powerpc_excp_books Date: Mon, 31 Jan 2022 12:07:59 +0100 Message-Id: <20220131110811.619053-30-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: rfrxlTVVnyJrlkwm2oJfZ2hd3_GAhsLT X-Proofpoint-ORIG-GUID: rfrxlTVVnyJrlkwm2oJfZ2hd3_GAhsLT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1034 priorityscore=1501 adultscore=0 impostorscore=0 spamscore=0 mlxlogscore=637 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.158.5; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, KHOP_HELO_FCRDNS=0.369, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643629700392100003 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Differences from the generic powerpc_excp code: - Not BookE, so some MSR bits are cleared at interrupt dispatch; - Always uses HV_EMU if the CPU has MSR_HV; - Exceptions always delivered in 64 bit. Exceptions used: POWERPC_EXCP_ALIGN POWERPC_EXCP_DECR POWERPC_EXCP_DSEG POWERPC_EXCP_DSI POWERPC_EXCP_EXTERNAL POWERPC_EXCP_FPU POWERPC_EXCP_FU POWERPC_EXCP_HDECR POWERPC_EXCP_HDSI POWERPC_EXCP_HISI POWERPC_EXCP_HVIRT POWERPC_EXCP_HV_EMU POWERPC_EXCP_HV_FU POWERPC_EXCP_ISEG POWERPC_EXCP_ISI POWERPC_EXCP_MAINT POWERPC_EXCP_MCHECK POWERPC_EXCP_PERFM POWERPC_EXCP_PROGRAM POWERPC_EXCP_RESET POWERPC_EXCP_SDOOR_HV POWERPC_EXCP_SYSCALL POWERPC_EXCP_SYSCALL_VECTORED POWERPC_EXCP_THERM POWERPC_EXCP_TRACE POWERPC_EXCP_VPU POWERPC_EXCP_VPUA POWERPC_EXCP_VSXU POWERPC_EXCP_HV_MAINT POWERPC_EXCP_SDOOR (I added the two above that were not being considered. They used to be "Invalid exception". Now they become "Unimplemented exception" which is more accurate.) Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220124184605.999353-3-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 161 ++++----------------------------------- 1 file changed, 14 insertions(+), 147 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index a2a605f8f59e..161b207bc7b8 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -551,6 +551,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) powerpc_set_excp_state(cpu, vector, new_msr); } =20 +#ifdef TARGET_PPC64 static void powerpc_excp_books(PowerPCCPU *cpu, int excp) { CPUState *cs =3D CPU(cpu); @@ -568,11 +569,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int ex= cp) excp, env->error_code); =20 /* new srr1 value excluding must-be-zero bits */ - if (excp_model =3D=3D POWERPC_EXCP_BOOKE) { - msr =3D env->msr; - } else { - msr =3D env->msr & ~0x783f0000ULL; - } + msr =3D env->msr & ~0x783f0000ULL; =20 /* * new interrupt handler msr preserves existing HV and ME unless @@ -593,29 +590,13 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) } =20 /* - * Hypervisor emulation assistance interrupt only exists on server - * arch 2.05 server or later. We also don't want to generate it if - * we don't have HVB in msr_mask (PAPR mode). + * We don't want to generate a Hypervisor Emulation Assistance + * Interrupt if we don't have HVB in msr_mask (PAPR mode). */ - if (excp =3D=3D POWERPC_EXCP_HV_EMU -#if defined(TARGET_PPC64) - && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB)) -#endif /* defined(TARGET_PPC64) */ - - ) { + if (excp =3D=3D POWERPC_EXCP_HV_EMU && !(env->msr_mask & MSR_HVB)) { excp =3D POWERPC_EXCP_PROGRAM; } =20 -#ifdef TARGET_PPC64 - /* - * SPEU and VPU share the same IVOR but they exist in different - * processors. SPEU is e500v1/2 only and VPU is e6500 only. - */ - if (excp_model =3D=3D POWERPC_EXCP_BOOKE && excp =3D=3D POWERPC_EXCP_V= PU) { - excp =3D POWERPC_EXCP_SPEU; - } -#endif - vector =3D env->excp_vectors[excp]; if (vector =3D=3D (target_ulong)-1ULL) { cpu_abort(cs, "Raised an exception without defined vector %d\n", @@ -625,22 +606,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int ex= cp) vector |=3D env->excp_prefix; =20 switch (excp) { - case POWERPC_EXCP_CRITICAL: /* Critical input = */ - switch (excp_model) { - case POWERPC_EXCP_40x: - srr0 =3D SPR_40x_SRR2; - srr1 =3D SPR_40x_SRR3; - break; - case POWERPC_EXCP_BOOKE: - srr0 =3D SPR_BOOKE_CSRR0; - srr1 =3D SPR_BOOKE_CSRR1; - break; - case POWERPC_EXCP_G2: - break; - default: - goto excp_invalid; - } - break; case POWERPC_EXCP_MCHECK: /* Machine check exception = */ if (msr_me =3D=3D 0) { /* @@ -817,50 +782,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int ex= cp) env->ctr =3D msr; break; case POWERPC_EXCP_FPU: /* Floating-point unavailable exception = */ - case POWERPC_EXCP_APU: /* Auxiliary processor unavailable = */ case POWERPC_EXCP_DECR: /* Decrementer exception = */ break; - case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt = */ - /* FIT on 4xx */ - trace_ppc_excp_print("FIT"); - break; - case POWERPC_EXCP_WDT: /* Watchdog timer interrupt = */ - trace_ppc_excp_print("WDT"); - switch (excp_model) { - case POWERPC_EXCP_BOOKE: - srr0 =3D SPR_BOOKE_CSRR0; - srr1 =3D SPR_BOOKE_CSRR1; - break; - default: - break; - } - break; - case POWERPC_EXCP_DTLB: /* Data TLB error = */ - case POWERPC_EXCP_ITLB: /* Instruction TLB error = */ - break; - case POWERPC_EXCP_DEBUG: /* Debug interrupt = */ - if (env->flags & POWERPC_FLAG_DE) { - /* FIXME: choose one or the other based on CPU type */ - srr0 =3D SPR_BOOKE_DSRR0; - srr1 =3D SPR_BOOKE_DSRR1; - - env->spr[SPR_BOOKE_CSRR0] =3D env->nip; - env->spr[SPR_BOOKE_CSRR1] =3D msr; - - /* DBSR already modified by caller */ - } else { - cpu_abort(cs, "Debug exception triggered on unsupported model\= n"); - } - break; - case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/V= PU */ - env->spr[SPR_BOOKE_ESR] =3D ESR_SPV; - break; - case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt = */ - break; - case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt = */ - srr0 =3D SPR_BOOKE_CSRR0; - srr1 =3D SPR_BOOKE_CSRR1; - break; case POWERPC_EXCP_RESET: /* System reset exception = */ /* A power-saving exception sets ME, otherwise it is unchanged */ if (msr_pow) { @@ -890,8 +813,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int exc= p) /* fall through */ case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception = */ case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception = */ - case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception = */ - case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excepti= on */ case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt = */ case POWERPC_EXCP_HV_EMU: case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization = */ @@ -903,70 +824,25 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) case POWERPC_EXCP_VPU: /* Vector unavailable exception = */ case POWERPC_EXCP_VSXU: /* VSX unavailable exception = */ case POWERPC_EXCP_FU: /* Facility unavailable exception = */ -#ifdef TARGET_PPC64 env->spr[SPR_FSCR] |=3D ((target_ulong)env->error_code << 56); -#endif break; case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Except= ion */ -#ifdef TARGET_PPC64 env->spr[SPR_HFSCR] |=3D ((target_ulong)env->error_code << FSCR_IC= _POS); srr0 =3D SPR_HSRR0; srr1 =3D SPR_HSRR1; new_msr |=3D (target_ulong)MSR_HVB; new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); -#endif - break; - case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt = */ - trace_ppc_excp_print("PIT"); - break; - case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error = */ - case POWERPC_EXCP_DLTLB: /* Data load TLB miss = */ - case POWERPC_EXCP_DSTLB: /* Data store TLB miss = */ - switch (excp_model) { - case POWERPC_EXCP_602: - case POWERPC_EXCP_603: - case POWERPC_EXCP_G2: - /* Swap temporary saved registers with GPRs */ - if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { - new_msr |=3D (target_ulong)1 << MSR_TGPR; - hreg_swap_gpr_tgpr(env); - } - /* fall through */ - case POWERPC_EXCP_7x5: - ppc_excp_debug_sw_tlb(env, excp); - - msr |=3D env->crf[0] << 28; - msr |=3D env->error_code; /* key, D/I, S/L bits */ - /* Set way using a LRU mechanism */ - msr |=3D ((env->last_way + 1) & (env->nb_ways - 1)) << 17; - break; - default: - cpu_abort(cs, "Invalid TLB miss exception\n"); - break; - } break; - case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt= */ - case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrup= t */ - case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt= */ - case POWERPC_EXCP_IO: /* IO error exception = */ - case POWERPC_EXCP_RUNM: /* Run mode exception = */ - case POWERPC_EXCP_EMUL: /* Emulation trap exception = */ - case POWERPC_EXCP_FPA: /* Floating-point assist exception = */ - case POWERPC_EXCP_DABR: /* Data address breakpoint = */ - case POWERPC_EXCP_IABR: /* Instruction address breakpoint = */ - case POWERPC_EXCP_SMI: /* System management interrupt = */ case POWERPC_EXCP_THERM: /* Thermal interrupt = */ case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt= */ case POWERPC_EXCP_VPUA: /* Vector assist exception = */ - case POWERPC_EXCP_SOFTP: /* Soft patch exception = */ case POWERPC_EXCP_MAINT: /* Maintenance exception = */ - case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint = */ - case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint = */ + case POWERPC_EXCP_SDOOR: /* Doorbell interrupt = */ + case POWERPC_EXCP_HV_MAINT: /* Hypervisor Maintenance exception = */ cpu_abort(cs, "%s exception not implemented\n", powerpc_excp_name(excp)); break; default: - excp_invalid: cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); break; } @@ -991,22 +867,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int ex= cp) new_msr |=3D (target_ulong)1 << MSR_LE; } =20 -#if defined(TARGET_PPC64) - if (excp_model =3D=3D POWERPC_EXCP_BOOKE) { - if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) { - /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */ - new_msr |=3D (target_ulong)1 << MSR_CM; - } else { - vector =3D (uint32_t)vector; - } - } else { - if (!msr_isf && !mmu_is_64bit(env->mmu_model)) { - vector =3D (uint32_t)vector; - } else { - new_msr |=3D (target_ulong)1 << MSR_SF; - } - } -#endif + new_msr |=3D (target_ulong)1 << MSR_SF; =20 if (excp !=3D POWERPC_EXCP_SYSCALL_VECTORED) { /* Save PC */ @@ -1021,6 +882,12 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) =20 powerpc_set_excp_state(cpu, vector, new_msr); } +#else +static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp) +{ + g_assert_not_reached(); +} +#endif =20 /* * Note that this function should be greatly optimized when called --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643628584523494.7207947122622; Mon, 31 Jan 2022 03:29:44 -0800 (PST) Received: from localhost ([::1]:43194 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEUsR-0006nv-O2 for importer@patchew.org; Mon, 31 Jan 2022 06:29:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34258) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYg-00061I-VE; Mon, 31 Jan 2022 06:09:19 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:39892) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYb-000566-W7; Mon, 31 Jan 2022 06:09:17 -0500 Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 20V9sFn7005858; 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Mon, 31 Jan 2022 11:08:39 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 05FA111C058; Mon, 31 Jan 2022 11:08:39 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:38 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 2A348220149; Mon, 31 Jan 2022 12:08:38 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 30/41] target/ppc: books: Machine Check exception cleanup Date: Mon, 31 Jan 2022 12:08:00 +0100 Message-Id: <20220131110811.619053-31-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: D2lU7cF67q3aekJxGQ2hSPj-ypztn92t X-Proofpoint-ORIG-GUID: D2lU7cF67q3aekJxGQ2hSPj-ypztn92t X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 mlxlogscore=970 clxscore=1034 bulkscore=0 priorityscore=1501 adultscore=0 spamscore=0 suspectscore=0 mlxscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643628586841100003 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas powerpc_excp_books is BookS only, so remove 40x and BookE code. Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220124184605.999353-4-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 161b207bc7b8..be8c64a0cde9 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -632,23 +632,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int ex= cp) /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); =20 - /* XXX: should also have something loaded in DAR / DSISR */ - switch (excp_model) { - case POWERPC_EXCP_40x: - srr0 =3D SPR_40x_SRR2; - srr1 =3D SPR_40x_SRR3; - break; - case POWERPC_EXCP_BOOKE: - /* FIXME: choose one or the other based on CPU type */ - srr0 =3D SPR_BOOKE_MCSRR0; - srr1 =3D SPR_BOOKE_MCSRR1; - - env->spr[SPR_BOOKE_CSRR0] =3D env->nip; - env->spr[SPR_BOOKE_CSRR1] =3D msr; - break; - default: - break; - } break; case POWERPC_EXCP_DSI: /* Data storage exception = */ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643629221564706.0519196776225; Mon, 31 Jan 2022 03:40:21 -0800 (PST) Received: from localhost ([::1]:35584 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEV2i-0004lY-K3 for importer@patchew.org; Mon, 31 Jan 2022 06:40:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34654) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUZ3-0006BR-JS; Mon, 31 Jan 2022 06:09:41 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:37244) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYy-00055e-7B; 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Mon, 31 Jan 2022 11:08:40 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2099111C052; Mon, 31 Jan 2022 11:08:40 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C0C4E11C04C; Mon, 31 Jan 2022 11:08:39 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:39 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id E4FCA2201C1; Mon, 31 Jan 2022 12:08:38 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 31/41] target/ppc: books: External interrupt cleanup Date: Mon, 31 Jan 2022 12:08:01 +0100 Message-Id: <20220131110811.619053-32-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: DSxKlnPEXJdZ0MgrVwDOp2xdhFoMq5s_ X-Proofpoint-GUID: DSxKlnPEXJdZ0MgrVwDOp2xdhFoMq5s_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 suspectscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 malwarescore=0 impostorscore=0 phishscore=0 mlxscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643629224414100029 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Since this is now BookS only, we can simplify the code a bit and check has_hv_mode instead of enumerating the exception models. LPES0 does not make sense if there is no MSR_HV. Note that QEMU does not support HV mode on 970 and POWER5+ so we don't set MSR_HV in msr_mask. Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220124184605.999353-5-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 30 +++++++----------------------- 1 file changed, 7 insertions(+), 23 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index be8c64a0cde9..e0d6287c4e88 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -644,39 +644,23 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) { bool lpes0; =20 - cs =3D CPU(cpu); - /* - * Exception targeting modifiers - * - * LPES0 is supported on POWER7/8/9 - * LPES1 is not supported (old iSeries mode) - * - * On anything else, we behave as if LPES0 is 1 - * (externals don't alter MSR:HV) + * LPES0 is only taken into consideration if we support HV + * mode for this CPU. */ -#if defined(TARGET_PPC64) - if (excp_model =3D=3D POWERPC_EXCP_POWER7 || - excp_model =3D=3D POWERPC_EXCP_POWER8 || - excp_model =3D=3D POWERPC_EXCP_POWER9 || - excp_model =3D=3D POWERPC_EXCP_POWER10) { - lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); - } else -#endif /* defined(TARGET_PPC64) */ - { - lpes0 =3D true; + if (!env->has_hv_mode) { + break; } =20 + lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); + if (!lpes0) { new_msr |=3D (target_ulong)MSR_HVB; new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); srr0 =3D SPR_HSRR0; srr1 =3D SPR_HSRR1; } - if (env->mpic_proxy) { - /* IACK the IRQ on delivery */ - env->spr[SPR_BOOKE_EPR] =3D ldl_phys(cs->as, env->mpic_iack); - } + break; } case POWERPC_EXCP_ALIGN: /* Alignment exception = */ --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643627899662584.5892645126366; Mon, 31 Jan 2022 03:18:19 -0800 (PST) Received: from localhost ([::1]:55510 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEUhO-0003Vv-MP for importer@patchew.org; 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Mon, 31 Jan 2022 12:08:39 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 32/41] target/ppc: books: Program exception cleanup Date: Mon, 31 Jan 2022 12:08:02 +0100 Message-Id: <20220131110811.619053-33-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 2IJTHR_2HgWSujuB5R4l6sLODLZ_5nsQ X-Proofpoint-GUID: 2IJTHR_2HgWSujuB5R4l6sLODLZ_5nsQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=928 lowpriorityscore=0 suspectscore=0 malwarescore=0 mlxscore=0 bulkscore=0 clxscore=1034 phishscore=0 impostorscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643627901681100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Remove setting of BookE registers. Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220124184605.999353-6-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index e0d6287c4e88..0e84cecc68e7 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -688,20 +688,16 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) * precise in the MSR. */ msr |=3D 0x00100000; - env->spr[SPR_BOOKE_ESR] =3D ESR_FP; break; case POWERPC_EXCP_INVAL: trace_ppc_excp_inval(env->nip); msr |=3D 0x00080000; - env->spr[SPR_BOOKE_ESR] =3D ESR_PIL; break; case POWERPC_EXCP_PRIV: msr |=3D 0x00040000; - env->spr[SPR_BOOKE_ESR] =3D ESR_PPR; break; case POWERPC_EXCP_TRAP: msr |=3D 0x00020000; - env->spr[SPR_BOOKE_ESR] =3D ESR_PTR; break; default: /* Should never occur */ --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 31 Jan 2022 11:08:41 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5821FA405B; Mon, 31 Jan 2022 11:08:41 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av23.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:41 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 7C27C2201C1; Mon, 31 Jan 2022 12:08:40 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 33/41] target/ppc: Introduce powerpc_excp_74xx Date: Mon, 31 Jan 2022 12:08:03 +0100 Message-Id: <20220131110811.619053-34-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: tA4mu8usjn_nZGOOkQjgmAC6LawvFOt- X-Proofpoint-GUID: tA4mu8usjn_nZGOOkQjgmAC6LawvFOt- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=954 suspectscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 malwarescore=0 impostorscore=0 phishscore=0 mlxscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643629671857100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Introduce a new powerpc_excp function specific for PowerPC 74xx CPUs. This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas Message-Id: <20220127201116.1154733-2-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 474 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 474 insertions(+) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 0e84cecc68e7..0e3d3ffcf488 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -551,6 +551,477 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int exc= p) powerpc_set_excp_state(cpu, vector, new_msr); } =20 +static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) +{ + CPUState *cs =3D CPU(cpu); + CPUPPCState *env =3D &cpu->env; + int excp_model =3D env->excp_model; + target_ulong msr, new_msr, vector; + int srr0, srr1, lev =3D -1; + + if (excp <=3D POWERPC_EXCP_NONE || excp >=3D POWERPC_EXCP_NB) { + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); + } + + qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx + " =3D> %s (%d) error=3D%02x\n", env->nip, powerpc_excp_n= ame(excp), + excp, env->error_code); + + /* new srr1 value excluding must-be-zero bits */ + if (excp_model =3D=3D POWERPC_EXCP_BOOKE) { + msr =3D env->msr; + } else { + msr =3D env->msr & ~0x783f0000ULL; + } + + /* + * new interrupt handler msr preserves existing HV and ME unless + * explicitly overriden + */ + new_msr =3D env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); + + /* target registers */ + srr0 =3D SPR_SRR0; + srr1 =3D SPR_SRR1; + + /* + * check for special resume at 0x100 from doze/nap/sleep/winkle on + * P7/P8/P9 + */ + if (env->resume_as_sreset) { + excp =3D powerpc_reset_wakeup(cs, env, excp, &msr); + } + + /* + * Hypervisor emulation assistance interrupt only exists on server + * arch 2.05 server or later. We also don't want to generate it if + * we don't have HVB in msr_mask (PAPR mode). + */ + if (excp =3D=3D POWERPC_EXCP_HV_EMU +#if defined(TARGET_PPC64) + && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB)) +#endif /* defined(TARGET_PPC64) */ + + ) { + excp =3D POWERPC_EXCP_PROGRAM; + } + +#ifdef TARGET_PPC64 + /* + * SPEU and VPU share the same IVOR but they exist in different + * processors. SPEU is e500v1/2 only and VPU is e6500 only. + */ + if (excp_model =3D=3D POWERPC_EXCP_BOOKE && excp =3D=3D POWERPC_EXCP_V= PU) { + excp =3D POWERPC_EXCP_SPEU; + } +#endif + + vector =3D env->excp_vectors[excp]; + if (vector =3D=3D (target_ulong)-1ULL) { + cpu_abort(cs, "Raised an exception without defined vector %d\n", + excp); + } + + vector |=3D env->excp_prefix; + + switch (excp) { + case POWERPC_EXCP_CRITICAL: /* Critical input = */ + switch (excp_model) { + case POWERPC_EXCP_40x: + srr0 =3D SPR_40x_SRR2; + srr1 =3D SPR_40x_SRR3; + break; + case POWERPC_EXCP_BOOKE: + srr0 =3D SPR_BOOKE_CSRR0; + srr1 =3D SPR_BOOKE_CSRR1; + break; + case POWERPC_EXCP_G2: + break; + default: + goto excp_invalid; + } + break; + case POWERPC_EXCP_MCHECK: /* Machine check exception = */ + if (msr_me =3D=3D 0) { + /* + * Machine check exception is not enabled. Enter + * checkstop state. + */ + fprintf(stderr, "Machine check while not allowed. " + "Entering checkstop state\n"); + if (qemu_log_separate()) { + qemu_log("Machine check while not allowed. " + "Entering checkstop state\n"); + } + cs->halted =3D 1; + cpu_interrupt_exittb(cs); + } + if (env->msr_mask & MSR_HVB) { + /* + * ISA specifies HV, but can be delivered to guest with HV + * clear (e.g., see FWNMI in PAPR). + */ + new_msr |=3D (target_ulong)MSR_HVB; + } + + /* machine check exceptions don't have ME set */ + new_msr &=3D ~((target_ulong)1 << MSR_ME); + + /* XXX: should also have something loaded in DAR / DSISR */ + switch (excp_model) { + case POWERPC_EXCP_40x: + srr0 =3D SPR_40x_SRR2; + srr1 =3D SPR_40x_SRR3; + break; + case POWERPC_EXCP_BOOKE: + /* FIXME: choose one or the other based on CPU type */ + srr0 =3D SPR_BOOKE_MCSRR0; + srr1 =3D SPR_BOOKE_MCSRR1; + + env->spr[SPR_BOOKE_CSRR0] =3D env->nip; + env->spr[SPR_BOOKE_CSRR1] =3D msr; + break; + default: + break; + } + break; + case POWERPC_EXCP_DSI: /* Data storage exception = */ + trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); + break; + case POWERPC_EXCP_ISI: /* Instruction storage exception = */ + trace_ppc_excp_isi(msr, env->nip); + msr |=3D env->error_code; + break; + case POWERPC_EXCP_EXTERNAL: /* External input = */ + { + bool lpes0; + + cs =3D CPU(cpu); + + /* + * Exception targeting modifiers + * + * LPES0 is supported on POWER7/8/9 + * LPES1 is not supported (old iSeries mode) + * + * On anything else, we behave as if LPES0 is 1 + * (externals don't alter MSR:HV) + */ +#if defined(TARGET_PPC64) + if (excp_model =3D=3D POWERPC_EXCP_POWER7 || + excp_model =3D=3D POWERPC_EXCP_POWER8 || + excp_model =3D=3D POWERPC_EXCP_POWER9 || + excp_model =3D=3D POWERPC_EXCP_POWER10) { + lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); + } else +#endif /* defined(TARGET_PPC64) */ + { + lpes0 =3D true; + } + + if (!lpes0) { + new_msr |=3D (target_ulong)MSR_HVB; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); + srr0 =3D SPR_HSRR0; + srr1 =3D SPR_HSRR1; + } + if (env->mpic_proxy) { + /* IACK the IRQ on delivery */ + env->spr[SPR_BOOKE_EPR] =3D ldl_phys(cs->as, env->mpic_iack); + } + break; + } + case POWERPC_EXCP_ALIGN: /* Alignment exception = */ + /* Get rS/rD and rA from faulting opcode */ + /* + * Note: the opcode fields will not be set properly for a + * direct store load/store, but nobody cares as nobody + * actually uses direct store segments. + */ + env->spr[SPR_DSISR] |=3D (env->error_code & 0x03FF0000) >> 16; + break; + case POWERPC_EXCP_PROGRAM: /* Program exception = */ + switch (env->error_code & ~0xF) { + case POWERPC_EXCP_FP: + if ((msr_fe0 =3D=3D 0 && msr_fe1 =3D=3D 0) || msr_fp =3D=3D 0)= { + trace_ppc_excp_fp_ignore(); + cs->exception_index =3D POWERPC_EXCP_NONE; + env->error_code =3D 0; + return; + } + + /* + * FP exceptions always have NIP pointing to the faulting + * instruction, so always use store_next and claim we are + * precise in the MSR. + */ + msr |=3D 0x00100000; + env->spr[SPR_BOOKE_ESR] =3D ESR_FP; + break; + case POWERPC_EXCP_INVAL: + trace_ppc_excp_inval(env->nip); + msr |=3D 0x00080000; + env->spr[SPR_BOOKE_ESR] =3D ESR_PIL; + break; + case POWERPC_EXCP_PRIV: + msr |=3D 0x00040000; + env->spr[SPR_BOOKE_ESR] =3D ESR_PPR; + break; + case POWERPC_EXCP_TRAP: + msr |=3D 0x00020000; + env->spr[SPR_BOOKE_ESR] =3D ESR_PTR; + break; + default: + /* Should never occur */ + cpu_abort(cs, "Invalid program exception %d. Aborting\n", + env->error_code); + break; + } + break; + case POWERPC_EXCP_SYSCALL: /* System call exception = */ + lev =3D env->error_code; + + if ((lev =3D=3D 1) && cpu->vhyp) { + dump_hcall(env); + } else { + dump_syscall(env); + } + + /* + * We need to correct the NIP which in this case is supposed + * to point to the next instruction + */ + env->nip +=3D 4; + + /* "PAPR mode" built-in hypercall emulation */ + if ((lev =3D=3D 1) && cpu->vhyp) { + PPCVirtualHypervisorClass *vhc =3D + PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); + vhc->hypercall(cpu->vhyp, cpu); + return; + } + if (lev =3D=3D 1) { + new_msr |=3D (target_ulong)MSR_HVB; + } + break; + case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception = */ + lev =3D env->error_code; + dump_syscall(env); + env->nip +=3D 4; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_EE); + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); + + vector +=3D lev * 0x20; + + env->lr =3D env->nip; + env->ctr =3D msr; + break; + case POWERPC_EXCP_FPU: /* Floating-point unavailable exception = */ + case POWERPC_EXCP_APU: /* Auxiliary processor unavailable = */ + case POWERPC_EXCP_DECR: /* Decrementer exception = */ + break; + case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt = */ + /* FIT on 4xx */ + trace_ppc_excp_print("FIT"); + break; + case POWERPC_EXCP_WDT: /* Watchdog timer interrupt = */ + trace_ppc_excp_print("WDT"); + switch (excp_model) { + case POWERPC_EXCP_BOOKE: + srr0 =3D SPR_BOOKE_CSRR0; + srr1 =3D SPR_BOOKE_CSRR1; + break; + default: + break; + } + break; + case POWERPC_EXCP_DTLB: /* Data TLB error = */ + case POWERPC_EXCP_ITLB: /* Instruction TLB error = */ + break; + case POWERPC_EXCP_DEBUG: /* Debug interrupt = */ + if (env->flags & POWERPC_FLAG_DE) { + /* FIXME: choose one or the other based on CPU type */ + srr0 =3D SPR_BOOKE_DSRR0; + srr1 =3D SPR_BOOKE_DSRR1; + + env->spr[SPR_BOOKE_CSRR0] =3D env->nip; + env->spr[SPR_BOOKE_CSRR1] =3D msr; + + /* DBSR already modified by caller */ + } else { + cpu_abort(cs, "Debug exception triggered on unsupported model\= n"); + } + break; + case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/V= PU */ + env->spr[SPR_BOOKE_ESR] =3D ESR_SPV; + break; + case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt = */ + break; + case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt = */ + srr0 =3D SPR_BOOKE_CSRR0; + srr1 =3D SPR_BOOKE_CSRR1; + break; + case POWERPC_EXCP_RESET: /* System reset exception = */ + /* A power-saving exception sets ME, otherwise it is unchanged */ + if (msr_pow) { + /* indicate that we resumed from power save mode */ + msr |=3D 0x10000; + new_msr |=3D ((target_ulong)1 << MSR_ME); + } + if (env->msr_mask & MSR_HVB) { + /* + * ISA specifies HV, but can be delivered to guest with HV + * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU). + */ + new_msr |=3D (target_ulong)MSR_HVB; + } else { + if (msr_pow) { + cpu_abort(cs, "Trying to deliver power-saving system reset= " + "exception %d with no HV support\n", excp); + } + } + break; + case POWERPC_EXCP_DSEG: /* Data segment exception = */ + case POWERPC_EXCP_ISEG: /* Instruction segment exception = */ + case POWERPC_EXCP_TRACE: /* Trace exception = */ + break; + case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excepti= on */ + msr |=3D env->error_code; + /* fall through */ + case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception = */ + case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception = */ + case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception = */ + case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excepti= on */ + case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt = */ + case POWERPC_EXCP_HV_EMU: + case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization = */ + srr0 =3D SPR_HSRR0; + srr1 =3D SPR_HSRR1; + new_msr |=3D (target_ulong)MSR_HVB; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); + break; + case POWERPC_EXCP_VPU: /* Vector unavailable exception = */ + case POWERPC_EXCP_VSXU: /* VSX unavailable exception = */ + case POWERPC_EXCP_FU: /* Facility unavailable exception = */ +#ifdef TARGET_PPC64 + env->spr[SPR_FSCR] |=3D ((target_ulong)env->error_code << 56); +#endif + break; + case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Except= ion */ +#ifdef TARGET_PPC64 + env->spr[SPR_HFSCR] |=3D ((target_ulong)env->error_code << FSCR_IC= _POS); + srr0 =3D SPR_HSRR0; + srr1 =3D SPR_HSRR1; + new_msr |=3D (target_ulong)MSR_HVB; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); +#endif + break; + case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt = */ + trace_ppc_excp_print("PIT"); + break; + case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error = */ + case POWERPC_EXCP_DLTLB: /* Data load TLB miss = */ + case POWERPC_EXCP_DSTLB: /* Data store TLB miss = */ + switch (excp_model) { + case POWERPC_EXCP_602: + case POWERPC_EXCP_603: + case POWERPC_EXCP_G2: + /* Swap temporary saved registers with GPRs */ + if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { + new_msr |=3D (target_ulong)1 << MSR_TGPR; + hreg_swap_gpr_tgpr(env); + } + /* fall through */ + case POWERPC_EXCP_7x5: + ppc_excp_debug_sw_tlb(env, excp); + + msr |=3D env->crf[0] << 28; + msr |=3D env->error_code; /* key, D/I, S/L bits */ + /* Set way using a LRU mechanism */ + msr |=3D ((env->last_way + 1) & (env->nb_ways - 1)) << 17; + break; + default: + cpu_abort(cs, "Invalid TLB miss exception\n"); + break; + } + break; + case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt= */ + case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrup= t */ + case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt= */ + case POWERPC_EXCP_IO: /* IO error exception = */ + case POWERPC_EXCP_RUNM: /* Run mode exception = */ + case POWERPC_EXCP_EMUL: /* Emulation trap exception = */ + case POWERPC_EXCP_FPA: /* Floating-point assist exception = */ + case POWERPC_EXCP_DABR: /* Data address breakpoint = */ + case POWERPC_EXCP_IABR: /* Instruction address breakpoint = */ + case POWERPC_EXCP_SMI: /* System management interrupt = */ + case POWERPC_EXCP_THERM: /* Thermal interrupt = */ + case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt= */ + case POWERPC_EXCP_VPUA: /* Vector assist exception = */ + case POWERPC_EXCP_SOFTP: /* Soft patch exception = */ + case POWERPC_EXCP_MAINT: /* Maintenance exception = */ + case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint = */ + case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint = */ + cpu_abort(cs, "%s exception not implemented\n", + powerpc_excp_name(excp)); + break; + default: + excp_invalid: + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); + break; + } + + /* Sanity check */ + if (!(env->msr_mask & MSR_HVB)) { + if (new_msr & MSR_HVB) { + cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with " + "no HV support\n", excp); + } + if (srr0 =3D=3D SPR_HSRR0) { + cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with " + "no HV support\n", excp); + } + } + + /* + * Sort out endianness of interrupt, this differs depending on the + * CPU, the HV mode, etc... + */ + if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { + new_msr |=3D (target_ulong)1 << MSR_LE; + } + +#if defined(TARGET_PPC64) + if (excp_model =3D=3D POWERPC_EXCP_BOOKE) { + if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) { + /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */ + new_msr |=3D (target_ulong)1 << MSR_CM; + } else { + vector =3D (uint32_t)vector; + } + } else { + if (!msr_isf && !mmu_is_64bit(env->mmu_model)) { + vector =3D (uint32_t)vector; + } else { + new_msr |=3D (target_ulong)1 << MSR_SF; + } + } +#endif + + if (excp !=3D POWERPC_EXCP_SYSCALL_VECTORED) { + /* Save PC */ + env->spr[srr0] =3D env->nip; + + /* Save MSR */ + env->spr[srr1] =3D msr; + } + + /* This can update new_msr and vector if AIL applies */ + ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector); + + powerpc_set_excp_state(cpu, vector, new_msr); +} + #ifdef TARGET_PPC64 static void powerpc_excp_books(PowerPCCPU *cpu, int excp) { @@ -1335,6 +1806,9 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_40x: powerpc_excp_40x(cpu, excp); break; + case POWERPC_EXCP_74xx: + powerpc_excp_74xx(cpu, excp); + break; case POWERPC_EXCP_970: case POWERPC_EXCP_POWER7: case POWERPC_EXCP_POWER8: --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164363203106271.3310064923005; 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Mon, 31 Jan 2022 11:08:42 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av23.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:42 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 43880220149; Mon, 31 Jan 2022 12:08:41 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 34/41] target/ppc: Simplify powerpc_excp_74xx Date: Mon, 31 Jan 2022 12:08:04 +0100 Message-Id: <20220131110811.619053-35-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 1_c1UAmLifgvLdKKeZjd7DLItmhpx0Nn X-Proofpoint-ORIG-GUID: 1_c1UAmLifgvLdKKeZjd7DLItmhpx0Nn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 bulkscore=0 adultscore=0 impostorscore=0 mlxlogscore=541 malwarescore=0 phishscore=0 suspectscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643632033334100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Differences from the generic powerpc_excp code: - Not BookE, so some MSR bits are cleared at interrupt dispatch; - No MSR_HV; - No power saving states; - No Hypervisor Emulation Assistance; - Not 64 bits; - No System call vectored; - No Alternate Interrupt Location. Exceptions used: POWERPC_EXCP_ALIGN POWERPC_EXCP_DECR POWERPC_EXCP_DSI POWERPC_EXCP_EXTERNAL POWERPC_EXCP_FPU POWERPC_EXCP_IABR POWERPC_EXCP_ISI POWERPC_EXCP_MCHECK POWERPC_EXCP_PERFM POWERPC_EXCP_PROGRAM POWERPC_EXCP_RESET POWERPC_EXCP_SMI POWERPC_EXCP_SYSCALL POWERPC_EXCP_THERM POWERPC_EXCP_TRACE POWERPC_EXCP_VPU POWERPC_EXCP_VPUA Signed-off-by: Fabiano Rosas Message-Id: <20220127201116.1154733-3-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 211 ++------------------------------------- 1 file changed, 9 insertions(+), 202 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 0e3d3ffcf488..13e5cb3ddcdb 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -568,54 +568,26 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int ex= cp) excp, env->error_code); =20 /* new srr1 value excluding must-be-zero bits */ - if (excp_model =3D=3D POWERPC_EXCP_BOOKE) { - msr =3D env->msr; - } else { - msr =3D env->msr & ~0x783f0000ULL; - } + msr =3D env->msr & ~0x783f0000ULL; =20 /* - * new interrupt handler msr preserves existing HV and ME unless + * new interrupt handler msr preserves existing ME unless * explicitly overriden */ - new_msr =3D env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); + new_msr =3D env->msr & ((target_ulong)1 << MSR_ME); =20 /* target registers */ srr0 =3D SPR_SRR0; srr1 =3D SPR_SRR1; =20 - /* - * check for special resume at 0x100 from doze/nap/sleep/winkle on - * P7/P8/P9 - */ - if (env->resume_as_sreset) { - excp =3D powerpc_reset_wakeup(cs, env, excp, &msr); - } - /* * Hypervisor emulation assistance interrupt only exists on server - * arch 2.05 server or later. We also don't want to generate it if - * we don't have HVB in msr_mask (PAPR mode). + * arch 2.05 server or later. */ - if (excp =3D=3D POWERPC_EXCP_HV_EMU -#if defined(TARGET_PPC64) - && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB)) -#endif /* defined(TARGET_PPC64) */ - - ) { + if (excp =3D=3D POWERPC_EXCP_HV_EMU) { excp =3D POWERPC_EXCP_PROGRAM; } =20 -#ifdef TARGET_PPC64 - /* - * SPEU and VPU share the same IVOR but they exist in different - * processors. SPEU is e500v1/2 only and VPU is e6500 only. - */ - if (excp_model =3D=3D POWERPC_EXCP_BOOKE && excp =3D=3D POWERPC_EXCP_V= PU) { - excp =3D POWERPC_EXCP_SPEU; - } -#endif - vector =3D env->excp_vectors[excp]; if (vector =3D=3D (target_ulong)-1ULL) { cpu_abort(cs, "Raised an exception without defined vector %d\n", @@ -625,22 +597,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int exc= p) vector |=3D env->excp_prefix; =20 switch (excp) { - case POWERPC_EXCP_CRITICAL: /* Critical input = */ - switch (excp_model) { - case POWERPC_EXCP_40x: - srr0 =3D SPR_40x_SRR2; - srr1 =3D SPR_40x_SRR3; - break; - case POWERPC_EXCP_BOOKE: - srr0 =3D SPR_BOOKE_CSRR0; - srr1 =3D SPR_BOOKE_CSRR1; - break; - case POWERPC_EXCP_G2: - break; - default: - goto excp_invalid; - } - break; case POWERPC_EXCP_MCHECK: /* Machine check exception = */ if (msr_me =3D=3D 0) { /* @@ -804,63 +760,9 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int exc= p) new_msr |=3D (target_ulong)MSR_HVB; } break; - case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception = */ - lev =3D env->error_code; - dump_syscall(env); - env->nip +=3D 4; - new_msr |=3D env->msr & ((target_ulong)1 << MSR_EE); - new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); - - vector +=3D lev * 0x20; - - env->lr =3D env->nip; - env->ctr =3D msr; - break; case POWERPC_EXCP_FPU: /* Floating-point unavailable exception = */ - case POWERPC_EXCP_APU: /* Auxiliary processor unavailable = */ case POWERPC_EXCP_DECR: /* Decrementer exception = */ break; - case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt = */ - /* FIT on 4xx */ - trace_ppc_excp_print("FIT"); - break; - case POWERPC_EXCP_WDT: /* Watchdog timer interrupt = */ - trace_ppc_excp_print("WDT"); - switch (excp_model) { - case POWERPC_EXCP_BOOKE: - srr0 =3D SPR_BOOKE_CSRR0; - srr1 =3D SPR_BOOKE_CSRR1; - break; - default: - break; - } - break; - case POWERPC_EXCP_DTLB: /* Data TLB error = */ - case POWERPC_EXCP_ITLB: /* Instruction TLB error = */ - break; - case POWERPC_EXCP_DEBUG: /* Debug interrupt = */ - if (env->flags & POWERPC_FLAG_DE) { - /* FIXME: choose one or the other based on CPU type */ - srr0 =3D SPR_BOOKE_DSRR0; - srr1 =3D SPR_BOOKE_DSRR1; - - env->spr[SPR_BOOKE_CSRR0] =3D env->nip; - env->spr[SPR_BOOKE_CSRR1] =3D msr; - - /* DBSR already modified by caller */ - } else { - cpu_abort(cs, "Debug exception triggered on unsupported model\= n"); - } - break; - case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/V= PU */ - env->spr[SPR_BOOKE_ESR] =3D ESR_SPV; - break; - case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt = */ - break; - case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt = */ - srr0 =3D SPR_BOOKE_CSRR0; - srr1 =3D SPR_BOOKE_CSRR1; - break; case POWERPC_EXCP_RESET: /* System reset exception = */ /* A power-saving exception sets ME, otherwise it is unchanged */ if (msr_pow) { @@ -881,92 +783,19 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int ex= cp) } } break; - case POWERPC_EXCP_DSEG: /* Data segment exception = */ - case POWERPC_EXCP_ISEG: /* Instruction segment exception = */ case POWERPC_EXCP_TRACE: /* Trace exception = */ break; - case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excepti= on */ - msr |=3D env->error_code; - /* fall through */ - case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception = */ - case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception = */ - case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception = */ - case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excepti= on */ - case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt = */ - case POWERPC_EXCP_HV_EMU: - case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization = */ - srr0 =3D SPR_HSRR0; - srr1 =3D SPR_HSRR1; - new_msr |=3D (target_ulong)MSR_HVB; - new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); - break; case POWERPC_EXCP_VPU: /* Vector unavailable exception = */ - case POWERPC_EXCP_VSXU: /* VSX unavailable exception = */ - case POWERPC_EXCP_FU: /* Facility unavailable exception = */ -#ifdef TARGET_PPC64 - env->spr[SPR_FSCR] |=3D ((target_ulong)env->error_code << 56); -#endif break; - case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Except= ion */ -#ifdef TARGET_PPC64 - env->spr[SPR_HFSCR] |=3D ((target_ulong)env->error_code << FSCR_IC= _POS); - srr0 =3D SPR_HSRR0; - srr1 =3D SPR_HSRR1; - new_msr |=3D (target_ulong)MSR_HVB; - new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); -#endif - break; - case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt = */ - trace_ppc_excp_print("PIT"); - break; - case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error = */ - case POWERPC_EXCP_DLTLB: /* Data load TLB miss = */ - case POWERPC_EXCP_DSTLB: /* Data store TLB miss = */ - switch (excp_model) { - case POWERPC_EXCP_602: - case POWERPC_EXCP_603: - case POWERPC_EXCP_G2: - /* Swap temporary saved registers with GPRs */ - if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { - new_msr |=3D (target_ulong)1 << MSR_TGPR; - hreg_swap_gpr_tgpr(env); - } - /* fall through */ - case POWERPC_EXCP_7x5: - ppc_excp_debug_sw_tlb(env, excp); - - msr |=3D env->crf[0] << 28; - msr |=3D env->error_code; /* key, D/I, S/L bits */ - /* Set way using a LRU mechanism */ - msr |=3D ((env->last_way + 1) & (env->nb_ways - 1)) << 17; - break; - default: - cpu_abort(cs, "Invalid TLB miss exception\n"); - break; - } - break; - case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt= */ - case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrup= t */ - case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt= */ - case POWERPC_EXCP_IO: /* IO error exception = */ - case POWERPC_EXCP_RUNM: /* Run mode exception = */ - case POWERPC_EXCP_EMUL: /* Emulation trap exception = */ - case POWERPC_EXCP_FPA: /* Floating-point assist exception = */ - case POWERPC_EXCP_DABR: /* Data address breakpoint = */ case POWERPC_EXCP_IABR: /* Instruction address breakpoint = */ case POWERPC_EXCP_SMI: /* System management interrupt = */ case POWERPC_EXCP_THERM: /* Thermal interrupt = */ case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt= */ case POWERPC_EXCP_VPUA: /* Vector assist exception = */ - case POWERPC_EXCP_SOFTP: /* Soft patch exception = */ - case POWERPC_EXCP_MAINT: /* Maintenance exception = */ - case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint = */ - case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint = */ cpu_abort(cs, "%s exception not implemented\n", powerpc_excp_name(excp)); break; default: - excp_invalid: cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); break; } @@ -991,33 +820,11 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int ex= cp) new_msr |=3D (target_ulong)1 << MSR_LE; } =20 -#if defined(TARGET_PPC64) - if (excp_model =3D=3D POWERPC_EXCP_BOOKE) { - if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) { - /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */ - new_msr |=3D (target_ulong)1 << MSR_CM; - } else { - vector =3D (uint32_t)vector; - } - } else { - if (!msr_isf && !mmu_is_64bit(env->mmu_model)) { - vector =3D (uint32_t)vector; - } else { - new_msr |=3D (target_ulong)1 << MSR_SF; - } - } -#endif - - if (excp !=3D POWERPC_EXCP_SYSCALL_VECTORED) { - /* Save PC */ - env->spr[srr0] =3D env->nip; - - /* Save MSR */ - env->spr[srr1] =3D msr; - } + /* Save PC */ + env->spr[srr0] =3D env->nip; =20 - /* This can update new_msr and vector if AIL applies */ - ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector); + /* Save MSR */ + env->spr[srr1] =3D msr; =20 powerpc_set_excp_state(cpu, vector, new_msr); } --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 31 Jan 2022 11:08:43 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DADD911C054; Mon, 31 Jan 2022 11:08:42 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:42 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 0A1782201C1; Mon, 31 Jan 2022 12:08:41 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 35/41] target/ppc: 74xx: Machine Check exception cleanup Date: Mon, 31 Jan 2022 12:08:05 +0100 Message-Id: <20220131110811.619053-36-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 8ckN1oRX9D3eqqK19pkY3ORZ9FH8ErTH X-Proofpoint-ORIG-GUID: 8ckN1oRX9D3eqqK19pkY3ORZ9FH8ErTH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1034 impostorscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=707 priorityscore=1501 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643628967597100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas The 74xx don't have an MSR_HV. Also remove 40x and BookE code. Signed-off-by: Fabiano Rosas Message-Id: <20220127201116.1154733-4-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 13e5cb3ddcdb..0d8c66b98fd3 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -612,34 +612,10 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int ex= cp) cs->halted =3D 1; cpu_interrupt_exittb(cs); } - if (env->msr_mask & MSR_HVB) { - /* - * ISA specifies HV, but can be delivered to guest with HV - * clear (e.g., see FWNMI in PAPR). - */ - new_msr |=3D (target_ulong)MSR_HVB; - } =20 /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); =20 - /* XXX: should also have something loaded in DAR / DSISR */ - switch (excp_model) { - case POWERPC_EXCP_40x: - srr0 =3D SPR_40x_SRR2; - srr1 =3D SPR_40x_SRR3; - break; - case POWERPC_EXCP_BOOKE: - /* FIXME: choose one or the other based on CPU type */ - srr0 =3D SPR_BOOKE_MCSRR0; - srr1 =3D SPR_BOOKE_MCSRR1; - - env->spr[SPR_BOOKE_CSRR0] =3D env->nip; - env->spr[SPR_BOOKE_CSRR1] =3D msr; - break; - default: - break; - } break; case POWERPC_EXCP_DSI: /* Data storage exception = */ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643630319124419.3210688802269; Mon, 31 Jan 2022 03:58:39 -0800 (PST) Received: from localhost ([::1]:42890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEVKQ-0003zd-Cr for importer@patchew.org; Mon, 31 Jan 2022 06:58:38 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34656) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUZ3-0006BS-L5; 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Mon, 31 Jan 2022 11:08:46 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 20VB8i8E46727620 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 31 Jan 2022 11:08:44 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 03552A4071; Mon, 31 Jan 2022 11:08:44 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A09E9A407B; Mon, 31 Jan 2022 11:08:43 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:43 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id C375D220149; Mon, 31 Jan 2022 12:08:42 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 36/41] target/ppc: 74xx: External interrupt cleanup Date: Mon, 31 Jan 2022 12:08:06 +0100 Message-Id: <20220131110811.619053-37-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: VMJn6zpyYbfwalQu2zy0pMhN2a54cFWn X-Proofpoint-GUID: VMJn6zpyYbfwalQu2zy0pMhN2a54cFWn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 suspectscore=0 phishscore=0 impostorscore=0 malwarescore=0 mlxlogscore=852 bulkscore=0 adultscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643630321548100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas The 74xx don't have MSR_HV so all the LPES0 logic can be removed. Also remove the BookE IRQ code. Signed-off-by: Fabiano Rosas Message-Id: <20220127201116.1154733-5-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 38 -------------------------------------- 1 file changed, 38 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 0d8c66b98fd3..b9a1d7ae7e40 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -555,7 +555,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; - int excp_model =3D env->excp_model; target_ulong msr, new_msr, vector; int srr0, srr1, lev =3D -1; =20 @@ -625,44 +624,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int exc= p) msr |=3D env->error_code; break; case POWERPC_EXCP_EXTERNAL: /* External input = */ - { - bool lpes0; - - cs =3D CPU(cpu); - - /* - * Exception targeting modifiers - * - * LPES0 is supported on POWER7/8/9 - * LPES1 is not supported (old iSeries mode) - * - * On anything else, we behave as if LPES0 is 1 - * (externals don't alter MSR:HV) - */ -#if defined(TARGET_PPC64) - if (excp_model =3D=3D POWERPC_EXCP_POWER7 || - excp_model =3D=3D POWERPC_EXCP_POWER8 || - excp_model =3D=3D POWERPC_EXCP_POWER9 || - excp_model =3D=3D POWERPC_EXCP_POWER10) { - lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); - } else -#endif /* defined(TARGET_PPC64) */ - { - lpes0 =3D true; - } - - if (!lpes0) { - new_msr |=3D (target_ulong)MSR_HVB; - new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); - srr0 =3D SPR_HSRR0; - srr1 =3D SPR_HSRR1; - } - if (env->mpic_proxy) { - /* IACK the IRQ on delivery */ - env->spr[SPR_BOOKE_EPR] =3D ldl_phys(cs->as, env->mpic_iack); - } break; - } case POWERPC_EXCP_ALIGN: /* Alignment exception = */ /* Get rS/rD and rA from faulting opcode */ /* --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643631487589257.0496704015454; Mon, 31 Jan 2022 04:18:07 -0800 (PST) Received: from localhost ([::1]:36004 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEVdD-00032R-TE for importer@patchew.org; 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Mon, 31 Jan 2022 12:08:43 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 37/41] target/ppc: 74xx: Program exception cleanup Date: Mon, 31 Jan 2022 12:08:07 +0100 Message-Id: <20220131110811.619053-38-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: QoUzGpCerWlF8yvntE46PHqhquuWuJf8 X-Proofpoint-GUID: QoUzGpCerWlF8yvntE46PHqhquuWuJf8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 suspectscore=0 phishscore=0 impostorscore=0 malwarescore=0 mlxlogscore=831 bulkscore=0 adultscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643631489916100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Remove the BookE ESR setting. Signed-off-by: Fabiano Rosas Message-Id: <20220127201116.1154733-6-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b9a1d7ae7e40..bb17b65dc00c 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -650,20 +650,16 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int ex= cp) * precise in the MSR. */ msr |=3D 0x00100000; - env->spr[SPR_BOOKE_ESR] =3D ESR_FP; break; case POWERPC_EXCP_INVAL: trace_ppc_excp_inval(env->nip); msr |=3D 0x00080000; - env->spr[SPR_BOOKE_ESR] =3D ESR_PIL; break; case POWERPC_EXCP_PRIV: msr |=3D 0x00040000; - env->spr[SPR_BOOKE_ESR] =3D ESR_PPR; break; case POWERPC_EXCP_TRAP: msr |=3D 0x00020000; - env->spr[SPR_BOOKE_ESR] =3D ESR_PTR; break; default: /* Should never occur */ --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 31 Jan 2022 11:08:45 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4613FA404D; Mon, 31 Jan 2022 11:08:45 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av23.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:45 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 5A363220149; Mon, 31 Jan 2022 12:08:44 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 38/41] target/ppc: 74xx: System Call exception cleanup Date: Mon, 31 Jan 2022 12:08:08 +0100 Message-Id: <20220131110811.619053-39-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: rA1kGkUZcqTJ0gk0dmvUjqK_XxHzYA9L X-Proofpoint-ORIG-GUID: rA1kGkUZcqTJ0gk0dmvUjqK_XxHzYA9L X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 mlxlogscore=707 lowpriorityscore=0 malwarescore=0 mlxscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.158.5; envelope-from=clg@kaod.org; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643628744810100007 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Remove the BookE code and add a comment explaining why we need to keep hypercall support even though this CPU does not have a hypervisor mode. Signed-off-by: Fabiano Rosas Message-Id: <20220127201116.1154733-7-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index bb17b65dc00c..396e25ed3517 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -556,7 +556,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; target_ulong msr, new_msr, vector; - int srr0, srr1, lev =3D -1; + int srr0, srr1; =20 if (excp <=3D POWERPC_EXCP_NONE || excp >=3D POWERPC_EXCP_NB) { cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); @@ -669,7 +669,8 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) } break; case POWERPC_EXCP_SYSCALL: /* System call exception = */ - lev =3D env->error_code; + { + int lev =3D env->error_code; =20 if ((lev =3D=3D 1) && cpu->vhyp) { dump_hcall(env); @@ -683,17 +684,21 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int ex= cp) */ env->nip +=3D 4; =20 - /* "PAPR mode" built-in hypercall emulation */ + /* + * The Virtual Open Firmware (VOF) relies on the 'sc 1' + * instruction to communicate with QEMU. The pegasos2 machine + * uses VOF and the 74xx CPUs, so although the 74xx don't have + * HV mode, we need to keep hypercall support. + */ if ((lev =3D=3D 1) && cpu->vhyp) { PPCVirtualHypervisorClass *vhc =3D PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); vhc->hypercall(cpu->vhyp, cpu); return; } - if (lev =3D=3D 1) { - new_msr |=3D (target_ulong)MSR_HVB; - } + break; + } case POWERPC_EXCP_FPU: /* Floating-point unavailable exception = */ case POWERPC_EXCP_DECR: /* Decrementer exception = */ break; --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164363090028810.174484142543974; Mon, 31 Jan 2022 04:08:20 -0800 (PST) Received: from localhost ([::1]:51292 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEVTn-0001zW-GI for importer@patchew.org; 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Mon, 31 Jan 2022 11:08:45 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 2E9C82201C1; Mon, 31 Jan 2022 12:08:45 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 39/41] target/ppc: 74xx: System Reset interrupt cleanup Date: Mon, 31 Jan 2022 12:08:09 +0100 Message-Id: <20220131110811.619053-40-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: hyCjFc8gxEuTUEiPy5NXKP3XRvJrj_2f X-Proofpoint-GUID: hyCjFc8gxEuTUEiPy5NXKP3XRvJrj_2f X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=600 suspectscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 malwarescore=0 impostorscore=0 phishscore=0 mlxscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643630902567100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas The whole power saving states logic seems to be dependent on HV mode, which don't exist for 74xx so I'm removing it all and leaving the abort message. Signed-off-by: Fabiano Rosas Message-Id: <20220127201116.1154733-8-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 396e25ed3517..b7921c09562f 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -703,23 +703,9 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int exc= p) case POWERPC_EXCP_DECR: /* Decrementer exception = */ break; case POWERPC_EXCP_RESET: /* System reset exception = */ - /* A power-saving exception sets ME, otherwise it is unchanged */ if (msr_pow) { - /* indicate that we resumed from power save mode */ - msr |=3D 0x10000; - new_msr |=3D ((target_ulong)1 << MSR_ME); - } - if (env->msr_mask & MSR_HVB) { - /* - * ISA specifies HV, but can be delivered to guest with HV - * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU). - */ - new_msr |=3D (target_ulong)MSR_HVB; - } else { - if (msr_pow) { - cpu_abort(cs, "Trying to deliver power-saving system reset= " - "exception %d with no HV support\n", excp); - } + cpu_abort(cs, "Trying to deliver power-saving system reset " + "exception %d with no HV support\n", excp); } break; case POWERPC_EXCP_TRACE: /* Trace exception = */ --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643629724157346.6547908029469; Mon, 31 Jan 2022 03:48:44 -0800 (PST) Received: from localhost ([::1]:52500 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEVAp-00083D-2h for importer@patchew.org; Mon, 31 Jan 2022 06:48:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34586) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUZ2-0006BH-4u; Mon, 31 Jan 2022 06:09:41 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:40158) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEUYy-000571-6n; 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Mon, 31 Jan 2022 11:08:47 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1E77552074; Mon, 31 Jan 2022 11:08:47 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av21.portsmouth.uk.ibm.com (Postfix) with SMTP id BF8A55206D; Mon, 31 Jan 2022 11:08:46 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id EC8E4220149; Mon, 31 Jan 2022 12:08:45 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 40/41] target/ppc: 74xx: Set SRRs directly in exception code Date: Mon, 31 Jan 2022 12:08:10 +0100 Message-Id: <20220131110811.619053-41-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: -lp0uYodAmG9JV3yPVqOBWr_Zb6CeOyY X-Proofpoint-GUID: -lp0uYodAmG9JV3yPVqOBWr_Zb6CeOyY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=404 spamscore=0 lowpriorityscore=0 adultscore=0 clxscore=1034 priorityscore=1501 bulkscore=0 phishscore=0 suspectscore=0 malwarescore=0 mlxscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Fabiano Rosas Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643629726923100002 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas The 74xx does not have alternate/hypervisor Save and Restore Registers, so we can set SRR0 and SRR1 directly. Signed-off-by: Fabiano Rosas Message-Id: <20220127201116.1154733-9-farosas@linux.ibm.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b7921c09562f..4e6bb87b70a3 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -556,7 +556,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; target_ulong msr, new_msr, vector; - int srr0, srr1; =20 if (excp <=3D POWERPC_EXCP_NONE || excp >=3D POWERPC_EXCP_NB) { cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); @@ -575,10 +574,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int exc= p) */ new_msr =3D env->msr & ((target_ulong)1 << MSR_ME); =20 - /* target registers */ - srr0 =3D SPR_SRR0; - srr1 =3D SPR_SRR1; - /* * Hypervisor emulation assistance interrupt only exists on server * arch 2.05 server or later. @@ -731,10 +726,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int exc= p) cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with " "no HV support\n", excp); } - if (srr0 =3D=3D SPR_HSRR0) { - cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with " - "no HV support\n", excp); - } } =20 /* @@ -746,10 +737,10 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int ex= cp) } =20 /* Save PC */ - env->spr[srr0] =3D env->nip; + env->spr[SPR_SRR0] =3D env->nip; =20 /* Save MSR */ - env->spr[srr1] =3D msr; + env->spr[SPR_SRR1] =3D msr; =20 powerpc_set_excp_state(cpu, vector, new_msr); } --=20 2.34.1 From nobody Sat May 18 01:36:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 31 Jan 2022 11:08:47 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7C8F24C052; Mon, 31 Jan 2022 11:08:47 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av22.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 31 Jan 2022 11:08:47 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.57.185]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id B24652201C1; Mon, 31 Jan 2022 12:08:46 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 41/41] target/ppc: Remove support for the PowerPC 602 CPU Date: Mon, 31 Jan 2022 12:08:11 +0100 Message-Id: <20220131110811.619053-42-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220131110811.619053-1-clg@kaod.org> References: <20220131110811.619053-1-clg@kaod.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 4fapoekuh-ko-y5P3kebBgQB0UEYxHsb X-Proofpoint-GUID: 4fapoekuh-ko-y5P3kebBgQB0UEYxHsb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 phishscore=0 impostorscore=0 priorityscore=1501 spamscore=0 clxscore=1034 bulkscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201310074 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.158.5; envelope-from=clg@kaod.org; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, TVD_SUBJ_WIPE_DEBT=1.004, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643631259212100001 Content-Type: text/plain; charset="utf-8" The 602 was derived from the PowerPC 603, for the gaming market it seems. It was hardly used and no firmware supporting the CPU could be found. Drop support. Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/cpu-models.h | 1 - target/ppc/cpu.h | 8 +- target/ppc/helper.h | 1 - target/ppc/cpu-models.c | 2 - target/ppc/cpu_init.c | 147 ----------------------------------- target/ppc/excp_helper.c | 1 - target/ppc/int_helper.c | 21 ----- target/ppc/mfrom_table_gen.c | 34 -------- target/ppc/translate.c | 30 ------- target/ppc/mfrom_table.c.inc | 78 ------------------- 10 files changed, 1 insertion(+), 322 deletions(-) delete mode 100644 target/ppc/mfrom_table_gen.c delete mode 100644 target/ppc/mfrom_table.c.inc diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index bf1dc7e5ca3d..612978a3fbd2 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -208,7 +208,6 @@ enum { CPU_POWERPC_601_v0 =3D 0x00010001, CPU_POWERPC_601_v1 =3D 0x00010001, CPU_POWERPC_601_v2 =3D 0x00010002, - CPU_POWERPC_602 =3D 0x00050100, CPU_POWERPC_603 =3D 0x00030100, CPU_POWERPC_603E_v11 =3D 0x00060101, CPU_POWERPC_603E_v12 =3D 0x00060102, diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 66e13075c3df..dcd83b503c62 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -321,9 +321,7 @@ typedef enum { #define MSR_UCLE 26 /* User-mode cache lock enable for BookE = */ #define MSR_VR 25 /* altivec available x hfla= gs */ #define MSR_SPE 25 /* SPE enable for BookE x hfla= gs */ -#define MSR_AP 23 /* Access privilege state on 602 hfla= gs */ #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hfla= gs */ -#define MSR_SA 22 /* Supervisor access mode on 602 hfla= gs */ #define MSR_S 22 /* Secure state = */ #define MSR_KEY 19 /* key bit on 603e = */ #define MSR_POW 18 /* Power management = */ @@ -477,9 +475,7 @@ typedef enum { #define msr_ucle ((env->msr >> MSR_UCLE) & 1) #define msr_vr ((env->msr >> MSR_VR) & 1) #define msr_spe ((env->msr >> MSR_SPE) & 1) -#define msr_ap ((env->msr >> MSR_AP) & 1) #define msr_vsx ((env->msr >> MSR_VSX) & 1) -#define msr_sa ((env->msr >> MSR_SA) & 1) #define msr_key ((env->msr >> MSR_KEY) & 1) #define msr_pow ((env->msr >> MSR_POW) & 1) #define msr_tgpr ((env->msr >> MSR_TGPR) & 1) @@ -2142,8 +2138,6 @@ enum { PPC_MFTB =3D 0x0000000000000200ULL, =20 /* Fixed-point unit extensions = */ - /* PowerPC 602 specific = */ - PPC_602_SPEC =3D 0x0000000000000400ULL, /* isel instruction = */ PPC_ISEL =3D 0x0000000000000800ULL, /* popcntb instruction = */ @@ -2245,7 +2239,7 @@ enum { #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \ | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \ | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \ - | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \ + | PPC_ISEL | PPC_POPCNTB \ | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \ | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \ | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index bdbbd5e1d90f..f2e5060910de 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -646,7 +646,6 @@ DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, = tl) DEF_HELPER_FLAGS_2(load_sr, TCG_CALL_NO_RWG, tl, env, tl) DEF_HELPER_FLAGS_3(store_sr, TCG_CALL_NO_RWG, void, env, tl, tl) =20 -DEF_HELPER_FLAGS_1(602_mfrom, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_1(msgsnd, void, tl) DEF_HELPER_2(msgclr, void, env, tl) DEF_HELPER_1(book3s_msgsnd, void, tl) diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index 764afe5a2afb..a2c720cc4d0c 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -428,8 +428,6 @@ "PowerPC 601v1") POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v, "PowerPC 601v2") - POWERPC_DEF("602", CPU_POWERPC_602, 602, - "PowerPC 602") POWERPC_DEF("603", CPU_POWERPC_603, 603, "PowerPC 603") POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 23a13036b211..bf60529d3715 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -749,54 +749,6 @@ static void register_G2_sprs(CPUPPCState *env) 0x00000000); } =20 -/* SPR specific to PowerPC 602 implementation */ -static void register_602_sprs(CPUPPCState *env) -{ - /* ESA registers */ - /* XXX : not implemented */ - spr_register(env, SPR_SER, "SER", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_SEBR, "SEBR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_ESASRR, "ESASRR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Floating point status */ - /* XXX : not implemented */ - spr_register(env, SPR_SP, "SP", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_LT, "LT", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Watchdog timer */ - /* XXX : not implemented */ - spr_register(env, SPR_TCR, "TCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Interrupt base */ - spr_register(env, SPR_IBR, "IBR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_IABR, "IABR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - /* SPR specific to PowerPC 601 implementation */ static void register_601_sprs(CPUPPCState *env) { @@ -2128,33 +2080,6 @@ static void init_excp_601(CPUPPCState *env) #endif } =20 -static void init_excp_602(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - /* XXX: exception prefix has a special behavior on 602 */ - env->excp_vectors[POWERPC_EXCP_RESET] =3D 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] =3D 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] =3D 0x00000300; - env->excp_vectors[POWERPC_EXCP_ISI] =3D 0x00000400; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] =3D 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] =3D 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] =3D 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] =3D 0x00000800; - env->excp_vectors[POWERPC_EXCP_DECR] =3D 0x00000900; - env->excp_vectors[POWERPC_EXCP_SYSCALL] =3D 0x00000C00; - env->excp_vectors[POWERPC_EXCP_TRACE] =3D 0x00000D00; - env->excp_vectors[POWERPC_EXCP_IFTLB] =3D 0x00001000; - env->excp_vectors[POWERPC_EXCP_DLTLB] =3D 0x00001100; - env->excp_vectors[POWERPC_EXCP_DSTLB] =3D 0x00001200; - env->excp_vectors[POWERPC_EXCP_IABR] =3D 0x00001300; - env->excp_vectors[POWERPC_EXCP_SMI] =3D 0x00001400; - env->excp_vectors[POWERPC_EXCP_WDT] =3D 0x00001500; - env->excp_vectors[POWERPC_EXCP_EMUL] =3D 0x00001600; - /* Hardware reset vector */ - env->hreset_vector =3D 0x00000100UL; -#endif -} - static void init_excp_603(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) @@ -4081,76 +4006,6 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) pcc->flags =3D POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_H= ID0_LE; } =20 -static void init_proc_602(CPUPPCState *env) -{ - register_ne_601_sprs(env); - register_sdr1_sprs(env); - register_602_sprs(env); - /* Time base */ - register_tbl(env); - /* hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - register_low_BATs(env); - register_6xx_7xx_soft_tlb(env, 64, 2); - init_excp_602(env); - env->dcache_line_size =3D 32; - env->icache_line_size =3D 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(602)(ObjectClass *oc, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(oc); - PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); - - dc->desc =3D "PowerPC 602"; - pcc->init_proc =3D init_proc_602; - pcc->check_pow =3D check_pow_hid0; - pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_602_SPEC; - pcc->msr_mask =3D (1ull << MSR_VSX) | - (1ull << MSR_SA) | - (1ull << MSR_POW) | - (1ull << MSR_TGPR) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - /* XXX: 602 MMU is quite specific. Should add a special case */ - pcc->mmu_model =3D POWERPC_MMU_SOFT_6xx; - pcc->excp_model =3D POWERPC_EXCP_602; - pcc->bus_model =3D PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach =3D bfd_mach_ppc_602; - pcc->flags =3D POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; -} - static void init_proc_603(CPUPPCState *env) { register_ne_601_sprs(env); @@ -8271,8 +8126,6 @@ static void ppc_cpu_reset(DeviceState *dev) =20 msr =3D (target_ulong)0; msr |=3D (target_ulong)MSR_HVB; - msr |=3D (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ - msr |=3D (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ msr |=3D (target_ulong)1 << MSR_EP; #if defined(DO_SINGLE_STEP) && 0 /* Single step trace mode */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 4e6bb87b70a3..c107953dec10 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1422,7 +1422,6 @@ static inline void powerpc_excp_legacy(PowerPCCPU *cp= u, int excp) case POWERPC_EXCP_DLTLB: /* Data load TLB miss = */ case POWERPC_EXCP_DSTLB: /* Data store TLB miss = */ switch (excp_model) { - case POWERPC_EXCP_602: case POWERPC_EXCP_603: case POWERPC_EXCP_G2: /* Swap temporary saved registers with GPRs */ diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 9bc327bcba5a..d7765fd3e3d8 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -488,27 +488,6 @@ target_ulong helper_divso(CPUPPCState *env, target_ulo= ng arg1, } } =20 -/*************************************************************************= ****/ -/* 602 specific instructions */ -/* mfrom is the most crazy instruction ever seen, imho ! */ -/* Real implementation uses a ROM table. Do the same */ -/* - * Extremely decomposed: - * -arg / 256 - * return 256 * log10(10 + 1.0) + 0.5 - */ -#if !defined(CONFIG_USER_ONLY) -target_ulong helper_602_mfrom(target_ulong arg) -{ - if (likely(arg < 602)) { -#include "mfrom_table.c.inc" - return mfrom_ROM_table[arg]; - } else { - return 0; - } -} -#endif - /*************************************************************************= ****/ /* Altivec extension helpers */ #if defined(HOST_WORDS_BIGENDIAN) diff --git a/target/ppc/mfrom_table_gen.c b/target/ppc/mfrom_table_gen.c deleted file mode 100644 index f96c4268ba70..000000000000 --- a/target/ppc/mfrom_table_gen.c +++ /dev/null @@ -1,34 +0,0 @@ -#define _GNU_SOURCE -#include "qemu/osdep.h" -#include - -int main(void) -{ - double d; - uint8_t n; - int i; - - printf("static const uint8_t mfrom_ROM_table[602] =3D\n{\n "); - for (i =3D 0; i < 602; i++) { - /* - * Extremely decomposed: - * -T0 / 256 - * T0 =3D 256 * log10(10 + 1.0) + 0.5 - */ - d =3D -i; - d /=3D 256.0; - d =3D exp10(d); - d +=3D 1.0; - d =3D log10(d); - d *=3D 256; - d +=3D 0.5; - n =3D d; - printf("%3d, ", n); - if ((i & 7) =3D=3D 7) { - printf("\n "); - } - } - printf("\n};\n"); - - return 0; -} diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d61c6f0e8f91..c2f436f8d3bc 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6272,33 +6272,6 @@ static void gen_srq(DisasContext *ctx) } } =20 -/* PowerPC 602 specific instructions */ - -/* dsa */ -static void gen_dsa(DisasContext *ctx) -{ - /* XXX: TODO */ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); -} - -/* esa */ -static void gen_esa(DisasContext *ctx) -{ - /* XXX: TODO */ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); -} - -/* mfrom */ -static void gen_mfrom(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV; -#else - CHK_SV; - gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)= ]); -#endif /* defined(CONFIG_USER_ONLY) */ -} - /* 602 - 603 - G2 TLB management */ =20 /* tlbld */ @@ -7779,9 +7752,6 @@ GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_P= OWER_BR), GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), -GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), -GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), -GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB= ), GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB= ), GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), diff --git a/target/ppc/mfrom_table.c.inc b/target/ppc/mfrom_table.c.inc deleted file mode 100644 index 1653b974a434..000000000000 --- a/target/ppc/mfrom_table.c.inc +++ /dev/null @@ -1,78 +0,0 @@ -static const uint8_t mfrom_ROM_table[602] =3D { - 77, 77, 76, 76, 75, 75, 74, 74, - 73, 73, 72, 72, 71, 71, 70, 70, - 69, 69, 68, 68, 68, 67, 67, 66, - 66, 65, 65, 64, 64, 64, 63, 63, - 62, 62, 61, 61, 61, 60, 60, 59, - 59, 58, 58, 58, 57, 57, 56, 56, - 56, 55, 55, 54, 54, 54, 53, 53, - 53, 52, 52, 51, 51, 51, 50, 50, - 50, 49, 49, 49, 48, 48, 47, 47, - 47, 46, 46, 46, 45, 45, 45, 44, - 44, 44, 43, 43, 43, 42, 42, 42, - 42, 41, 41, 41, 40, 40, 40, 39, - 39, 39, 39, 38, 38, 38, 37, 37, - 37, 37, 36, 36, 36, 35, 35, 35, - 35, 34, 34, 34, 34, 33, 33, 33, - 33, 32, 32, 32, 32, 31, 31, 31, - 31, 30, 30, 30, 30, 29, 29, 29, - 29, 28, 28, 28, 28, 28, 27, 27, - 27, 27, 26, 26, 26, 26, 26, 25, - 25, 25, 25, 25, 24, 24, 24, 24, - 24, 23, 23, 23, 23, 23, 23, 22, - 22, 22, 22, 22, 21, 21, 21, 21, - 21, 21, 20, 20, 20, 20, 20, 20, - 19, 19, 19, 19, 19, 19, 19, 18, - 18, 18, 18, 18, 18, 17, 17, 17, - 17, 17, 17, 17, 16, 16, 16, 16, - 16, 16, 16, 16, 15, 15, 15, 15, - 15, 15, 15, 15, 14, 14, 14, 14, - 14, 14, 14, 14, 13, 13, 13, 13, - 13, 13, 13, 13, 13, 12, 12, 12, - 12, 12, 12, 12, 12, 12, 12, 11, - 11, 11, 11, 11, 11, 11, 11, 11, - 11, 11, 10, 10, 10, 10, 10, 10, - 10, 10, 10, 10, 10, 9, 9, 9, - 9, 9, 9, 9, 9, 9, 9, 9, - 9, 9, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, - 7, 7, 7, 7, 7, 7, 7, 7, - 7, 7, 7, 7, 7, 7, 7, 7, - 7, 6, 6, 6, 6, 6, 6, 6, - 6, 6, 6, 6, 6, 6, 6, 6, - 6, 6, 6, 6, 5, 5, 5, 5, - 5, 5, 5, 5, 5, 5, 5, 5, - 5, 5, 5, 5, 5, 5, 5, 5, - 5, 5, 5, 4, 4, 4, 4, 4, - 4, 4, 4, 4, 4, 4, 4, 4, - 4, 4, 4, 4, 4, 4, 4, 4, - 4, 4, 4, 4, 4, 4, 4, 3, - 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 0, -}; --=20 2.34.1