From nobody Sun Apr 28 21:56:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643317118340740.4818620644596; Thu, 27 Jan 2022 12:58:38 -0800 (PST) Received: from localhost ([::1]:34836 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nDBql-0001pd-3j for importer@patchew.org; Thu, 27 Jan 2022 15:58:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34376) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBmh-0007L3-01 for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:23 -0500 Received: from [2001:41c9:1:41f::167] (port=36804 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBmf-0004uv-LZ for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:22 -0500 Received: from [2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe] (helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nDBm9-000BHM-RW; Thu, 27 Jan 2022 20:53:54 +0000 From: Mark Cave-Ayland To: laurent@vivier.eu, qemu-devel@nongnu.org Date: Thu, 27 Jan 2022 20:53:55 +0000 Message-Id: <20220127205405.23499-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> References: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH 01/11] mos6522: add defines for IFR bit flags X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) X-Host-Lookup-Failed: Reverse DNS lookup failed for 2001:41c9:1:41f::167 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643317120177100001 Content-Type: text/plain; charset="utf-8" These are intended to make it easier to see how the physical control lines are wired for each instance. Signed-off-by: Mark Cave-Ayland --- include/hw/misc/mos6522.h | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h index fc95d22b0f..12abd8b8d2 100644 --- a/include/hw/misc/mos6522.h +++ b/include/hw/misc/mos6522.h @@ -41,13 +41,21 @@ #define IER_SET 0x80 /* set bits in IER */ #define IER_CLR 0 /* clear bits in IER */ =20 -#define CA2_INT 0x01 -#define CA1_INT 0x02 -#define SR_INT 0x04 /* Shift register full/empty */ -#define CB2_INT 0x08 -#define CB1_INT 0x10 -#define T2_INT 0x20 /* Timer 2 interrupt */ -#define T1_INT 0x40 /* Timer 1 interrupt */ +#define CA2_INT_BIT 0 +#define CA1_INT_BIT 1 +#define SR_INT_BIT 2 /* Shift register full/empty */ +#define CB2_INT_BIT 3 +#define CB1_INT_BIT 4 +#define T2_INT_BIT 5 /* Timer 2 interrupt */ +#define T1_INT_BIT 6 /* Timer 1 interrupt */ + +#define CA2_INT (1 << CA2_INT_BIT) +#define CA1_INT (1 << CA1_INT_BIT) +#define SR_INT (1 << SR_INT_BIT) +#define CB2_INT (1 << CB2_INT_BIT) +#define CB1_INT (1 << CB1_INT_BIT) +#define T2_INT (1 << T2_INT_BIT) +#define T1_INT (1 << T1_INT_BIT) =20 /* Bits in ACR */ #define T1MODE 0xc0 /* Timer 1 mode */ --=20 2.20.1 From nobody Sun Apr 28 21:56:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643317381627661.8774361911927; Thu, 27 Jan 2022 13:03:01 -0800 (PST) Received: from localhost ([::1]:42996 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nDBv2-00089x-US for importer@patchew.org; Thu, 27 Jan 2022 16:03:00 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34394) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBmk-0007Tz-S7 for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:26 -0500 Received: from [2001:41c9:1:41f::167] (port=36808 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBmj-0004vb-Aj for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:26 -0500 Received: from [2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe] (helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nDBmE-000BHM-2k; Thu, 27 Jan 2022 20:53:58 +0000 From: Mark Cave-Ayland To: laurent@vivier.eu, qemu-devel@nongnu.org Date: Thu, 27 Jan 2022 20:53:56 +0000 Message-Id: <20220127205405.23499-3-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> References: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH 02/11] mac_via: use IFR bit flag constants for VIA1 IRQs X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) X-Host-Lookup-Failed: Reverse DNS lookup failed for 2001:41c9:1:41f::167 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643317383382100001 Content-Type: text/plain; charset="utf-8" This allows us to easily see how the physical control lines are mapped to t= he IFR bit flags. Signed-off-by: Mark Cave-Ayland --- include/hw/misc/mac_via.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/hw/misc/mac_via.h b/include/hw/misc/mac_via.h index b445565866..b0c3825c9b 100644 --- a/include/hw/misc/mac_via.h +++ b/include/hw/misc/mac_via.h @@ -18,11 +18,11 @@ #define VIA_SIZE 0x2000 =20 /* VIA 1 */ -#define VIA1_IRQ_ONE_SECOND_BIT 0 -#define VIA1_IRQ_60HZ_BIT 1 -#define VIA1_IRQ_ADB_READY_BIT 2 -#define VIA1_IRQ_ADB_DATA_BIT 3 -#define VIA1_IRQ_ADB_CLOCK_BIT 4 +#define VIA1_IRQ_ONE_SECOND_BIT CA2_INT_BIT +#define VIA1_IRQ_60HZ_BIT CA1_INT_BIT +#define VIA1_IRQ_ADB_READY_BIT SR_INT_BIT +#define VIA1_IRQ_ADB_DATA_BIT CB2_INT_BIT +#define VIA1_IRQ_ADB_CLOCK_BIT CB1_INT_BIT =20 #define VIA1_IRQ_NB 8 =20 --=20 2.20.1 From nobody Sun Apr 28 21:56:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643317178801708.2173841940099; Thu, 27 Jan 2022 12:59:38 -0800 (PST) Received: from localhost ([::1]:35824 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nDBrl-0002lA-W3 for importer@patchew.org; Thu, 27 Jan 2022 15:59:38 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34424) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBmo-0007dh-G6 for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:30 -0500 Received: from [2001:41c9:1:41f::167] (port=36814 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBmn-0004vl-41 for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:30 -0500 Received: from [2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe] (helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nDBmI-000BHM-9I; Thu, 27 Jan 2022 20:54:02 +0000 From: Mark Cave-Ayland To: laurent@vivier.eu, qemu-devel@nongnu.org Date: Thu, 27 Jan 2022 20:53:57 +0000 Message-Id: <20220127205405.23499-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> References: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH 03/11] mac_via: use IFR bit flag constants for VIA2 IRQs X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) X-Host-Lookup-Failed: Reverse DNS lookup failed for 2001:41c9:1:41f::167 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643317181788100003 Content-Type: text/plain; charset="utf-8" This allows us to easily see how the physical control lines are mapped to t= he IFR bit flags. Signed-off-by: Mark Cave-Ayland --- include/hw/misc/mac_via.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/hw/misc/mac_via.h b/include/hw/misc/mac_via.h index b0c3825c9b..2df1ab01b6 100644 --- a/include/hw/misc/mac_via.h +++ b/include/hw/misc/mac_via.h @@ -80,11 +80,10 @@ struct MOS6522Q800VIA1State { =20 =20 /* VIA 2 */ -#define VIA2_IRQ_SCSI_DATA_BIT 0 -#define VIA2_IRQ_NUBUS_BIT 1 -#define VIA2_IRQ_UNUSED_BIT 2 -#define VIA2_IRQ_SCSI_BIT 3 -#define VIA2_IRQ_ASC_BIT 4 +#define VIA2_IRQ_SCSI_DATA_BIT CA2_INT_BIT +#define VIA2_IRQ_NUBUS_BIT CA1_INT_BIT +#define VIA2_IRQ_SCSI_BIT CB2_INT_BIT +#define VIA2_IRQ_ASC_BIT CB1_INT_BIT =20 #define VIA2_IRQ_NB 8 =20 --=20 2.20.1 From nobody Sun Apr 28 21:56:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643317183741264.1093293950978; Thu, 27 Jan 2022 12:59:43 -0800 (PST) Received: from localhost ([::1]:36040 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nDBrq-0002tt-Rp for importer@patchew.org; Thu, 27 Jan 2022 15:59:42 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34434) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBmp-0007i6-V7 for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:31 -0500 Received: from [2001:41c9:1:41f::167] (port=36820 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBmn-0004vn-IS for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:31 -0500 Received: from [2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe] (helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nDBmM-000BHM-Eg; Thu, 27 Jan 2022 20:54:02 +0000 From: Mark Cave-Ayland To: laurent@vivier.eu, qemu-devel@nongnu.org Date: Thu, 27 Jan 2022 20:53:58 +0000 Message-Id: <20220127205405.23499-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> References: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH 04/11] mos6522: switch over to use qdev gpios for IRQs X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) X-Host-Lookup-Failed: Reverse DNS lookup failed for 2001:41c9:1:41f::167 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643317186994100001 Content-Type: text/plain; charset="utf-8" For historical reasons each mos6522 instance implements its own setting and update of the IFR flag bits using methods exposed by MOS6522DeviceClass. As of today this is no longer required, and it is now possible to implement the mos6522 IRQs as standard qdev gpios. Switch over to use qdev gpios for the mos6522 device and update all instanc= es accordingly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/misc/mac_via.c | 56 +++++++-------------------------------- hw/misc/macio/cuda.c | 5 ++-- hw/misc/macio/pmu.c | 4 +-- hw/misc/mos6522.c | 15 +++++++++++ include/hw/misc/mac_via.h | 6 +---- include/hw/misc/mos6522.h | 2 ++ 6 files changed, 32 insertions(+), 56 deletions(-) diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index b378e6b305..0756374f1b 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -325,10 +325,9 @@ static void via1_sixty_hz(void *opaque) { MOS6522Q800VIA1State *v1s =3D opaque; MOS6522State *s =3D MOS6522(v1s); - MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(s); + qemu_irq irq =3D qdev_get_gpio_in(DEVICE(s), VIA1_IRQ_60HZ_BIT); =20 - s->ifr |=3D VIA1_IRQ_60HZ; - mdc->update_irq(s); + qemu_set_irq(irq, 1); =20 via1_sixty_hz_update(v1s); } @@ -337,44 +336,13 @@ static void via1_one_second(void *opaque) { MOS6522Q800VIA1State *v1s =3D opaque; MOS6522State *s =3D MOS6522(v1s); - MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(s); + qemu_irq irq =3D qdev_get_gpio_in(DEVICE(s), VIA1_IRQ_ONE_SECOND_BIT); =20 - s->ifr |=3D VIA1_IRQ_ONE_SECOND; - mdc->update_irq(s); + qemu_set_irq(irq, 1); =20 via1_one_second_update(v1s); } =20 -static void via1_irq_request(void *opaque, int irq, int level) -{ - MOS6522Q800VIA1State *v1s =3D opaque; - MOS6522State *s =3D MOS6522(v1s); - MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(s); - - if (level) { - s->ifr |=3D 1 << irq; - } else { - s->ifr &=3D ~(1 << irq); - } - - mdc->update_irq(s); -} - -static void via2_irq_request(void *opaque, int irq, int level) -{ - MOS6522Q800VIA2State *v2s =3D opaque; - MOS6522State *s =3D MOS6522(v2s); - MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(s); - - if (level) { - s->ifr |=3D 1 << irq; - } else { - s->ifr &=3D ~(1 << irq); - } - - mdc->update_irq(s); -} - =20 static void pram_update(MOS6522Q800VIA1State *v1s) { @@ -1061,8 +1029,6 @@ static void mos6522_q800_via1_init(Object *obj) qbus_init((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus), TYPE_ADB_BUS, DEVICE(v1s), "adb.0"); =20 - qdev_init_gpio_in(DEVICE(obj), via1_irq_request, VIA1_IRQ_NB); - /* A/UX mode */ qdev_init_gpio_out(DEVICE(obj), &v1s->auxmode_irq, 1); } @@ -1150,22 +1116,20 @@ static void mos6522_q800_via2_reset(DeviceState *de= v) ms->a =3D 0x7f; } =20 -static void via2_nubus_irq_request(void *opaque, int irq, int level) +static void via2_nubus_irq_request(void *opaque, int n, int level) { MOS6522Q800VIA2State *v2s =3D opaque; MOS6522State *s =3D MOS6522(v2s); - MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(s); + qemu_irq irq =3D qdev_get_gpio_in(DEVICE(s), VIA2_IRQ_NUBUS_BIT); =20 if (level) { /* Port A nubus IRQ inputs are active LOW */ - s->a &=3D ~(1 << irq); - s->ifr |=3D 1 << VIA2_IRQ_NUBUS_BIT; + s->a &=3D ~(1 << n); } else { - s->a |=3D (1 << irq); - s->ifr &=3D ~(1 << VIA2_IRQ_NUBUS_BIT); + s->a |=3D (1 << n); } =20 - mdc->update_irq(s); + qemu_set_irq(irq, level); } =20 static void mos6522_q800_via2_init(Object *obj) @@ -1177,8 +1141,6 @@ static void mos6522_q800_via2_init(Object *obj) "via2", VIA_SIZE); sysbus_init_mmio(sbd, &v2s->via_mem); =20 - qdev_init_gpio_in(DEVICE(obj), via2_irq_request, VIA2_IRQ_NB); - qdev_init_gpio_in_named(DEVICE(obj), via2_nubus_irq_request, "nubus-ir= q", VIA2_NUBUS_IRQ_NB); } diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index e917a6a095..f76d9227d3 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -25,6 +25,7 @@ =20 #include "qemu/osdep.h" #include "qemu-common.h" +#include "hw/irq.h" #include "hw/ppc/mac.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -96,9 +97,9 @@ static void cuda_set_sr_int(void *opaque) CUDAState *s =3D opaque; MOS6522CUDAState *mcs =3D &s->mos6522_cuda; MOS6522State *ms =3D MOS6522(mcs); - MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(ms); + qemu_irq irq =3D qdev_get_gpio_in(DEVICE(ms), SR_INT_BIT); =20 - mdc->set_sr_int(ms); + qemu_set_irq(irq, 1); } =20 static void cuda_delay_set_sr_int(CUDAState *s) diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c index eb39c64694..6e80fe1cfa 100644 --- a/hw/misc/macio/pmu.c +++ b/hw/misc/macio/pmu.c @@ -75,9 +75,9 @@ static void via_set_sr_int(void *opaque) PMUState *s =3D opaque; MOS6522PMUState *mps =3D MOS6522_PMU(&s->mos6522_pmu); MOS6522State *ms =3D MOS6522(mps); - MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(ms); + qemu_irq irq =3D qdev_get_gpio_in(DEVICE(ms), SR_INT_BIT); =20 - mdc->set_sr_int(ms); + qemu_set_irq(irq, 1); } =20 static void pmu_update_extirq(PMUState *s) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 1c57332b40..6be6853dc2 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -52,6 +52,19 @@ static void mos6522_update_irq(MOS6522State *s) } } =20 +static void mos6522_set_irq(void *opaque, int n, int level) +{ + MOS6522State *s =3D MOS6522(opaque); + + if (level) { + s->ifr |=3D 1 << n; + } else { + s->ifr &=3D ~(1 << n); + } + + mos6522_update_irq(s); +} + static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti) { MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(s); @@ -488,6 +501,8 @@ static void mos6522_init(Object *obj) =20 s->timers[0].timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1= , s); s->timers[1].timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2= , s); + + qdev_init_gpio_in(DEVICE(obj), mos6522_set_irq, VIA_NUM_INTS); } =20 static void mos6522_finalize(Object *obj) diff --git a/include/hw/misc/mac_via.h b/include/hw/misc/mac_via.h index 2df1ab01b6..bffeba38ee 100644 --- a/include/hw/misc/mac_via.h +++ b/include/hw/misc/mac_via.h @@ -24,8 +24,6 @@ #define VIA1_IRQ_ADB_DATA_BIT CB2_INT_BIT #define VIA1_IRQ_ADB_CLOCK_BIT CB1_INT_BIT =20 -#define VIA1_IRQ_NB 8 - #define VIA1_IRQ_ONE_SECOND (1 << VIA1_IRQ_ONE_SECOND_BIT) #define VIA1_IRQ_60HZ (1 << VIA1_IRQ_60HZ_BIT) #define VIA1_IRQ_ADB_READY (1 << VIA1_IRQ_ADB_READY_BIT) @@ -42,7 +40,7 @@ struct MOS6522Q800VIA1State { =20 MemoryRegion via_mem; =20 - qemu_irq irqs[VIA1_IRQ_NB]; + qemu_irq irqs[VIA_NUM_INTS]; qemu_irq auxmode_irq; uint8_t last_b; =20 @@ -85,8 +83,6 @@ struct MOS6522Q800VIA1State { #define VIA2_IRQ_SCSI_BIT CB2_INT_BIT #define VIA2_IRQ_ASC_BIT CB1_INT_BIT =20 -#define VIA2_IRQ_NB 8 - #define VIA2_IRQ_SCSI_DATA (1 << VIA2_IRQ_SCSI_DATA_BIT) #define VIA2_IRQ_NUBUS (1 << VIA2_IRQ_NUBUS_BIT) #define VIA2_IRQ_UNUSED (1 << VIA2_IRQ_SCSI_BIT) diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h index 12abd8b8d2..ced8a670bf 100644 --- a/include/hw/misc/mos6522.h +++ b/include/hw/misc/mos6522.h @@ -57,6 +57,8 @@ #define T2_INT (1 << T2_INT_BIT) #define T1_INT (1 << T1_INT_BIT) =20 +#define VIA_NUM_INTS 5 + /* Bits in ACR */ #define T1MODE 0xc0 /* Timer 1 mode */ #define T1MODE_CONT 0x40 /* continuous interrupts */ --=20 2.20.1 From nobody Sun Apr 28 21:56:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643317398080681.8158516566072; Thu, 27 Jan 2022 13:03:18 -0800 (PST) Received: from localhost ([::1]:44402 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nDBvJ-0000iD-6i for importer@patchew.org; Thu, 27 Jan 2022 16:03:17 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34460) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBmt-0007uw-Hg for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:35 -0500 Received: from [2001:41c9:1:41f::167] (port=36828 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBms-0004w7-3H for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:35 -0500 Received: from [2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe] (helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nDBmM-000BHM-Ts; Thu, 27 Jan 2022 20:54:07 +0000 From: Mark Cave-Ayland To: laurent@vivier.eu, qemu-devel@nongnu.org Date: Thu, 27 Jan 2022 20:53:59 +0000 Message-Id: <20220127205405.23499-6-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> References: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH 05/11] mos6522: remove update_irq() and set_sr_int() methods from MOS6522DeviceClass X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) X-Host-Lookup-Failed: Reverse DNS lookup failed for 2001:41c9:1:41f::167 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643317400113100001 Content-Type: text/plain; charset="utf-8" Now that the mos6522 IRQs are managed using standard qdev gpios these metho= ds are no longer required. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/misc/mos6522.c | 9 --------- include/hw/misc/mos6522.h | 2 -- 2 files changed, 11 deletions(-) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 6be6853dc2..4c3147a7d1 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -208,13 +208,6 @@ static void mos6522_timer2(void *opaque) mos6522_update_irq(s); } =20 -static void mos6522_set_sr_int(MOS6522State *s) -{ - trace_mos6522_set_sr_int(); - s->ifr |=3D SR_INT; - mos6522_update_irq(s); -} - static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *t= i) { return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, @@ -527,10 +520,8 @@ static void mos6522_class_init(ObjectClass *oc, void *= data) dc->vmsd =3D &vmstate_mos6522; device_class_set_props(dc, mos6522_properties); mdc->parent_reset =3D dc->reset; - mdc->set_sr_int =3D mos6522_set_sr_int; mdc->portB_write =3D mos6522_portB_write; mdc->portA_write =3D mos6522_portA_write; - mdc->update_irq =3D mos6522_update_irq; mdc->get_timer1_counter_value =3D mos6522_get_counter_value; mdc->get_timer2_counter_value =3D mos6522_get_counter_value; mdc->get_timer1_load_time =3D mos6522_get_load_time; diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h index ced8a670bf..f6b513a3a2 100644 --- a/include/hw/misc/mos6522.h +++ b/include/hw/misc/mos6522.h @@ -140,10 +140,8 @@ struct MOS6522DeviceClass { DeviceClass parent_class; =20 DeviceReset parent_reset; - void (*set_sr_int)(MOS6522State *dev); void (*portB_write)(MOS6522State *dev); void (*portA_write)(MOS6522State *dev); - void (*update_irq)(MOS6522State *dev); /* These are used to influence the CUDA MacOS timebase calibration */ uint64_t (*get_timer1_counter_value)(MOS6522State *dev, MOS6522Timer *= ti); uint64_t (*get_timer2_counter_value)(MOS6522State *dev, MOS6522Timer *= ti); --=20 2.20.1 From nobody Sun Apr 28 21:56:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643317401170475.4056541913576; Thu, 27 Jan 2022 13:03:21 -0800 (PST) Received: from localhost ([::1]:44740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nDBvM-0000vR-Dk for importer@patchew.org; Thu, 27 Jan 2022 16:03:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34462) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBmt-0007wU-UM for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:35 -0500 Received: from [2001:41c9:1:41f::167] (port=36834 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBms-0004w9-AD for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:35 -0500 Received: from [2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe] (helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nDBmR-000BHM-3s; Thu, 27 Jan 2022 20:54:07 +0000 From: Mark Cave-Ayland To: laurent@vivier.eu, qemu-devel@nongnu.org Date: Thu, 27 Jan 2022 20:54:00 +0000 Message-Id: <20220127205405.23499-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> References: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH 06/11] mos6522: use device_class_set_parent_reset() to propagate reset to parent X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) X-Host-Lookup-Failed: Reverse DNS lookup failed for 2001:41c9:1:41f::167 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643317402842100001 Content-Type: text/plain; charset="utf-8" Switch from using a legacy approach to the more formal approach for propaga= ting device reset to the parent. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/misc/mac_via.c | 7 +++++-- hw/misc/macio/cuda.c | 3 ++- hw/misc/macio/pmu.c | 3 ++- hw/misc/mos6522.c | 1 - 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index 0756374f1b..95cf2e03d9 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -1076,9 +1076,11 @@ static Property mos6522_q800_via1_properties[] =3D { static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); + MOS6522DeviceClass *mdc =3D MOS6522_CLASS(oc); =20 dc->realize =3D mos6522_q800_via1_realize; - dc->reset =3D mos6522_q800_via1_reset; + device_class_set_parent_reset(dc, mos6522_q800_via1_reset, + &mdc->parent_reset); dc->vmsd =3D &vmstate_q800_via1; device_class_set_props(dc, mos6522_q800_via1_properties); } @@ -1161,7 +1163,8 @@ static void mos6522_q800_via2_class_init(ObjectClass = *oc, void *data) DeviceClass *dc =3D DEVICE_CLASS(oc); MOS6522DeviceClass *mdc =3D MOS6522_CLASS(oc); =20 - dc->reset =3D mos6522_q800_via2_reset; + device_class_set_parent_reset(dc, mos6522_q800_via2_reset, + &mdc->parent_reset); dc->vmsd =3D &vmstate_q800_via2; mdc->portB_write =3D mos6522_q800_via2_portB_write; } diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index f76d9227d3..4ced31c2c5 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -606,7 +606,8 @@ static void mos6522_cuda_class_init(ObjectClass *oc, vo= id *data) DeviceClass *dc =3D DEVICE_CLASS(oc); MOS6522DeviceClass *mdc =3D MOS6522_CLASS(oc); =20 - dc->reset =3D mos6522_cuda_reset; + device_class_set_parent_reset(dc, mos6522_cuda_reset, + &mdc->parent_reset); mdc->portB_write =3D mos6522_cuda_portB_write; mdc->get_timer1_counter_value =3D cuda_get_counter_value; mdc->get_timer2_counter_value =3D cuda_get_counter_value; diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c index 6e80fe1cfa..a5dd0a4734 100644 --- a/hw/misc/macio/pmu.c +++ b/hw/misc/macio/pmu.c @@ -850,7 +850,8 @@ static void mos6522_pmu_class_init(ObjectClass *oc, voi= d *data) DeviceClass *dc =3D DEVICE_CLASS(oc); MOS6522DeviceClass *mdc =3D MOS6522_CLASS(oc); =20 - dc->reset =3D mos6522_pmu_reset; + device_class_set_parent_reset(dc, mos6522_pmu_reset, + &mdc->parent_reset); mdc->portB_write =3D mos6522_pmu_portB_write; mdc->portA_write =3D mos6522_pmu_portA_write; } diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 4c3147a7d1..093cc83dcf 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -519,7 +519,6 @@ static void mos6522_class_init(ObjectClass *oc, void *d= ata) dc->reset =3D mos6522_reset; dc->vmsd =3D &vmstate_mos6522; device_class_set_props(dc, mos6522_properties); - mdc->parent_reset =3D dc->reset; mdc->portB_write =3D mos6522_portB_write; mdc->portA_write =3D mos6522_portA_write; mdc->get_timer1_counter_value =3D mos6522_get_counter_value; --=20 2.20.1 From nobody Sun Apr 28 21:56:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643317727090138.75839912206447; Thu, 27 Jan 2022 13:08:47 -0800 (PST) Received: from localhost ([::1]:53192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nDC0c-0006ho-8q for importer@patchew.org; Thu, 27 Jan 2022 16:08:46 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34476) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBmy-0008C2-Bm for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:40 -0500 Received: from [2001:41c9:1:41f::167] (port=36838 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBmw-0004wa-Li for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:40 -0500 Received: from [2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe] (helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nDBmR-000BHM-Ez; Thu, 27 Jan 2022 20:54:11 +0000 From: Mark Cave-Ayland To: laurent@vivier.eu, qemu-devel@nongnu.org Date: Thu, 27 Jan 2022 20:54:01 +0000 Message-Id: <20220127205405.23499-8-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> References: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH 07/11] mos6522: add register names to register read/write trace events X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) X-Host-Lookup-Failed: Reverse DNS lookup failed for 2001:41c9:1:41f::167 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643317728934100001 Content-Type: text/plain; charset="utf-8" This helps to follow how the guest is programming the mos6522 when debuggin= g. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/misc/mos6522.c | 10 ++++++++-- hw/misc/trace-events | 4 ++-- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 093cc83dcf..aaae195d63 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -36,6 +36,12 @@ #include "qemu/module.h" #include "trace.h" =20 + +static const char *mos6522_reg_names[16] =3D { + "ORB", "ORA", "DDRB", "DDRA", "T1CL", "T1CH", "T1LL", "T1LH", + "T2CL", "T2CH", "SR", "ACR", "PCR", "IFR", "IER", "ANH" +}; + /* XXX: implement all timer modes */ =20 static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti, @@ -310,7 +316,7 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsign= ed size) } =20 if (addr !=3D VIA_REG_IFR || val !=3D 0) { - trace_mos6522_read(addr, val); + trace_mos6522_read(addr, mos6522_reg_names[addr], val); } =20 return val; @@ -321,7 +327,7 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t = val, unsigned size) MOS6522State *s =3D opaque; MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(s); =20 - trace_mos6522_write(addr, val); + trace_mos6522_write(addr, mos6522_reg_names[addr], val); =20 switch (addr) { case VIA_REG_B: diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 1c373dd0a4..c1ea57de31 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -95,8 +95,8 @@ imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%= 08" PRIx64 "value 0x%08 mos6522_set_counter(int index, unsigned int val) "T%d.counter=3D%d" mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch= =3D%d counter=3D0x%"PRId64 " delta_next=3D0x%"PRId64 mos6522_set_sr_int(void) "set sr_int" -mos6522_write(uint64_t addr, uint64_t val) "reg=3D0x%"PRIx64 " val=3D0x%"P= RIx64 -mos6522_read(uint64_t addr, unsigned val) "reg=3D0x%"PRIx64 " val=3D0x%x" +mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=3D0x%"PR= Ix64 " [%s] val=3D0x%"PRIx64 +mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=3D0x%"PRI= x64 " [%s] val=3D0x%x" =20 # npcm7xx_clk.c npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 = " value: 0x%08" PRIx32 --=20 2.20.1 From nobody Sun Apr 28 21:56:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643317389028215.41230640248432; Thu, 27 Jan 2022 13:03:09 -0800 (PST) Received: from localhost ([::1]:43488 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nDBvA-0008U9-BO for importer@patchew.org; Thu, 27 Jan 2022 16:03:08 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34516) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBn2-0008KR-G0 for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:44 -0500 Received: from [2001:41c9:1:41f::167] (port=36844 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBn0-0004xA-Rj for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:44 -0500 Received: from [2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe] (helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nDBmV-000BHM-Lc; Thu, 27 Jan 2022 20:54:15 +0000 From: Mark Cave-Ayland To: laurent@vivier.eu, qemu-devel@nongnu.org Date: Thu, 27 Jan 2022 20:54:02 +0000 Message-Id: <20220127205405.23499-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> References: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH 08/11] mos6522: add "info via" HMP command for debugging X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) X-Host-Lookup-Failed: Reverse DNS lookup failed for 2001:41c9:1:41f::167 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643317391654100001 Content-Type: text/plain; charset="utf-8" This displays detailed information about the device registers and timers to= aid debugging problems with timers and interrupts. Signed-off-by: Mark Cave-Ayland --- hmp-commands-info.hx | 12 ++++++ hw/misc/mos6522.c | 92 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+) diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx index e90f20a107..4e714e79a2 100644 --- a/hmp-commands-info.hx +++ b/hmp-commands-info.hx @@ -879,3 +879,15 @@ SRST ``info sgx`` Show intel SGX information. ERST + + { + .name =3D "via", + .args_type =3D "", + .params =3D "", + .help =3D "show guest 6522 VIA devices", + }, + +SRST + ``info via`` + Show guest 6522 VIA devices. +ERST diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index aaae195d63..cfa6a9c44b 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -30,6 +30,8 @@ #include "hw/misc/mos6522.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" +#include "monitor/monitor.h" +#include "qapi/type-helpers.h" #include "qemu/timer.h" #include "qemu/cutils.h" #include "qemu/log.h" @@ -415,6 +417,95 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t= val, unsigned size) } } =20 +static int qmp_x_query_via_foreach(Object *obj, void *opaque) +{ + GString *buf =3D opaque; + + if (object_dynamic_cast(obj, TYPE_MOS6522)) { + MOS6522State *s =3D MOS6522(obj); + int64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint16_t t1counter =3D get_counter(s, &s->timers[0]); + uint16_t t2counter =3D get_counter(s, &s->timers[1]); + + g_string_append_printf(buf, "%s:\n", object_get_typename(obj)); + + g_string_append_printf(buf, " Registers:\n"); + g_string_append_printf(buf, " %-*s: 0x%x\n", 4, + mos6522_reg_names[0], s->b); + g_string_append_printf(buf, " %-*s: 0x%x\n", 4, + mos6522_reg_names[1], s->a); + g_string_append_printf(buf, " %-*s: 0x%x\n", 4, + mos6522_reg_names[2], s->dirb); + g_string_append_printf(buf, " %-*s: 0x%x\n", 4, + mos6522_reg_names[3], s->dira); + g_string_append_printf(buf, " %-*s: 0x%x\n", 4, + mos6522_reg_names[4], t1counter & 0xff); + g_string_append_printf(buf, " %-*s: 0x%x\n", 4, + mos6522_reg_names[5], t1counter >> 8); + g_string_append_printf(buf, " %-*s: 0x%x\n", 4, + mos6522_reg_names[6], + s->timers[0].latch & 0xff); + g_string_append_printf(buf, " %-*s: 0x%x\n", 4, + mos6522_reg_names[7], + s->timers[0].latch >> 8); + g_string_append_printf(buf, " %-*s: 0x%x\n", 4, + mos6522_reg_names[8], t2counter & 0xff); + g_string_append_printf(buf, " %-*s: 0x%x\n", 4, + mos6522_reg_names[9], t2counter >> 8); + g_string_append_printf(buf, " %-*s: 0x%x\n", 4, + mos6522_reg_names[10], s->sr); + g_string_append_printf(buf, " %-*s: 0x%x\n", 4, + mos6522_reg_names[11], s->acr); + g_string_append_printf(buf, " %-*s: 0x%x\n", 4, + mos6522_reg_names[12], s->pcr); + g_string_append_printf(buf, " %-*s: 0x%x\n", 4, + mos6522_reg_names[13], s->ifr); + g_string_append_printf(buf, " %-*s: 0x%x\n", 4, + mos6522_reg_names[14], s->ier); + + g_string_append_printf(buf, " Timers:\n"); + g_string_append_printf(buf, " Using current time now(ns)=3D%"PR= Id64 + "\n", now); + g_string_append_printf(buf, " T1 freq(hz)=3D%"PRId64 + " mode=3D%s" + " counter=3D0x%x" + " latch=3D0x%x\n" + " load_time(ns)=3D%"PRId64 + " next_irq_time(ns)=3D%"PRId64 "\n", + s->timers[0].frequency, + ((s->acr & T1MODE) =3D=3D T1MODE_CONT) ? "c= ontinuous" + : "one-s= hot", + t1counter, + s->timers[0].latch, + s->timers[0].load_time, + get_next_irq_time(s, &s->timers[0], now)); + g_string_append_printf(buf, " T2 freq(hz)=3D%"PRId64 + " mode=3D%s" + " counter=3D0x%x" + " latch=3D0x%x\n" + " load_time(ns)=3D%"PRId64 + " next_irq_time(ns)=3D%"PRId64 "\n", + s->timers[1].frequency, + "one-shot", + t2counter, + s->timers[1].latch, + s->timers[1].load_time, + get_next_irq_time(s, &s->timers[1], now)); + } + + return 0; +} + +static HumanReadableText *qmp_x_query_via(Error **errp) +{ + g_autoptr(GString) buf =3D g_string_new(""); + + object_child_foreach_recursive(object_get_root(), + qmp_x_query_via_foreach, buf); + + return human_readable_text_from_str(buf); +} + static const MemoryRegionOps mos6522_ops =3D { .read =3D mos6522_read, .write =3D mos6522_write, @@ -547,6 +638,7 @@ static const TypeInfo mos6522_type_info =3D { static void mos6522_register_types(void) { type_register_static(&mos6522_type_info); + monitor_register_hmp_info_hrt("via", qmp_x_query_via); } =20 type_init(mos6522_register_types) --=20 2.20.1 From nobody Sun Apr 28 21:56:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643318086680256.6715533009208; Thu, 27 Jan 2022 13:14:46 -0800 (PST) Received: from localhost ([::1]:60612 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nDC6P-0003v0-9v for importer@patchew.org; Thu, 27 Jan 2022 16:14:45 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34514) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBn2-0008KM-DM for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:44 -0500 Received: from [2001:41c9:1:41f::167] (port=36850 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBn1-0004xD-1z for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:44 -0500 Received: from [2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe] (helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nDBmZ-000BHM-UH; Thu, 27 Jan 2022 20:54:16 +0000 From: Mark Cave-Ayland To: laurent@vivier.eu, qemu-devel@nongnu.org Date: Thu, 27 Jan 2022 20:54:03 +0000 Message-Id: <20220127205405.23499-10-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> References: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH 09/11] mos6522: record last_irq_levels in mos6522_set_irq() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) X-Host-Lookup-Failed: Reverse DNS lookup failed for 2001:41c9:1:41f::167 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643318088937100001 Content-Type: text/plain; charset="utf-8" To detect edge-triggered IRQs it is necessary to store the last state of ea= ch IRQ in a last_irq_levels bitmap. Note: this is a migration break for machines which use mos6522 instances wh= ich are g3beige/mac99 (PPC) and q800 (m68k). Signed-off-by: Mark Cave-Ayland --- hw/misc/mos6522.c | 11 +++++++++-- include/hw/misc/mos6522.h | 1 + 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index cfa6a9c44b..6eed751726 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -71,6 +71,12 @@ static void mos6522_set_irq(void *opaque, int n, int lev= el) } =20 mos6522_update_irq(s); + + if (level) { + s->last_irq_levels |=3D 1 << n; + } else { + s->last_irq_levels &=3D ~(1 << n); + } } =20 static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti) @@ -532,8 +538,8 @@ static const VMStateDescription vmstate_mos6522_timer = =3D { =20 const VMStateDescription vmstate_mos6522 =3D { .name =3D "mos6522", - .version_id =3D 0, - .minimum_version_id =3D 0, + .version_id =3D 1, + .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { VMSTATE_UINT8(a, MOS6522State), VMSTATE_UINT8(b, MOS6522State), @@ -544,6 +550,7 @@ const VMStateDescription vmstate_mos6522 =3D { VMSTATE_UINT8(pcr, MOS6522State), VMSTATE_UINT8(ifr, MOS6522State), VMSTATE_UINT8(ier, MOS6522State), + VMSTATE_UINT8(last_irq_levels, MOS6522State), VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 0, vmstate_mos6522_timer, MOS6522Timer), VMSTATE_END_OF_LIST() diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h index f6b513a3a2..6c40a8fcd3 100644 --- a/include/hw/misc/mos6522.h +++ b/include/hw/misc/mos6522.h @@ -131,6 +131,7 @@ struct MOS6522State { uint64_t frequency; =20 qemu_irq irq; + uint8_t last_irq_levels; }; =20 #define TYPE_MOS6522 "mos6522" --=20 2.20.1 From nobody Sun Apr 28 21:56:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643317676796475.58340936063894; Thu, 27 Jan 2022 13:07:56 -0800 (PST) Received: from localhost ([::1]:52040 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nDBzn-0005vL-Mx for importer@patchew.org; Thu, 27 Jan 2022 16:07:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34548) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBn6-0008RA-U9 for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:49 -0500 Received: from [2001:41c9:1:41f::167] (port=36856 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBn5-0004xh-2B for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:48 -0500 Received: from [2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe] (helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nDBma-000BHM-84; Thu, 27 Jan 2022 20:54:20 +0000 From: Mark Cave-Ayland To: laurent@vivier.eu, qemu-devel@nongnu.org Date: Thu, 27 Jan 2022 20:54:04 +0000 Message-Id: <20220127205405.23499-11-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> References: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH 10/11] mos6522: implement edge-triggering for CA1/2 and CB1/2 control line IRQs X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) X-Host-Lookup-Failed: Reverse DNS lookup failed for 2001:41c9:1:41f::167 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643317678785100001 Content-Type: text/plain; charset="utf-8" The mos6522 datasheet describes how the control lines IRQs are edge-trigger= ed according to the configuration in the PCR register. Implement the logic acc= ording to the datasheet so that the interrupt bits in IFR are latched when the edg= e is detected, and cleared when reading portA/portB or writing to IFR as necessa= ry. To maintain bisectibility this change also updates the SCSI, SCSI data, Nub= us and VIA2 60Hz/1Hz clocks in the q800 machine to be negative edge-triggered = as confirmed by the PCR programming in all of Linux, NetBSD and MacOS. Signed-off-by: Mark Cave-Ayland --- hw/m68k/q800.c | 9 +++-- hw/misc/mac_via.c | 11 ++++-- hw/misc/mos6522.c | 82 +++++++++++++++++++++++++++++++++++++-- include/hw/misc/mos6522.h | 15 +++++++ 4 files changed, 106 insertions(+), 11 deletions(-) diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 55dfe5036f..66ca5c0df6 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -533,10 +533,11 @@ static void q800_init(MachineState *machine) =20 sysbus =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(sysbus, &error_fatal); - sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(via2_dev, - VIA2_IRQ_SCSI_BIT)); - sysbus_connect_irq(sysbus, 1, qdev_get_gpio_in(via2_dev, - VIA2_IRQ_SCSI_DATA_BIT)= ); + /* SCSI and SCSI data IRQs are negative edge triggered */ + sysbus_connect_irq(sysbus, 0, qemu_irq_invert(qdev_get_gpio_in(via2_de= v, + VIA2_IRQ_SCSI_BIT))); + sysbus_connect_irq(sysbus, 1, qemu_irq_invert(qdev_get_gpio_in(via2_de= v, + VIA2_IRQ_SCSI_DATA_BIT))= ); sysbus_mmio_map(sysbus, 0, ESP_BASE); sysbus_mmio_map(sysbus, 1, ESP_PDMA); =20 diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index 95cf2e03d9..d9ab5b3839 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -327,7 +327,9 @@ static void via1_sixty_hz(void *opaque) MOS6522State *s =3D MOS6522(v1s); qemu_irq irq =3D qdev_get_gpio_in(DEVICE(s), VIA1_IRQ_60HZ_BIT); =20 - qemu_set_irq(irq, 1); + /* Negative edge trigger */ + qemu_irq_lower(irq); + qemu_irq_raise(irq); =20 via1_sixty_hz_update(v1s); } @@ -338,7 +340,9 @@ static void via1_one_second(void *opaque) MOS6522State *s =3D MOS6522(v1s); qemu_irq irq =3D qdev_get_gpio_in(DEVICE(s), VIA1_IRQ_ONE_SECOND_BIT); =20 - qemu_set_irq(irq, 1); + /* Negative edge trigger */ + qemu_irq_lower(irq); + qemu_irq_raise(irq); =20 via1_one_second_update(v1s); } @@ -1131,7 +1135,8 @@ static void via2_nubus_irq_request(void *opaque, int = n, int level) s->a |=3D (1 << n); } =20 - qemu_set_irq(irq, level); + /* Negative edge trigger */ + qemu_set_irq(irq, !level); } =20 static void mos6522_q800_via2_init(Object *obj) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 6eed751726..84b2d54ef3 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -63,14 +63,62 @@ static void mos6522_update_irq(MOS6522State *s) static void mos6522_set_irq(void *opaque, int n, int level) { MOS6522State *s =3D MOS6522(opaque); + int last_level =3D !!(s->last_irq_levels & (1 << n)); + uint8_t last_ifr =3D s->ifr; + bool positive_edge =3D true; + int ctrl; + + /* + * SR_INT is managed by mos6522 instances and cleared upon SR + * read. It is only the external CA1/2 and CB1/2 lines that + * are edge-triggered and latched in IFR + */ + if (n !=3D SR_INT_BIT && level =3D=3D last_level) { + return; + } =20 - if (level) { + /* Detect negative edge trigger */ + if (last_level =3D=3D 1 && level =3D=3D 0) { + positive_edge =3D false; + } + + switch (n) { + case CA2_INT_BIT: + ctrl =3D (s->pcr & CA2_CTRL_MASK) >> CA2_CTRL_SHIFT; + if ((positive_edge && (ctrl & C2_POS)) || + (!positive_edge && !(ctrl & C2_POS))) { + s->ifr |=3D 1 << n; + } + break; + case CA1_INT_BIT: + ctrl =3D (s->pcr & CA1_CTRL_MASK) >> CA1_CTRL_SHIFT; + if ((positive_edge && (ctrl & C1_POS)) || + (!positive_edge && !(ctrl & C1_POS))) { + s->ifr |=3D 1 << n; + } + break; + case SR_INT_BIT: s->ifr |=3D 1 << n; - } else { - s->ifr &=3D ~(1 << n); + break; + case CB2_INT_BIT: + ctrl =3D (s->pcr & CB2_CTRL_MASK) >> CB2_CTRL_SHIFT; + if ((positive_edge && (ctrl & C2_POS)) || + (!positive_edge && !(ctrl & C2_POS))) { + s->ifr |=3D 1 << n; + } + break; + case CB1_INT_BIT: + ctrl =3D (s->pcr & CB1_CTRL_MASK) >> CB1_CTRL_SHIFT; + if ((positive_edge && (ctrl & C1_POS)) || + (!positive_edge && !(ctrl & C1_POS))) { + s->ifr |=3D 1 << n; + } + break; } =20 - mos6522_update_irq(s); + if (s->ifr !=3D last_ifr) { + mos6522_update_irq(s); + } =20 if (level) { s->last_irq_levels |=3D 1 << n; @@ -249,6 +297,7 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsign= ed size) { MOS6522State *s =3D opaque; uint32_t val; + int ctrl; int64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); =20 if (now >=3D s->timers[0].next_irq_time) { @@ -262,12 +311,24 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsi= gned size) switch (addr) { case VIA_REG_B: val =3D s->b; + ctrl =3D (s->pcr & CB2_CTRL_MASK) >> CB2_CTRL_SHIFT; + if (!(ctrl & C2_IND)) { + s->ifr &=3D ~CB2_INT; + } + s->ifr &=3D ~CB1_INT; + mos6522_update_irq(s); break; case VIA_REG_A: qemu_log_mask(LOG_UNIMP, "Read access to register A with handshake"= ); /* fall through */ case VIA_REG_ANH: val =3D s->a; + ctrl =3D (s->pcr & CA2_CTRL_MASK) >> CA2_CTRL_SHIFT; + if (!(ctrl & C2_IND)) { + s->ifr &=3D ~CA2_INT; + } + s->ifr &=3D ~CA1_INT; + mos6522_update_irq(s); break; case VIA_REG_DIRB: val =3D s->dirb; @@ -334,6 +395,7 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t = val, unsigned size) { MOS6522State *s =3D opaque; MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(s); + int ctrl; =20 trace_mos6522_write(addr, mos6522_reg_names[addr], val); =20 @@ -341,6 +403,12 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t= val, unsigned size) case VIA_REG_B: s->b =3D (s->b & ~s->dirb) | (val & s->dirb); mdc->portB_write(s); + ctrl =3D (s->pcr & CB2_CTRL_MASK) >> CB2_CTRL_SHIFT; + if (!(ctrl & C2_IND)) { + s->ifr &=3D ~CB2_INT; + } + s->ifr &=3D ~CB1_INT; + mos6522_update_irq(s); break; case VIA_REG_A: qemu_log_mask(LOG_UNIMP, "Write access to register A with handshake= "); @@ -348,6 +416,12 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t= val, unsigned size) case VIA_REG_ANH: s->a =3D (s->a & ~s->dira) | (val & s->dira); mdc->portA_write(s); + ctrl =3D (s->pcr & CA2_CTRL_MASK) >> CA2_CTRL_SHIFT; + if (!(ctrl & C2_IND)) { + s->ifr &=3D ~CA2_INT; + } + s->ifr &=3D ~CA1_INT; + mos6522_update_irq(s); break; case VIA_REG_DIRB: s->dirb =3D val; diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h index 6c40a8fcd3..a9afb539b2 100644 --- a/include/hw/misc/mos6522.h +++ b/include/hw/misc/mos6522.h @@ -63,6 +63,21 @@ #define T1MODE 0xc0 /* Timer 1 mode */ #define T1MODE_CONT 0x40 /* continuous interrupts */ =20 +/* Bits in PCR */ +#define CB2_CTRL_MASK 0xe0 +#define CB2_CTRL_SHIFT 5 +#define CB1_CTRL_MASK 0x10 +#define CB1_CTRL_SHIFT 4 +#define CA2_CTRL_MASK 0x0e +#define CA2_CTRL_SHIFT 1 +#define CA1_CTRL_MASK 0x1 +#define CA1_CTRL_SHIFT 0 + +#define C2_POS 0x2 +#define C2_IND 0x1 + +#define C1_POS 0x1 + /* VIA registers */ #define VIA_REG_B 0x00 #define VIA_REG_A 0x01 --=20 2.20.1 From nobody Sun Apr 28 21:56:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643317720911171.17658770175308; Thu, 27 Jan 2022 13:08:40 -0800 (PST) Received: from localhost ([::1]:52944 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nDC0W-0006Xx-48 for importer@patchew.org; Thu, 27 Jan 2022 16:08:40 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34566) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBnB-00006V-75 for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:53 -0500 Received: from [2001:41c9:1:41f::167] (port=36860 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDBn9-0004zS-AE for qemu-devel@nongnu.org; Thu, 27 Jan 2022 15:54:52 -0500 Received: from [2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe] (helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nDBme-000BHM-F0; Thu, 27 Jan 2022 20:54:24 +0000 From: Mark Cave-Ayland To: laurent@vivier.eu, qemu-devel@nongnu.org Date: Thu, 27 Jan 2022 20:54:05 +0000 Message-Id: <20220127205405.23499-12-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> References: <20220127205405.23499-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8ba0:ca00:d4eb:dbd5:5a41:aefe X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH 11/11] macio/pmu.c: remove redundant code X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) X-Host-Lookup-Failed: Reverse DNS lookup failed for 2001:41c9:1:41f::167 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1643317721871100001 Content-Type: text/plain; charset="utf-8" Now that the logic related to edge-triggered interrupts is all contained wi= thin the mos6522 device the redundant implementation for the mac99 PMU device can be removed. Signed-off-by: Mark Cave-Ayland --- hw/misc/macio/pmu.c | 33 --------------------------------- include/hw/misc/macio/pmu.h | 2 -- 2 files changed, 35 deletions(-) diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c index a5dd0a4734..a16841e758 100644 --- a/hw/misc/macio/pmu.c +++ b/hw/misc/macio/pmu.c @@ -57,19 +57,6 @@ =20 #define VIA_TIMER_FREQ (4700000 / 6) =20 -static void via_update_irq(PMUState *s) -{ - MOS6522PMUState *mps =3D MOS6522_PMU(&s->mos6522_pmu); - MOS6522State *ms =3D MOS6522(mps); - - bool new_state =3D !!(ms->ifr & ms->ier & (SR_INT | T1_INT | T2_INT)); - - if (new_state !=3D s->via_irq_state) { - s->via_irq_state =3D new_state; - qemu_set_irq(s->via_irq, new_state); - } -} - static void via_set_sr_int(void *opaque) { PMUState *s =3D opaque; @@ -808,28 +795,9 @@ static void mos6522_pmu_portB_write(MOS6522State *s) MOS6522PMUState *mps =3D container_of(s, MOS6522PMUState, parent_obj); PMUState *ps =3D container_of(mps, PMUState, mos6522_pmu); =20 - if ((s->pcr & 0xe0) =3D=3D 0x20 || (s->pcr & 0xe0) =3D=3D 0x60) { - s->ifr &=3D ~CB2_INT; - } - s->ifr &=3D ~CB1_INT; - - via_update_irq(ps); pmu_update(ps); } =20 -static void mos6522_pmu_portA_write(MOS6522State *s) -{ - MOS6522PMUState *mps =3D container_of(s, MOS6522PMUState, parent_obj); - PMUState *ps =3D container_of(mps, PMUState, mos6522_pmu); - - if ((s->pcr & 0x0e) =3D=3D 0x02 || (s->pcr & 0x0e) =3D=3D 0x06) { - s->ifr &=3D ~CA2_INT; - } - s->ifr &=3D ~CA1_INT; - - via_update_irq(ps); -} - static void mos6522_pmu_reset(DeviceState *dev) { MOS6522State *ms =3D MOS6522(dev); @@ -853,7 +821,6 @@ static void mos6522_pmu_class_init(ObjectClass *oc, voi= d *data) device_class_set_parent_reset(dc, mos6522_pmu_reset, &mdc->parent_reset); mdc->portB_write =3D mos6522_pmu_portB_write; - mdc->portA_write =3D mos6522_pmu_portA_write; } =20 static const TypeInfo mos6522_pmu_type_info =3D { diff --git a/include/hw/misc/macio/pmu.h b/include/hw/misc/macio/pmu.h index 78237d99a2..00fcdd23f5 100644 --- a/include/hw/misc/macio/pmu.h +++ b/include/hw/misc/macio/pmu.h @@ -193,8 +193,6 @@ struct PMUState { =20 MemoryRegion mem; uint64_t frequency; - qemu_irq via_irq; - bool via_irq_state; =20 /* PMU state */ MOS6522PMUState mos6522_pmu; --=20 2.20.1