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b=J3grFWEx8RZKw1RmcjfaHKAsunDDMcD2Zpcd7isVEqQbRBtoNCUYKm9lXH2fZW0AhCT5 sTcZ9h8uu7LSkTZiK155OnzC3aaUpy/2UZurRiLLCz5Ra1Xb46s4SXTfD88RZtWqONZM bzLszJvx6dpfDx6fFGlyDOk3TqbnlicdE6wJqTn451p8XfS0by4rdpJHcE/lw3yqU9Gy rtuwQn5GapoaRlfD0VrUk4Wv0KB6MiD77cxXZRagpJM/P9Dl51wbfF3bNa4OLenr5SxA 6uDqauuKDP2e+RCS2XsPImesa4gN5H6KU3n5hs4aAjkq4uaPXxFoz+j3rBG0/jJtnVmk EQ== From: Fabiano Rosas To: qemu-devel@nongnu.org Subject: [PATCH 1/5] target/ppc: Introduce powerpc_excp_books Date: Mon, 24 Jan 2022 15:46:01 -0300 Message-Id: <20220124184605.999353-2-farosas@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220124184605.999353-1-farosas@linux.ibm.com> References: <20220124184605.999353-1-farosas@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: S8egVPuXDBfVQLpOokd8okUedBXVPHYD X-Proofpoint-GUID: FoVVztcYvM1eti0V-XE66XZlqM0bMEkS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-24_09,2022-01-24_02,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 impostorscore=0 phishscore=0 mlxscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201240121 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: danielhb413@gmail.com, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1643050602211100001 Content-Type: text/plain; charset="utf-8" Introduce a new powerpc_excp function specific for BookS CPUs. This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 478 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 478 insertions(+) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index a0c932cd16..08aca37f0a 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -551,6 +551,477 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int exc= p) powerpc_set_excp_state(cpu, vector, new_msr); } =20 +static void powerpc_excp_books(PowerPCCPU *cpu, int excp) +{ + CPUState *cs =3D CPU(cpu); + CPUPPCState *env =3D &cpu->env; + int excp_model =3D env->excp_model; + target_ulong msr, new_msr, vector; + int srr0, srr1, lev =3D -1; + + if (excp <=3D POWERPC_EXCP_NONE || excp >=3D POWERPC_EXCP_NB) { + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); + } + + qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx + " =3D> %s (%d) error=3D%02x\n", env->nip, powerpc_excp_n= ame(excp), + excp, env->error_code); + + /* new srr1 value excluding must-be-zero bits */ + if (excp_model =3D=3D POWERPC_EXCP_BOOKE) { + msr =3D env->msr; + } else { + msr =3D env->msr & ~0x783f0000ULL; + } + + /* + * new interrupt handler msr preserves existing HV and ME unless + * explicitly overriden + */ + new_msr =3D env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); + + /* target registers */ + srr0 =3D SPR_SRR0; + srr1 =3D SPR_SRR1; + + /* + * check for special resume at 0x100 from doze/nap/sleep/winkle on + * P7/P8/P9 + */ + if (env->resume_as_sreset) { + excp =3D powerpc_reset_wakeup(cs, env, excp, &msr); + } + + /* + * Hypervisor emulation assistance interrupt only exists on server + * arch 2.05 server or later. We also don't want to generate it if + * we don't have HVB in msr_mask (PAPR mode). + */ + if (excp =3D=3D POWERPC_EXCP_HV_EMU +#if defined(TARGET_PPC64) + && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB)) +#endif /* defined(TARGET_PPC64) */ + + ) { + excp =3D POWERPC_EXCP_PROGRAM; + } + +#ifdef TARGET_PPC64 + /* + * SPEU and VPU share the same IVOR but they exist in different + * processors. SPEU is e500v1/2 only and VPU is e6500 only. + */ + if (excp_model =3D=3D POWERPC_EXCP_BOOKE && excp =3D=3D POWERPC_EXCP_V= PU) { + excp =3D POWERPC_EXCP_SPEU; + } +#endif + + vector =3D env->excp_vectors[excp]; + if (vector =3D=3D (target_ulong)-1ULL) { + cpu_abort(cs, "Raised an exception without defined vector %d\n", + excp); + } + + vector |=3D env->excp_prefix; + + switch (excp) { + case POWERPC_EXCP_CRITICAL: /* Critical input = */ + switch (excp_model) { + case POWERPC_EXCP_40x: + srr0 =3D SPR_40x_SRR2; + srr1 =3D SPR_40x_SRR3; + break; + case POWERPC_EXCP_BOOKE: + srr0 =3D SPR_BOOKE_CSRR0; + srr1 =3D SPR_BOOKE_CSRR1; + break; + case POWERPC_EXCP_G2: + break; + default: + goto excp_invalid; + } + break; + case POWERPC_EXCP_MCHECK: /* Machine check exception = */ + if (msr_me =3D=3D 0) { + /* + * Machine check exception is not enabled. Enter + * checkstop state. + */ + fprintf(stderr, "Machine check while not allowed. " + "Entering checkstop state\n"); + if (qemu_log_separate()) { + qemu_log("Machine check while not allowed. " + "Entering checkstop state\n"); + } + cs->halted =3D 1; + cpu_interrupt_exittb(cs); + } + if (env->msr_mask & MSR_HVB) { + /* + * ISA specifies HV, but can be delivered to guest with HV + * clear (e.g., see FWNMI in PAPR). + */ + new_msr |=3D (target_ulong)MSR_HVB; + } + + /* machine check exceptions don't have ME set */ + new_msr &=3D ~((target_ulong)1 << MSR_ME); + + /* XXX: should also have something loaded in DAR / DSISR */ + switch (excp_model) { + case POWERPC_EXCP_40x: + srr0 =3D SPR_40x_SRR2; + srr1 =3D SPR_40x_SRR3; + break; + case POWERPC_EXCP_BOOKE: + /* FIXME: choose one or the other based on CPU type */ + srr0 =3D SPR_BOOKE_MCSRR0; + srr1 =3D SPR_BOOKE_MCSRR1; + + env->spr[SPR_BOOKE_CSRR0] =3D env->nip; + env->spr[SPR_BOOKE_CSRR1] =3D msr; + break; + default: + break; + } + break; + case POWERPC_EXCP_DSI: /* Data storage exception = */ + trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); + break; + case POWERPC_EXCP_ISI: /* Instruction storage exception = */ + trace_ppc_excp_isi(msr, env->nip); + msr |=3D env->error_code; + break; + case POWERPC_EXCP_EXTERNAL: /* External input = */ + { + bool lpes0; + + cs =3D CPU(cpu); + + /* + * Exception targeting modifiers + * + * LPES0 is supported on POWER7/8/9 + * LPES1 is not supported (old iSeries mode) + * + * On anything else, we behave as if LPES0 is 1 + * (externals don't alter MSR:HV) + */ +#if defined(TARGET_PPC64) + if (excp_model =3D=3D POWERPC_EXCP_POWER7 || + excp_model =3D=3D POWERPC_EXCP_POWER8 || + excp_model =3D=3D POWERPC_EXCP_POWER9 || + excp_model =3D=3D POWERPC_EXCP_POWER10) { + lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); + } else +#endif /* defined(TARGET_PPC64) */ + { + lpes0 =3D true; + } + + if (!lpes0) { + new_msr |=3D (target_ulong)MSR_HVB; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); + srr0 =3D SPR_HSRR0; + srr1 =3D SPR_HSRR1; + } + if (env->mpic_proxy) { + /* IACK the IRQ on delivery */ + env->spr[SPR_BOOKE_EPR] =3D ldl_phys(cs->as, env->mpic_iack); + } + break; + } + case POWERPC_EXCP_ALIGN: /* Alignment exception = */ + /* Get rS/rD and rA from faulting opcode */ + /* + * Note: the opcode fields will not be set properly for a + * direct store load/store, but nobody cares as nobody + * actually uses direct store segments. + */ + env->spr[SPR_DSISR] |=3D (env->error_code & 0x03FF0000) >> 16; + break; + case POWERPC_EXCP_PROGRAM: /* Program exception = */ + switch (env->error_code & ~0xF) { + case POWERPC_EXCP_FP: + if ((msr_fe0 =3D=3D 0 && msr_fe1 =3D=3D 0) || msr_fp =3D=3D 0)= { + trace_ppc_excp_fp_ignore(); + cs->exception_index =3D POWERPC_EXCP_NONE; + env->error_code =3D 0; + return; + } + + /* + * FP exceptions always have NIP pointing to the faulting + * instruction, so always use store_next and claim we are + * precise in the MSR. + */ + msr |=3D 0x00100000; + env->spr[SPR_BOOKE_ESR] =3D ESR_FP; + break; + case POWERPC_EXCP_INVAL: + trace_ppc_excp_inval(env->nip); + msr |=3D 0x00080000; + env->spr[SPR_BOOKE_ESR] =3D ESR_PIL; + break; + case POWERPC_EXCP_PRIV: + msr |=3D 0x00040000; + env->spr[SPR_BOOKE_ESR] =3D ESR_PPR; + break; + case POWERPC_EXCP_TRAP: + msr |=3D 0x00020000; + env->spr[SPR_BOOKE_ESR] =3D ESR_PTR; + break; + default: + /* Should never occur */ + cpu_abort(cs, "Invalid program exception %d. Aborting\n", + env->error_code); + break; + } + break; + case POWERPC_EXCP_SYSCALL: /* System call exception = */ + lev =3D env->error_code; + + if ((lev =3D=3D 1) && cpu->vhyp) { + dump_hcall(env); + } else { + dump_syscall(env); + } + + /* + * We need to correct the NIP which in this case is supposed + * to point to the next instruction + */ + env->nip +=3D 4; + + /* "PAPR mode" built-in hypercall emulation */ + if ((lev =3D=3D 1) && cpu->vhyp) { + PPCVirtualHypervisorClass *vhc =3D + PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); + vhc->hypercall(cpu->vhyp, cpu); + return; + } + if (lev =3D=3D 1) { + new_msr |=3D (target_ulong)MSR_HVB; + } + break; + case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception = */ + lev =3D env->error_code; + dump_syscall(env); + env->nip +=3D 4; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_EE); + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); + + vector +=3D lev * 0x20; + + env->lr =3D env->nip; + env->ctr =3D msr; + break; + case POWERPC_EXCP_FPU: /* Floating-point unavailable exception = */ + case POWERPC_EXCP_APU: /* Auxiliary processor unavailable = */ + case POWERPC_EXCP_DECR: /* Decrementer exception = */ + break; + case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt = */ + /* FIT on 4xx */ + trace_ppc_excp_print("FIT"); + break; + case POWERPC_EXCP_WDT: /* Watchdog timer interrupt = */ + trace_ppc_excp_print("WDT"); + switch (excp_model) { + case POWERPC_EXCP_BOOKE: + srr0 =3D SPR_BOOKE_CSRR0; + srr1 =3D SPR_BOOKE_CSRR1; + break; + default: + break; + } + break; + case POWERPC_EXCP_DTLB: /* Data TLB error = */ + case POWERPC_EXCP_ITLB: /* Instruction TLB error = */ + break; + case POWERPC_EXCP_DEBUG: /* Debug interrupt = */ + if (env->flags & POWERPC_FLAG_DE) { + /* FIXME: choose one or the other based on CPU type */ + srr0 =3D SPR_BOOKE_DSRR0; + srr1 =3D SPR_BOOKE_DSRR1; + + env->spr[SPR_BOOKE_CSRR0] =3D env->nip; + env->spr[SPR_BOOKE_CSRR1] =3D msr; + + /* DBSR already modified by caller */ + } else { + cpu_abort(cs, "Debug exception triggered on unsupported model\= n"); + } + break; + case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/V= PU */ + env->spr[SPR_BOOKE_ESR] =3D ESR_SPV; + break; + case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt = */ + break; + case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt = */ + srr0 =3D SPR_BOOKE_CSRR0; + srr1 =3D SPR_BOOKE_CSRR1; + break; + case POWERPC_EXCP_RESET: /* System reset exception = */ + /* A power-saving exception sets ME, otherwise it is unchanged */ + if (msr_pow) { + /* indicate that we resumed from power save mode */ + msr |=3D 0x10000; + new_msr |=3D ((target_ulong)1 << MSR_ME); + } + if (env->msr_mask & MSR_HVB) { + /* + * ISA specifies HV, but can be delivered to guest with HV + * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU). + */ + new_msr |=3D (target_ulong)MSR_HVB; + } else { + if (msr_pow) { + cpu_abort(cs, "Trying to deliver power-saving system reset= " + "exception %d with no HV support\n", excp); + } + } + break; + case POWERPC_EXCP_DSEG: /* Data segment exception = */ + case POWERPC_EXCP_ISEG: /* Instruction segment exception = */ + case POWERPC_EXCP_TRACE: /* Trace exception = */ + break; + case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excepti= on */ + msr |=3D env->error_code; + /* fall through */ + case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception = */ + case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception = */ + case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception = */ + case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excepti= on */ + case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt = */ + case POWERPC_EXCP_HV_EMU: + case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization = */ + srr0 =3D SPR_HSRR0; + srr1 =3D SPR_HSRR1; + new_msr |=3D (target_ulong)MSR_HVB; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); + break; + case POWERPC_EXCP_VPU: /* Vector unavailable exception = */ + case POWERPC_EXCP_VSXU: /* VSX unavailable exception = */ + case POWERPC_EXCP_FU: /* Facility unavailable exception = */ +#ifdef TARGET_PPC64 + env->spr[SPR_FSCR] |=3D ((target_ulong)env->error_code << 56); +#endif + break; + case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Except= ion */ +#ifdef TARGET_PPC64 + env->spr[SPR_HFSCR] |=3D ((target_ulong)env->error_code << FSCR_IC= _POS); + srr0 =3D SPR_HSRR0; + srr1 =3D SPR_HSRR1; + new_msr |=3D (target_ulong)MSR_HVB; + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); +#endif + break; + case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt = */ + trace_ppc_excp_print("PIT"); + break; + case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error = */ + case POWERPC_EXCP_DLTLB: /* Data load TLB miss = */ + case POWERPC_EXCP_DSTLB: /* Data store TLB miss = */ + switch (excp_model) { + case POWERPC_EXCP_602: + case POWERPC_EXCP_603: + case POWERPC_EXCP_G2: + /* Swap temporary saved registers with GPRs */ + if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { + new_msr |=3D (target_ulong)1 << MSR_TGPR; + hreg_swap_gpr_tgpr(env); + } + /* fall through */ + case POWERPC_EXCP_7x5: + ppc_excp_debug_sw_tlb(env, excp); + + msr |=3D env->crf[0] << 28; + msr |=3D env->error_code; /* key, D/I, S/L bits */ + /* Set way using a LRU mechanism */ + msr |=3D ((env->last_way + 1) & (env->nb_ways - 1)) << 17; + break; + default: + cpu_abort(cs, "Invalid TLB miss exception\n"); + break; + } + break; + case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt= */ + case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrup= t */ + case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt= */ + case POWERPC_EXCP_IO: /* IO error exception = */ + case POWERPC_EXCP_RUNM: /* Run mode exception = */ + case POWERPC_EXCP_EMUL: /* Emulation trap exception = */ + case POWERPC_EXCP_FPA: /* Floating-point assist exception = */ + case POWERPC_EXCP_DABR: /* Data address breakpoint = */ + case POWERPC_EXCP_IABR: /* Instruction address breakpoint = */ + case POWERPC_EXCP_SMI: /* System management interrupt = */ + case POWERPC_EXCP_THERM: /* Thermal interrupt = */ + case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt= */ + case POWERPC_EXCP_VPUA: /* Vector assist exception = */ + case POWERPC_EXCP_SOFTP: /* Soft patch exception = */ + case POWERPC_EXCP_MAINT: /* Maintenance exception = */ + case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint = */ + case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint = */ + cpu_abort(cs, "%s exception not implemented\n", + powerpc_excp_name(excp)); + break; + default: + excp_invalid: + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); + break; + } + + /* Sanity check */ + if (!(env->msr_mask & MSR_HVB)) { + if (new_msr & MSR_HVB) { + cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with " + "no HV support\n", excp); + } + if (srr0 =3D=3D SPR_HSRR0) { + cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with " + "no HV support\n", excp); + } + } + + /* + * Sort out endianness of interrupt, this differs depending on the + * CPU, the HV mode, etc... + */ + if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { + new_msr |=3D (target_ulong)1 << MSR_LE; + } + +#if defined(TARGET_PPC64) + if (excp_model =3D=3D POWERPC_EXCP_BOOKE) { + if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) { + /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */ + new_msr |=3D (target_ulong)1 << MSR_CM; + } else { + vector =3D (uint32_t)vector; + } + } else { + if (!msr_isf && !mmu_is_64bit(env->mmu_model)) { + vector =3D (uint32_t)vector; + } else { + new_msr |=3D (target_ulong)1 << MSR_SF; + } + } +#endif + + if (excp !=3D POWERPC_EXCP_SYSCALL_VECTORED) { + /* Save PC */ + env->spr[srr0] =3D env->nip; + + /* Save MSR */ + env->spr[srr1] =3D msr; + } + + /* This can update new_msr and vector if AIL applies */ + ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector); + + powerpc_set_excp_state(cpu, vector, new_msr); +} + /* * Note that this function should be greatly optimized when called * with a constant excp, from ppc_hw_interrupt @@ -1034,6 +1505,13 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_40x: powerpc_excp_40x(cpu, excp); break; + case POWERPC_EXCP_970: + case POWERPC_EXCP_POWER7: + case POWERPC_EXCP_POWER8: + case POWERPC_EXCP_POWER9: + case POWERPC_EXCP_POWER10: + powerpc_excp_books(cpu, excp); + break; default: powerpc_excp_legacy(cpu, excp); } --=20 2.34.1 From nobody Sat May 4 12:26:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643050937990931.587932923396; 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Mon, 24 Jan 2022 18:46:18 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 09575AE062; Mon, 24 Jan 2022 18:46:18 +0000 (GMT) Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0D7DDAE05C; Mon, 24 Jan 2022 18:46:16 +0000 (GMT) Received: from farosas.linux.ibm.com.com (unknown [9.163.24.67]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP; Mon, 24 Jan 2022 18:46:15 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=P0BhcNrggoymmUGFuQkla+dSUmJya4wUvEj5biypSeQ=; b=dsTey9+RyQEh3ksleavN1uPRVhhDJV2r8K07meTAbyYxoa/0x/Ygw6Nb5iHumLKGxDmn agk35jhyCFEvzpNExdjSkosgV01ApOwa7RlXMvtnD7PVDafO/hr/7UNOC+J/GKSY/1Qi F+lJn+3jSf5ShmIS9zYoPN+6eT6Z21c2jYvzhthZizcOLux6uXhlQl5UkeJ5YgXquG4q 30KREBdfgNfNVxdez3U/W9IyaFiTG26AyRhq7B8Bp8HeTTEMX9E9cFqLjztW8qQkX/XQ AFGz2FkK2CiXkDmcOsG7pIW+MUf64QvNq0DRMrOt5KyamlIGpXO6EVr0PJELqBFcQ2d+ 5A== From: Fabiano Rosas To: qemu-devel@nongnu.org Subject: [PATCH 2/5] target/ppc: Simplify powerpc_excp_books Date: Mon, 24 Jan 2022 15:46:02 -0300 Message-Id: <20220124184605.999353-3-farosas@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220124184605.999353-1-farosas@linux.ibm.com> References: <20220124184605.999353-1-farosas@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: LBPT2gnChng02dPKtAgBgKHU4PQLACQ2 X-Proofpoint-ORIG-GUID: rKDfQGYRp_mfvsKkd3yCtvBrWf-fjWef X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-24_09,2022-01-24_02,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 suspectscore=0 clxscore=1015 priorityscore=1501 mlxscore=0 bulkscore=0 mlxlogscore=855 adultscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201240121 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: danielhb413@gmail.com, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1643050940043100003 Content-Type: text/plain; charset="utf-8" Differences from the generic powerpc_excp code: - Not BookE, so some MSR bits are cleared at interrupt dispatch; - Always uses HV_EMU if the CPU has MSR_HV; - Exceptions always delivered in 64 bit. Exceptions used: POWERPC_EXCP_ALIGN POWERPC_EXCP_DECR POWERPC_EXCP_DSEG POWERPC_EXCP_DSI POWERPC_EXCP_EXTERNAL POWERPC_EXCP_FPU POWERPC_EXCP_FU POWERPC_EXCP_HDECR POWERPC_EXCP_HDSI POWERPC_EXCP_HISI POWERPC_EXCP_HVIRT POWERPC_EXCP_HV_EMU POWERPC_EXCP_HV_FU POWERPC_EXCP_ISEG POWERPC_EXCP_ISI POWERPC_EXCP_MAINT POWERPC_EXCP_MCHECK POWERPC_EXCP_PERFM POWERPC_EXCP_PROGRAM POWERPC_EXCP_RESET POWERPC_EXCP_SDOOR_HV POWERPC_EXCP_SYSCALL POWERPC_EXCP_SYSCALL_VECTORED POWERPC_EXCP_THERM POWERPC_EXCP_TRACE POWERPC_EXCP_VPU POWERPC_EXCP_VPUA POWERPC_EXCP_VSXU POWERPC_EXCP_HV_MAINT POWERPC_EXCP_SDOOR (I added the two above that were not being considered. They used to be "Invalid exception". Now they become "Unimplemented exception" which is more accurate.) Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 161 ++++----------------------------------- 1 file changed, 14 insertions(+), 147 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 08aca37f0a..0d27dfb2c5 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -551,6 +551,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) powerpc_set_excp_state(cpu, vector, new_msr); } =20 +#ifdef TARGET_PPC64 static void powerpc_excp_books(PowerPCCPU *cpu, int excp) { CPUState *cs =3D CPU(cpu); @@ -568,11 +569,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int ex= cp) excp, env->error_code); =20 /* new srr1 value excluding must-be-zero bits */ - if (excp_model =3D=3D POWERPC_EXCP_BOOKE) { - msr =3D env->msr; - } else { - msr =3D env->msr & ~0x783f0000ULL; - } + msr =3D env->msr & ~0x783f0000ULL; =20 /* * new interrupt handler msr preserves existing HV and ME unless @@ -593,29 +590,13 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) } =20 /* - * Hypervisor emulation assistance interrupt only exists on server - * arch 2.05 server or later. We also don't want to generate it if - * we don't have HVB in msr_mask (PAPR mode). + * We don't want to generate a Hypervisor Emulation Assistance + * Interrupt if we don't have HVB in msr_mask (PAPR mode). */ - if (excp =3D=3D POWERPC_EXCP_HV_EMU -#if defined(TARGET_PPC64) - && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB)) -#endif /* defined(TARGET_PPC64) */ - - ) { + if (excp =3D=3D POWERPC_EXCP_HV_EMU && !(env->msr_mask & MSR_HVB)) { excp =3D POWERPC_EXCP_PROGRAM; } =20 -#ifdef TARGET_PPC64 - /* - * SPEU and VPU share the same IVOR but they exist in different - * processors. SPEU is e500v1/2 only and VPU is e6500 only. - */ - if (excp_model =3D=3D POWERPC_EXCP_BOOKE && excp =3D=3D POWERPC_EXCP_V= PU) { - excp =3D POWERPC_EXCP_SPEU; - } -#endif - vector =3D env->excp_vectors[excp]; if (vector =3D=3D (target_ulong)-1ULL) { cpu_abort(cs, "Raised an exception without defined vector %d\n", @@ -625,22 +606,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int ex= cp) vector |=3D env->excp_prefix; =20 switch (excp) { - case POWERPC_EXCP_CRITICAL: /* Critical input = */ - switch (excp_model) { - case POWERPC_EXCP_40x: - srr0 =3D SPR_40x_SRR2; - srr1 =3D SPR_40x_SRR3; - break; - case POWERPC_EXCP_BOOKE: - srr0 =3D SPR_BOOKE_CSRR0; - srr1 =3D SPR_BOOKE_CSRR1; - break; - case POWERPC_EXCP_G2: - break; - default: - goto excp_invalid; - } - break; case POWERPC_EXCP_MCHECK: /* Machine check exception = */ if (msr_me =3D=3D 0) { /* @@ -817,50 +782,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int ex= cp) env->ctr =3D msr; break; case POWERPC_EXCP_FPU: /* Floating-point unavailable exception = */ - case POWERPC_EXCP_APU: /* Auxiliary processor unavailable = */ case POWERPC_EXCP_DECR: /* Decrementer exception = */ break; - case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt = */ - /* FIT on 4xx */ - trace_ppc_excp_print("FIT"); - break; - case POWERPC_EXCP_WDT: /* Watchdog timer interrupt = */ - trace_ppc_excp_print("WDT"); - switch (excp_model) { - case POWERPC_EXCP_BOOKE: - srr0 =3D SPR_BOOKE_CSRR0; - srr1 =3D SPR_BOOKE_CSRR1; - break; - default: - break; - } - break; - case POWERPC_EXCP_DTLB: /* Data TLB error = */ - case POWERPC_EXCP_ITLB: /* Instruction TLB error = */ - break; - case POWERPC_EXCP_DEBUG: /* Debug interrupt = */ - if (env->flags & POWERPC_FLAG_DE) { - /* FIXME: choose one or the other based on CPU type */ - srr0 =3D SPR_BOOKE_DSRR0; - srr1 =3D SPR_BOOKE_DSRR1; - - env->spr[SPR_BOOKE_CSRR0] =3D env->nip; - env->spr[SPR_BOOKE_CSRR1] =3D msr; - - /* DBSR already modified by caller */ - } else { - cpu_abort(cs, "Debug exception triggered on unsupported model\= n"); - } - break; - case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/V= PU */ - env->spr[SPR_BOOKE_ESR] =3D ESR_SPV; - break; - case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt = */ - break; - case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt = */ - srr0 =3D SPR_BOOKE_CSRR0; - srr1 =3D SPR_BOOKE_CSRR1; - break; case POWERPC_EXCP_RESET: /* System reset exception = */ /* A power-saving exception sets ME, otherwise it is unchanged */ if (msr_pow) { @@ -890,8 +813,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int exc= p) /* fall through */ case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception = */ case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception = */ - case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception = */ - case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excepti= on */ case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt = */ case POWERPC_EXCP_HV_EMU: case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization = */ @@ -903,70 +824,25 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) case POWERPC_EXCP_VPU: /* Vector unavailable exception = */ case POWERPC_EXCP_VSXU: /* VSX unavailable exception = */ case POWERPC_EXCP_FU: /* Facility unavailable exception = */ -#ifdef TARGET_PPC64 env->spr[SPR_FSCR] |=3D ((target_ulong)env->error_code << 56); -#endif break; case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Except= ion */ -#ifdef TARGET_PPC64 env->spr[SPR_HFSCR] |=3D ((target_ulong)env->error_code << FSCR_IC= _POS); srr0 =3D SPR_HSRR0; srr1 =3D SPR_HSRR1; new_msr |=3D (target_ulong)MSR_HVB; new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); -#endif break; - case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt = */ - trace_ppc_excp_print("PIT"); - break; - case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error = */ - case POWERPC_EXCP_DLTLB: /* Data load TLB miss = */ - case POWERPC_EXCP_DSTLB: /* Data store TLB miss = */ - switch (excp_model) { - case POWERPC_EXCP_602: - case POWERPC_EXCP_603: - case POWERPC_EXCP_G2: - /* Swap temporary saved registers with GPRs */ - if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { - new_msr |=3D (target_ulong)1 << MSR_TGPR; - hreg_swap_gpr_tgpr(env); - } - /* fall through */ - case POWERPC_EXCP_7x5: - ppc_excp_debug_sw_tlb(env, excp); - - msr |=3D env->crf[0] << 28; - msr |=3D env->error_code; /* key, D/I, S/L bits */ - /* Set way using a LRU mechanism */ - msr |=3D ((env->last_way + 1) & (env->nb_ways - 1)) << 17; - break; - default: - cpu_abort(cs, "Invalid TLB miss exception\n"); - break; - } - break; - case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt= */ - case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrup= t */ - case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt= */ - case POWERPC_EXCP_IO: /* IO error exception = */ - case POWERPC_EXCP_RUNM: /* Run mode exception = */ - case POWERPC_EXCP_EMUL: /* Emulation trap exception = */ - case POWERPC_EXCP_FPA: /* Floating-point assist exception = */ - case POWERPC_EXCP_DABR: /* Data address breakpoint = */ - case POWERPC_EXCP_IABR: /* Instruction address breakpoint = */ - case POWERPC_EXCP_SMI: /* System management interrupt = */ case POWERPC_EXCP_THERM: /* Thermal interrupt = */ case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt= */ case POWERPC_EXCP_VPUA: /* Vector assist exception = */ - case POWERPC_EXCP_SOFTP: /* Soft patch exception = */ case POWERPC_EXCP_MAINT: /* Maintenance exception = */ - case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint = */ - case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint = */ + case POWERPC_EXCP_SDOOR: /* Doorbell interrupt = */ + case POWERPC_EXCP_HV_MAINT: /* Hypervisor Maintenance exception = */ cpu_abort(cs, "%s exception not implemented\n", powerpc_excp_name(excp)); break; default: - excp_invalid: cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); break; } @@ -991,22 +867,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int ex= cp) new_msr |=3D (target_ulong)1 << MSR_LE; } =20 -#if defined(TARGET_PPC64) - if (excp_model =3D=3D POWERPC_EXCP_BOOKE) { - if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) { - /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */ - new_msr |=3D (target_ulong)1 << MSR_CM; - } else { - vector =3D (uint32_t)vector; - } - } else { - if (!msr_isf && !mmu_is_64bit(env->mmu_model)) { - vector =3D (uint32_t)vector; - } else { - new_msr |=3D (target_ulong)1 << MSR_SF; - } - } -#endif + new_msr |=3D (target_ulong)1 << MSR_SF; =20 if (excp !=3D POWERPC_EXCP_SYSCALL_VECTORED) { /* Save PC */ @@ -1021,6 +882,12 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) =20 powerpc_set_excp_state(cpu, vector, new_msr); } +#else +static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp) +{ + g_assert_not_reached(); +} +#endif =20 /* * Note that this function should be greatly optimized when called --=20 2.34.1 From nobody Sat May 4 12:26:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643050997758309.10666582130773; Mon, 24 Jan 2022 11:03:17 -0800 (PST) Received: from localhost ([::1]:49762 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nC4cX-0000ii-1L for importer@patchew.org; Mon, 24 Jan 2022 14:03:17 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47456) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nC4MP-0003cC-C0; Mon, 24 Jan 2022 13:46:38 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:29654) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nC4MN-0005Ka-FK; Mon, 24 Jan 2022 13:46:37 -0500 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 20OGkfOk031250; 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Mon, 24 Jan 2022 18:46:22 +0000 Received: from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com [9.57.199.110]) by b01cxnp22035.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 20OIkKB628049910 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 24 Jan 2022 18:46:20 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B2650AE066; Mon, 24 Jan 2022 18:46:20 +0000 (GMT) Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A873AAE05C; Mon, 24 Jan 2022 18:46:18 +0000 (GMT) Received: from farosas.linux.ibm.com.com (unknown [9.163.24.67]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP; Mon, 24 Jan 2022 18:46:18 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=DesE41KItusfkC447q2fNLpXTdn9wNZ4wSmAwHqOkWY=; b=eGtuseMrhV1vj6TZwZFgEm8Rg5WwnkulUk4Zbgh9cDk1Pt416ZgqOmXvueC1/TuU2RA3 J8eRfI9Lj2d7dtWtkP9+EBUX47TR9gBlYHKzxdabcdIRv3XLlhqYQ6YZakbKrKNmlq9+ uW857rGHI1bFy/232IiNgStDNzIejDR11fEg9wpZnvJubt3KvBMWcZ+/jGC2ot/Rvxpf 8aDwnQzUvt8HUt8Wqz0QGfK2m7Wp1lyeP951NTyRf/x6kjnCZ3axvwvYXiBFVoo8uXtI XSBn/3sMigOd9qGTwdJ77o5HHBOJ05oCvAWE8UQTAfj7OiXQBdxNZRxIzVCHvGBZFEoq Gw== From: Fabiano Rosas To: qemu-devel@nongnu.org Subject: [PATCH 3/5] target/ppc: books: Machine Check exception cleanup Date: Mon, 24 Jan 2022 15:46:03 -0300 Message-Id: <20220124184605.999353-4-farosas@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220124184605.999353-1-farosas@linux.ibm.com> References: <20220124184605.999353-1-farosas@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: S5ronr7uTfrH3MVh9nK9LOxAqYHRRh9g X-Proofpoint-ORIG-GUID: BYEyADGtgYGey-B04CDJNQyxEgV-dod- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-24_09,2022-01-24_02,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 suspectscore=0 clxscore=1015 priorityscore=1501 mlxscore=0 bulkscore=0 mlxlogscore=999 adultscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201240121 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: danielhb413@gmail.com, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1643050999337100001 Content-Type: text/plain; charset="utf-8" powerpc_excp_books is BookS only, so remove 40x and BookE code. Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 0d27dfb2c5..e5f09e1984 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -632,23 +632,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int ex= cp) /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); =20 - /* XXX: should also have something loaded in DAR / DSISR */ - switch (excp_model) { - case POWERPC_EXCP_40x: - srr0 =3D SPR_40x_SRR2; - srr1 =3D SPR_40x_SRR3; - break; - case POWERPC_EXCP_BOOKE: - /* FIXME: choose one or the other based on CPU type */ - srr0 =3D SPR_BOOKE_MCSRR0; - srr1 =3D SPR_BOOKE_MCSRR1; - - env->spr[SPR_BOOKE_CSRR0] =3D env->nip; - env->spr[SPR_BOOKE_CSRR1] =3D msr; - break; - default: - break; - } break; case POWERPC_EXCP_DSI: /* Data storage exception = */ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); --=20 2.34.1 From nobody Sat May 4 12:26:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643050887726492.33188669371305; Mon, 24 Jan 2022 11:01:27 -0800 (PST) Received: from localhost ([::1]:45162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nC4ak-0005wj-EN for importer@patchew.org; Mon, 24 Jan 2022 14:01:26 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47470) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nC4MR-0003cr-5X; Mon, 24 Jan 2022 13:46:39 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:47718) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nC4MP-0005Kj-CZ; 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Mon, 24 Jan 2022 18:46:24 +0000 Received: from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com [9.57.199.110]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 20OIkNAP34537920 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 24 Jan 2022 18:46:23 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 62BBAAE063; Mon, 24 Jan 2022 18:46:23 +0000 (GMT) Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 59E34AE05C; Mon, 24 Jan 2022 18:46:21 +0000 (GMT) Received: from farosas.linux.ibm.com.com (unknown [9.163.24.67]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP; Mon, 24 Jan 2022 18:46:21 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=or3/ci/+kjI9/GIK8/kNoNq8Ri/RHAOwZ8MWrv+AIhE=; b=JgK/z63FMiNG5qnZHmmmcc9kbZdZ7V9z0TRxesJRgpwIR22zOwU3289NYU3D3ke7s87y xgcjDRMTnCKYsvmtN33WsH7cQNVwdzZYg2yjI238ynVlv/na5EYvjQ6Z6nfbu6oEXDH6 k66zTynNsiDGQvfKW9qRaRUSibHN8RGJUuVOP3PkiA6fWxNf5IvIgGV2A5vu7Q71m/AO RzgcyVZigXA1gdsT1e+aL1h+6yYnpX5GQ09pA7MANF7yl+o/wOyKsk2bYr4JqdyqdchS 6KUgxHEJh+wp5e7MfuxUr1cXD45yHJUVs6aZSKcqd8rq27rBM9bZb+gY8xlciEPEyrEu 2g== From: Fabiano Rosas To: qemu-devel@nongnu.org Subject: [PATCH 4/5] target/ppc: books: External interrupt cleanup Date: Mon, 24 Jan 2022 15:46:04 -0300 Message-Id: <20220124184605.999353-5-farosas@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220124184605.999353-1-farosas@linux.ibm.com> References: <20220124184605.999353-1-farosas@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: rWYJZ0tVolamT1gbrBnBOddICVT0B2u9 X-Proofpoint-GUID: NUhmwzmTrahcDqXHvjcBxD_aL8S1TR6X X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-24_09,2022-01-24_02,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 impostorscore=0 phishscore=0 mlxscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201240121 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: danielhb413@gmail.com, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1643050890764100001 Content-Type: text/plain; charset="utf-8" Since this is now BookS only, we can simplify the code a bit and check has_hv_mode instead of enumerating the exception models. LPES0 does not make sense if there is no MSR_HV. Note that QEMU does not support HV mode on 970 and POWER5+ so we don't set MSR_HV in msr_mask. Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 30 +++++++----------------------- 1 file changed, 7 insertions(+), 23 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index e5f09e1984..67faec3775 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -644,39 +644,23 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) { bool lpes0; =20 - cs =3D CPU(cpu); - /* - * Exception targeting modifiers - * - * LPES0 is supported on POWER7/8/9 - * LPES1 is not supported (old iSeries mode) - * - * On anything else, we behave as if LPES0 is 1 - * (externals don't alter MSR:HV) + * LPES0 is only taken into consideration if we support HV + * mode for this CPU. */ -#if defined(TARGET_PPC64) - if (excp_model =3D=3D POWERPC_EXCP_POWER7 || - excp_model =3D=3D POWERPC_EXCP_POWER8 || - excp_model =3D=3D POWERPC_EXCP_POWER9 || - excp_model =3D=3D POWERPC_EXCP_POWER10) { - lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); - } else -#endif /* defined(TARGET_PPC64) */ - { - lpes0 =3D true; + if (!env->has_hv_mode) { + break; } =20 + lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); + if (!lpes0) { new_msr |=3D (target_ulong)MSR_HVB; new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); srr0 =3D SPR_HSRR0; srr1 =3D SPR_HSRR1; } - if (env->mpic_proxy) { - /* IACK the IRQ on delivery */ - env->spr[SPR_BOOKE_EPR] =3D ldl_phys(cs->as, env->mpic_iack); - } + break; } case POWERPC_EXCP_ALIGN: /* Alignment exception = */ --=20 2.34.1 From nobody Sat May 4 12:26:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643051207268319.6591668473533; Mon, 24 Jan 2022 11:06:47 -0800 (PST) Received: from localhost ([::1]:54056 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nC4fu-0003cC-6B for importer@patchew.org; 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Mon, 24 Jan 2022 18:46:26 +0000 (GMT) Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 07530AE05C; Mon, 24 Jan 2022 18:46:24 +0000 (GMT) Received: from farosas.linux.ibm.com.com (unknown [9.163.24.67]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP; Mon, 24 Jan 2022 18:46:23 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=UaHG7bJqwR8qgEWlUt1GpwPVoW/oERyCrbb/TwYm1sY=; b=tMbzx8pvxGttZQYU1RILJL1LahlUdb+HAqdH65iOD35k38V1ERpE5NrUlgomr8pP/Bp9 d8L//64c8dkg1mMcQEj0OMmA8DlNZuEnak1NASqZ7TSBktv4YCGAYd0cqopbvIM1+805 udvz5ksN+O+KGjyTPqxFxHz8a2Q9tS+tVHA0FQUVoxPg2UYe3W9E5hfqv7mDiYi5ybtk U7XYMHWOAiVeJ9aCT2rqn79uhiuKolSFz3o3YN2XBthBvlVKkdsORUw58Yk2BHrWCRhU 2afEG2MSVnrDXicsVJrMY50ZOm89l60aG077O8X6ILTHKfrn528mUw+NqCRwBLQCIt2L Og== From: Fabiano Rosas To: qemu-devel@nongnu.org Subject: [PATCH 5/5] target/ppc: books: Program exception cleanup Date: Mon, 24 Jan 2022 15:46:05 -0300 Message-Id: <20220124184605.999353-6-farosas@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220124184605.999353-1-farosas@linux.ibm.com> References: <20220124184605.999353-1-farosas@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: kClcYpxNgV8Ib7oPR7OleefLvIjw8zSQ X-Proofpoint-ORIG-GUID: 8LwVYMgzCWMyVjCif9mXNOuavnZv8oCJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-24_09,2022-01-24_02,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 suspectscore=0 spamscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 mlxscore=0 phishscore=0 adultscore=0 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201240121 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: danielhb413@gmail.com, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1643051208784100005 Content-Type: text/plain; charset="utf-8" Remove setting of BookE registers. Signed-off-by: Fabiano Rosas Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 67faec3775..d1cce76e75 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -688,20 +688,16 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) * precise in the MSR. */ msr |=3D 0x00100000; - env->spr[SPR_BOOKE_ESR] =3D ESR_FP; break; case POWERPC_EXCP_INVAL: trace_ppc_excp_inval(env->nip); msr |=3D 0x00080000; - env->spr[SPR_BOOKE_ESR] =3D ESR_PIL; break; case POWERPC_EXCP_PRIV: msr |=3D 0x00040000; - env->spr[SPR_BOOKE_ESR] =3D ESR_PPR; break; case POWERPC_EXCP_TRAP: msr |=3D 0x00020000; - env->spr[SPR_BOOKE_ESR] =3D ESR_PTR; break; default: /* Should never occur */ --=20 2.34.1