From nobody Mon Feb 9 12:42:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1643047858; cv=none; d=zohomail.com; s=zohoarc; b=PKL3nDLUVckyxBkGEbCQEnuRK9ZYI1ekSuhT/mlazVZmBY/QRexXiR7TMXHK0hePXDtBN6M2C28SR1lFwtxgZYDsEOIBRLsjBTkxivPjweo9KsLGu9OwRjLop7JQ14N/Qq/8FW++6/ECjA5XP15zxmBCvYTuj3lLGvNRZdt30Ao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1643047858; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=unRptrbroCsB2v42TuKzCsyAhkTEO3x5a3hl1GMO4FY=; b=VIQ3v272wcvRniOrjaSUoeB+C617rH8boi+9rYE1xFa/lEbXxtlDd7jil5pMd8AcwrbFgsb/wVOipwoog8uKXzM9aJLq7e1zEeIn2Cz9mnZfr6E6gMNcjafJJoP9YeRoqTYvXrC77DxYImovlbX4A4r1TozE547Z7gcNC/0Ldsw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1643047858097318.9859839419937; Mon, 24 Jan 2022 10:10:58 -0800 (PST) Received: from localhost ([::1]:45206 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nC3nt-0006Jp-7n for importer@patchew.org; Mon, 24 Jan 2022 13:10:57 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59540) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nC3FD-0004or-Qk for qemu-devel@nongnu.org; Mon, 24 Jan 2022 12:35:09 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]:2203) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nC3FA-0001wq-Ue for qemu-devel@nongnu.org; Mon, 24 Jan 2022 12:35:07 -0500 Received: from fraeml744-chm.china.huawei.com (unknown [172.18.147.201]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4JjH8m3YSwz67M4k; Tue, 25 Jan 2022 01:31:36 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml744-chm.china.huawei.com (10.206.15.225) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.21; Mon, 24 Jan 2022 18:34:59 +0100 Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.21; Mon, 24 Jan 2022 17:34:58 +0000 To: , Marcel Apfelbaum , "Michael S . Tsirkin" , Igor Mammedov CC: , Ben Widawsky , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , , Shameerali Kolothum Thodi , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Saransh Gupta1 , Shreyas Shah , Chris Browy , Samarth Saxena , "Dan Williams" Subject: [PATCH v4 35/42] cxl/cxl-host: Add memops for CFMWS region. Date: Mon, 24 Jan 2022 17:16:58 +0000 Message-ID: <20220124171705.10432-36-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220124171705.10432-1-Jonathan.Cameron@huawei.com> References: <20220124171705.10432-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhreml740-chm.china.huawei.com (10.201.108.190) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Jonathan Cameron From: Jonathan Cameron via X-ZM-MESSAGEID: 1643047860004100001 Content-Type: text/plain; charset="utf-8" From: Jonathan Cameron These memops perform interleave decoding, walking down the CXL topology from CFMWS described host interleave decoder via CXL host bridge HDM decoders, through the CXL root ports and finally call CXL type 3 specific read and write functions. Note that, whilst functional the current implementation does not support: * switches * multiple HDM decoders at a given level. * unaligned accesses across the interleave boundaries Signed-off-by: Jonathan Cameron --- hw/cxl/cxl-host.c | 125 +++++++++++++++++++++++++++++++++++++++++++ include/hw/cxl/cxl.h | 2 + 2 files changed, 127 insertions(+) diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c index 9f303e6d8e..d9cad188a8 100644 --- a/hw/cxl/cxl-host.c +++ b/hw/cxl/cxl-host.c @@ -136,3 +136,128 @@ void cxl_fixed_memory_window_link_targets(Error **err= p) } } } + +/* TODO: support, multiple hdm decoders */ +static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr, + uint8_t *target) +{ + uint32_t ctrl; + uint32_t ig_enc; + uint32_t iw_enc; + uint32_t target_reg; + uint32_t target_idx; + + ctrl =3D cache_mem[R_CXL_HDM_DECODER0_CTRL]; + if (!FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED)) { + return false; + } + + ig_enc =3D FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IG); + iw_enc =3D FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW); + target_idx =3D (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc); + + if (target_idx > 4) { + target_reg =3D cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO]; + target_reg >>=3D target_idx * 8; + } else { + target_reg =3D cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO]; + target_reg >>=3D (target_idx - 4) * 8; + } + *target =3D target_reg & 0xff; + + return true; +} + +static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr) +{ + CXLComponentState *hb_cstate; + PCIHostState *hb; + int rb_index; + uint32_t *cache_mem; + uint8_t target; + bool target_found; + PCIDevice *rp, *d; + + /* Address is relative to memory region. Convert to HPA */ + addr +=3D fw->base; + + rb_index =3D (addr / cxl_decode_ig(fw->enc_int_gran)) % fw->num_target= s; + hb =3D PCI_HOST_BRIDGE(fw->target_hbs[rb_index]->cxl.cxl_host_bridge); + if (!hb || !hb->bus || !pci_bus_is_cxl(hb->bus)) { + return NULL; + } + + hb_cstate =3D cxl_get_hb_cstate(hb); + if (!hb_cstate) { + return NULL; + } + + cache_mem =3D hb_cstate->crb.cache_mem_registers; + + target_found =3D cxl_hdm_find_target(cache_mem, addr, &target); + if (!target_found) { + return NULL; + } + + rp =3D pcie_find_port_by_pn(hb->bus, target); + if (!rp) { + return NULL; + } + + d =3D pci_bridge_get_sec_bus(PCI_BRIDGE(rp))->devices[0]; + + if (!d || !object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3_DEV)) { + return NULL; + } + + return d; +} + +static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t *dat= a, + unsigned size, MemTxAttrs attrs) +{ + CXLFixedWindow *fw =3D opaque; + PCIDevice *d; + + d =3D cxl_cfmws_find_device(fw, addr); + if (d =3D=3D NULL) { + *data =3D 0; + /* Reads to invalid address return poison */ + return MEMTX_ERROR; + } + + return cxl_type3_read(d, addr + fw->base, data, size, attrs); +} + +static MemTxResult cxl_write_cfmws(void *opaque, hwaddr addr, + uint64_t data, unsigned size, + MemTxAttrs attrs) +{ + CXLFixedWindow *fw =3D opaque; + PCIDevice *d; + + d =3D cxl_cfmws_find_device(fw, addr); + if (d =3D=3D NULL) { + /* Writes to invalid address are silent */ + return MEMTX_OK; + } + + return cxl_type3_write(d, addr + fw->base, data, size, attrs); +} + +const MemoryRegionOps cfmws_ops =3D { + .read_with_attrs =3D cxl_read_cfmws, + .write_with_attrs =3D cxl_write_cfmws, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + .unaligned =3D true, + }, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + .unaligned =3D true, + }, +}; + diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index 1b72c0b7b7..260d602ec9 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -46,4 +46,6 @@ extern QemuOptsList qemu_cxl_fixed_window_opts; void parse_cxl_fixed_memory_window_opts(MachineState *ms); void cxl_fixed_memory_window_link_targets(Error **errp); =20 +extern const MemoryRegionOps cfmws_ops; + #endif --=20 2.32.0