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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1642986017; x=1645578018; bh=2Sz4azhhBCyD9TZ8hR YrMVr2zFhqdk59LkcBrCN+QZg=; b=XWJNGLy4lxy4nJ1akquWRLe74h2ANLp6EL mpyKNRjsaLCJjXzgnko8F2BAf36XkGCIAOamy1YIUc828aMnMWPffcmBDH3woRs2 3IHxvhHkU5YkAJD1e+ovxqVc18Y1vkR4vsX0l2N9VxgRYpPDFDttt+mpLCyKMA33 NRNidA/DOdeQyHPkS0QJ4N9oH6ym1A1zTZDI3e1hXqFQtcyxC2Ukm2odyHB5l/Oj KKIPKY+Be3ob40S3mayYAG0ENin7eZ+ZYInlsuA7J6UM4BQVS3DEsPjtCdGKM3HE NTU1dXkmpFvTVvV3xq1UiiBI3qiCbe2V/7WOQi8hYBfAaMyicHVQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alistair Francis , Paolo Bonzini , alistair23@gmail.com, Bin Meng , palmer@dabbelt.com, Peter Xu , David Hildenbrand , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , bmeng.cn@gmail.com Subject: [PATCH 1/2] accel: tcg: Allow forcing a store fault on read ops Date: Mon, 24 Jan 2022 10:59:57 +1000 Message-Id: <20220124005958.38848-2-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220124005958.38848-1-alistair.francis@opensource.wdc.com> References: <20220124005958.38848-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=01678aa48=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642986457701100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis When performing atomic operations TCG will do a read operation then a write operation. This results in a MMU_DATA_LOAD fault if the address is invalid. For some platforms (such as RISC-V) we should produce a store fault if an atomic operation fails. This patch adds a new MemOp (MO_WRITE_FAULT) that allows us to indicate that the operation should produce a MMU_DATA_STORE access type if the operation faults. Signed-off-by: Alistair Francis --- include/exec/memop.h | 2 ++ accel/tcg/cputlb.c | 11 +++++++++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index 2a885f3917..93ae1b6a2e 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -81,6 +81,8 @@ typedef enum MemOp { MO_ALIGN_32 =3D 5 << MO_ASHIFT, MO_ALIGN_64 =3D 6 << MO_ASHIFT, =20 + MO_WRITE_FAULT =3D 0x100, + /* Combinations of the above, for ease of use. */ MO_UB =3D MO_8, MO_UW =3D MO_16, diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5e0d0eebc3..320555d5e9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1362,8 +1362,15 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLB= Entry *iotlbentry, section->offset_within_address_space - section->offset_within_region; =20 - cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access= _type, - mmu_idx, iotlbentry->attrs, r, retaddr); + if (op & MO_WRITE_FAULT) { + cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), + MMU_DATA_STORE, mmu_idx, iotlbentry->at= trs, + r, retaddr); + } else { + cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), + access_type, mmu_idx, iotlbentry->attrs, + r, retaddr); + } } if (locked) { qemu_mutex_unlock_iothread(); --=20 2.31.1 From nobody Sun May 5 13:12:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642986278780956.7554148797049; Sun, 23 Jan 2022 17:04:38 -0800 (PST) Received: from localhost ([::1]:41988 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nBnmf-0005B0-F8 for importer@patchew.org; Sun, 23 Jan 2022 20:04:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41504) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nBnjj-0003Ef-Lt for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1642986025; x=1645578026; bh=Z9l97yNeymIo/fMxa2 isTdGBCvimAkQsFYCnC07EtMM=; b=q9W9IuYJMBNpVO1lnt7iP6WSeGxGVEEj1u qmd7WIZLvjUk1pu7KbpVBoLuhDhQjy9MF9YzvCZM+rXTyCxj5kzM7wms1LVmDafn neuWS4+GweCc4hL12ey3RqfQa7uKpgK9B7KO7be2DysKbld3dQl6p+jDXkgMNT47 QfJpzyou8pmPx9wzr31kyWfjmbUazDJSKRyMdgoxLiI66N15zbCGHHBsmzvdnjGH 81ArJpMYTu1B3UpXhkB9pRrWaKt2d+R8am0vpw8YxM97fOwXYaIh5id4V8KbYXO/ gt34Z4v3UOrHyOekolxz+qM/KNp4uCZIo50xscVMCYd6JSIRSM2w== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alistair Francis , Paolo Bonzini , alistair23@gmail.com, Bin Meng , palmer@dabbelt.com, Peter Xu , David Hildenbrand , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , bmeng.cn@gmail.com Subject: [PATCH 2/2] targett/riscv: rva: Correctly generate a store/amo fault Date: Mon, 24 Jan 2022 10:59:58 +1000 Message-Id: <20220124005958.38848-3-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220124005958.38848-1-alistair.francis@opensource.wdc.com> References: <20220124005958.38848-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=01678aa48=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642986281522100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis If the atomic operation fails we want to generate a MMU_DATA_STORE access type so we can produce a RISCV_EXCP_STORE_AMO_ACCESS_FAULT for the guest. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/594 Signed-off-by: Alistair Francis Reviewed-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rva.c.inc | 56 ++++++++++++++++--------- 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index 45db82c9be..be5c94803b 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -93,7 +93,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_lr(ctx, a, (MO_ALIGN | MO_TESL)); + return gen_lr(ctx, a, (MO_ALIGN | MO_TESL)); } =20 static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a) @@ -105,55 +105,64 @@ static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a) static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL)); + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TE= SL)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TE= SL)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TE= SL)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TES= L)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_T= ESL)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_T= ESL)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_T= ESL)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_T= ESL)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a) @@ -171,53 +180,62 @@ static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a) static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEUQ)); + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } =20 static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TE= UQ)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } =20 static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TE= UQ)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } =20 static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TE= UQ)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } =20 static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEU= Q)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } =20 static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_T= EUQ)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } =20 static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_T= EUQ)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } =20 static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_T= EUQ)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } =20 static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_T= EUQ)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } --=20 2.31.1