From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642696780950756.6252292868592; Thu, 20 Jan 2022 08:39:40 -0800 (PST) Received: from localhost ([::1]:34300 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAaTL-00088h-VB for importer@patchew.org; Thu, 20 Jan 2022 11:39:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38294) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWSZ-00034f-UA; Thu, 20 Jan 2022 07:22:35 -0500 Received: from out28-193.mail.aliyun.com ([115.124.28.193]:49998) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWSW-0007jq-0q; Thu, 20 Jan 2022 07:22:34 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfxKmoG_1642681346) by smtp.aliyun-inc.com(10.147.40.200); Thu, 20 Jan 2022 20:22:27 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07567868|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.205096-0.000127296-0.794776; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047192; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfxKmoG_1642681346; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 01/23] target/riscv: Adjust pmpcfg access with mxl Date: Thu, 20 Jan 2022 20:20:28 +0800 Message-Id: <20220120122050.41546-2-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.193; envelope-from=zhiwei_liu@c-sky.com; helo=out28-193.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642696783842100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 19 +++++++++++++++++++ target/riscv/pmp.c | 12 ++++-------- 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a9e7ac903b..6bc7ee780c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1497,9 +1497,23 @@ static RISCVException write_mseccfg(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 +static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index) +{ + /* TODO: RV128 restriction check */ + if ((reg_index & 1) && (riscv_cpu_mxl(env) =3D=3D MXL_RV64)) { + return false; + } + return true; +} + static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) { + uint32_t reg_index =3D csrno - CSR_PMPCFG0; + + if (!check_pmp_reg_index(env, reg_index)) { + return RISCV_EXCP_ILLEGAL_INST; + } *val =3D pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); return RISCV_EXCP_NONE; } @@ -1507,6 +1521,11 @@ static RISCVException read_pmpcfg(CPURISCVState *env= , int csrno, static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) { + uint32_t reg_index =3D csrno - CSR_PMPCFG0; + + if (!check_pmp_reg_index(env, reg_index)) { + return RISCV_EXCP_ILLEGAL_INST; + } pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); return RISCV_EXCP_NONE; } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 54abf42583..81b61bb65c 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -463,16 +463,11 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t re= g_index, { int i; uint8_t cfg_val; + int pmpcfg_nums =3D 2 << riscv_cpu_mxl(env); =20 trace_pmpcfg_csr_write(env->mhartid, reg_index, val); =20 - if ((reg_index & 1) && (sizeof(target_ulong) =3D=3D 8)) { - qemu_log_mask(LOG_GUEST_ERROR, - "ignoring pmpcfg write - incorrect address\n"); - return; - } - - for (i =3D 0; i < sizeof(target_ulong); i++) { + for (i =3D 0; i < pmpcfg_nums; i++) { cfg_val =3D (val >> 8 * i) & 0xff; pmp_write_cfg(env, (reg_index * 4) + i, cfg_val); } @@ -490,8 +485,9 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32= _t reg_index) int i; target_ulong cfg_val =3D 0; target_ulong val =3D 0; + int pmpcfg_nums =3D 2 << riscv_cpu_mxl(env); =20 - for (i =3D 0; i < sizeof(target_ulong); i++) { + for (i =3D 0; i < pmpcfg_nums; i++) { val =3D pmp_read_cfg(env, (reg_index * 4) + i); cfg_val |=3D (val << (i * 8)); } --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16426952703275.735785761688135; Thu, 20 Jan 2022 08:14:30 -0800 (PST) Received: from localhost ([::1]:32936 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAa4z-00048x-6W for importer@patchew.org; Thu, 20 Jan 2022 11:14:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38444) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWTC-0003TL-51; Thu, 20 Jan 2022 07:23:14 -0500 Received: from out28-49.mail.aliyun.com ([115.124.28.49]:36531) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWT9-0007mz-Ld; Thu, 20 Jan 2022 07:23:13 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfwAc2c_1642681377) by smtp.aliyun-inc.com(10.147.41.158); Thu, 20 Jan 2022 20:22:59 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07447494|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0111777-0.000397031-0.988425; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047202; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfwAc2c_1642681377; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 02/23] target/riscv: Don't save pc when exception return Date: Thu, 20 Jan 2022 20:20:29 +0800 Message-Id: <20220120122050.41546-3-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.49; envelope-from=zhiwei_liu@c-sky.com; helo=out28-49.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642695271095100001 Content-Type: text/plain; charset="utf-8" As pc will be written by the xepc in exception return, just ignore pc in translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 4 ++-- target/riscv/insn_trans/trans_privileged.c.inc | 7 ++----- target/riscv/op_helper.c | 4 ++-- 3 files changed, 6 insertions(+), 9 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 6cf6d6ce98..72cc2582f4 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -100,8 +100,8 @@ DEF_HELPER_2(csrr_i128, tl, env, int) DEF_HELPER_4(csrw_i128, void, env, int, tl, tl) DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY -DEF_HELPER_2(sret, tl, env, tl) -DEF_HELPER_2(mret, tl, env, tl) +DEF_HELPER_1(sret, tl, env) +DEF_HELPER_1(mret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) #endif diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 75c6ef80a6..6077bbbf11 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -74,10 +74,8 @@ static bool trans_uret(DisasContext *ctx, arg_uret *a) static bool trans_sret(DisasContext *ctx, arg_sret *a) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - if (has_ext(ctx, RVS)) { - gen_helper_sret(cpu_pc, cpu_env, cpu_pc); + gen_helper_sret(cpu_pc, cpu_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; } else { @@ -92,8 +90,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - gen_helper_mret(cpu_pc, cpu_env, cpu_pc); + gen_helper_mret(cpu_pc, cpu_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; return true; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 6f040f2fb9..67693cb42b 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -115,7 +115,7 @@ target_ulong helper_csrrw_i128(CPURISCVState *env, int = csr, =20 #ifndef CONFIG_USER_ONLY =20 -target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) +target_ulong helper_sret(CPURISCVState *env) { uint64_t mstatus; target_ulong prev_priv, prev_virt; @@ -176,7 +176,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) return retpc; } =20 -target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) +target_ulong helper_mret(CPURISCVState *env) { if (!(env->priv >=3D PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642697457766616.1809704943164; Thu, 20 Jan 2022 08:50:57 -0800 (PST) Received: from localhost ([::1]:42940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAaeG-00060W-IW for importer@patchew.org; Thu, 20 Jan 2022 11:50:56 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38492) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWTc-0003lX-ND; Thu, 20 Jan 2022 07:23:40 -0500 Received: from out28-196.mail.aliyun.com ([115.124.28.196]:43223) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWTa-0007qY-De; Thu, 20 Jan 2022 07:23:40 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfwN9dh_1642681409) by smtp.aliyun-inc.com(10.147.41.121); Thu, 20 Jan 2022 20:23:33 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.110418|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0613642-0.000762315-0.937873; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047201; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfwN9dh_1642681409; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 03/23] target/riscv: Sign extend link reg for jal and jalr Date: Thu, 20 Jan 2022 20:20:30 +0800 Message-Id: <20220120122050.41546-4-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.196; envelope-from=zhiwei_liu@c-sky.com; helo=out28-196.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642697460539100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 4 +--- target/riscv/translate.c | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 3a0ae28fef..b9ba57f266 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -68,9 +68,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) tcg_temp_free(t0); } =20 - if (a->rd !=3D 0) { - tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn); - } + gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn); tcg_gen_lookup_and_goto_ptr(); =20 if (misaligned) { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 330904265e..30c0e28778 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -369,10 +369,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_= ulong imm) return; } } - if (rd !=3D 0) { - tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); - } =20 + gen_set_gpri(ctx, rd, ctx->pc_succ_insn); gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for saf= ety */ ctx->base.is_jmp =3D DISAS_NORETURN; } --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642697812621967.795346572826; Thu, 20 Jan 2022 08:56:52 -0800 (PST) Received: from localhost ([::1]:51448 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAajz-0003bd-Dj for importer@patchew.org; Thu, 20 Jan 2022 11:56:51 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38602) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWU6-0004Sg-Dx; Thu, 20 Jan 2022 07:24:11 -0500 Received: from out28-149.mail.aliyun.com ([115.124.28.149]:43400) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWU3-0007tP-SE; Thu, 20 Jan 2022 07:24:10 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Mfw94pc_1642681443) by smtp.aliyun-inc.com(10.147.41.199); Thu, 20 Jan 2022 20:24:03 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.0744539|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0352721-0.00066645-0.964061; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047198; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.Mfw94pc_1642681443; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 04/23] target/riscv: Sign extend pc for different XLEN Date: Thu, 20 Jan 2022 20:20:31 +0800 Message-Id: <20220120122050.41546-5-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.149; envelope-from=zhiwei_liu@c-sky.com; helo=out28-149.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642697813282100001 Content-Type: text/plain; charset="utf-8" When pc is written, it is sign-extended to fill the widest supported XLEN. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- .../riscv/insn_trans/trans_privileged.c.inc | 2 +- target/riscv/insn_trans/trans_rvi.c.inc | 5 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 4 +-- target/riscv/translate.c | 25 ++++++++++++++++--- 4 files changed, 27 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 6077bbbf11..53613682e8 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -102,7 +102,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) static bool trans_wfi(DisasContext *ctx, arg_wfi *a) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); + gen_set_pc_imm(ctx, ctx->pc_succ_insn); gen_helper_wfi(cpu_env); return true; #else diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index b9ba57f266..04d3ea237f 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -59,6 +59,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm); tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); =20 + gen_set_pc(ctx, cpu_pc); if (!has_ext(ctx, RVC)) { TCGv t0 =3D tcg_temp_new(); =20 @@ -827,7 +828,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_= i *a) * FENCE_I is a no-op in QEMU, * however we need to end the translation block */ - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); + gen_set_pc_imm(ctx, ctx->pc_succ_insn); tcg_gen_exit_tb(NULL, 0); ctx->base.is_jmp =3D DISAS_NORETURN; return true; @@ -836,7 +837,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_= i *a) static bool do_csr_post(DisasContext *ctx) { /* We may have changed important cpu state -- exit to main loop. */ - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); + gen_set_pc_imm(ctx, ctx->pc_succ_insn); tcg_gen_exit_tb(NULL, 0); ctx->base.is_jmp =3D DISAS_NORETURN; return true; diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 7a040b3089..e03959c46f 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -194,7 +194,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1,= TCGv s2) gen_set_gpr(s, rd, dst); mark_vs_dirty(s); =20 - tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn); + gen_set_pc_imm(s, s->pc_succ_insn); tcg_gen_lookup_and_goto_ptr(); s->base.is_jmp =3D DISAS_NORETURN; =20 @@ -219,7 +219,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s= 1, TCGv s2) gen_helper_vsetvl(dst, cpu_env, s1, s2); gen_set_gpr(s, rd, dst); mark_vs_dirty(s); - tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn); + gen_set_pc_imm(s, s->pc_succ_insn); tcg_gen_lookup_and_goto_ptr(); s->base.is_jmp =3D DISAS_NORETURN; =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 30c0e28778..2a88bd99dc 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -193,16 +193,33 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64= in) tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); } =20 +static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) +{ + if (get_xl(ctx) =3D=3D MXL_RV32) { + dest =3D (int32_t)dest; + } + tcg_gen_movi_tl(cpu_pc, dest); +} + +static void gen_set_pc(DisasContext *ctx, TCGv dest) +{ + if (get_xl(ctx) =3D=3D MXL_RV32) { + tcg_gen_ext32s_tl(cpu_pc, dest); + } else { + tcg_gen_mov_tl(cpu_pc, dest); + } +} + static void generate_exception(DisasContext *ctx, int excp) { - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + gen_set_pc_imm(ctx, ctx->base.pc_next); gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 static void generate_exception_mtval(DisasContext *ctx, int excp) { - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + gen_set_pc_imm(ctx, ctx->base.pc_next); tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); ctx->base.is_jmp =3D DISAS_NORETURN; @@ -225,10 +242,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, tar= get_ulong dest) { if (translator_use_goto_tb(&ctx->base, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_tl(cpu_pc, dest); + gen_set_pc_imm(ctx, dest); tcg_gen_exit_tb(ctx->base.tb, n); } else { - tcg_gen_movi_tl(cpu_pc, dest); + gen_set_pc_imm(ctx, dest); tcg_gen_lookup_and_goto_ptr(); } } --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642694398838124.02418820961032; Thu, 20 Jan 2022 07:59:58 -0800 (PST) Received: from localhost ([::1]:45794 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAZqv-0001cf-NS for importer@patchew.org; Thu, 20 Jan 2022 10:59:57 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38760) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWUm-0005fx-NR; Thu, 20 Jan 2022 07:24:52 -0500 Received: from out28-172.mail.aliyun.com ([115.124.28.172]:51049) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWUY-0007xJ-Ui; Thu, 20 Jan 2022 07:24:45 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfwAcRC_1642681473) by smtp.aliyun-inc.com(10.147.41.158); Thu, 20 Jan 2022 20:24:34 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436284|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0393183-0.00100072-0.959681; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047187; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfwAcRC_1642681473; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 05/23] target/riscv: Create xl field in env Date: Thu, 20 Jan 2022 20:20:32 +0800 Message-Id: <20220120122050.41546-6-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.172; envelope-from=zhiwei_liu@c-sky.com; helo=out28-172.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642694400094100003 Content-Type: text/plain; charset="utf-8" Current xlen has been used in helper functions and many other places. The computation of current xlen is not so trivial, so that we should recompute it as little as possible. Fortunately, xlen only changes in very seldom cases, such as exception, misa write, mstatus write, cpu reset, migration load. So that we can only recompute xlen in this places and cache it into CPURISCVState. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 31 +++++++++++++++++++++++++++++++ target/riscv/cpu_helper.c | 34 ++-------------------------------- target/riscv/csr.c | 2 ++ target/riscv/machine.c | 10 ++++++++++ 5 files changed, 46 insertions(+), 32 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c2b570e904..736cf1d4e7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -413,6 +413,7 @@ static void riscv_cpu_reset(DeviceState *dev) /* mmte is supposed to have pm.current hardwired to 1 */ env->mmte |=3D (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); #endif + env->xl =3D riscv_cpu_mxl(env); cs->exception_index =3D RISCV_EXCP_NONE; env->load_res =3D -1; set_default_nan_mode(1, &env->fp_status); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 03552f4aaa..7657e22a56 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -146,6 +146,7 @@ struct CPURISCVState { uint32_t misa_mxl_max; /* max mxl for this cpu */ uint32_t misa_ext; /* current extensions */ uint32_t misa_ext_mask; /* max ext for this cpu */ + uint32_t xl; /* current xlen */ =20 /* 128-bit helpers upper part return value */ target_ulong retxh; @@ -456,6 +457,36 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *en= v) } #endif =20 +#if defined(TARGET_RISCV32) +#define cpu_recompute_xl(env) ((void)(env), MXL_RV32) +#else +static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) +{ + RISCVMXL xl =3D env->misa_mxl; +#if !defined(CONFIG_USER_ONLY) + /* + * When emulating a 32-bit-only cpu, use RV32. + * When emulating a 64-bit cpu, and MXL has been reduced to RV32, + * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened + * back to RV64 for lower privs. + */ + if (xl !=3D MXL_RV32) { + switch (env->priv) { + case PRV_M: + break; + case PRV_U: + xl =3D get_field(env->mstatus, MSTATUS64_UXL); + break; + default: /* PRV_S | PRV_H */ + xl =3D get_field(env->mstatus, MSTATUS64_SXL); + break; + } + } +#endif + return xl; +} +#endif + /* * Encode LMUL to lmul as follows: * LMUL vlmul lmul diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index afee770951..8ebcd57af0 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -35,37 +35,6 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } =20 -static RISCVMXL cpu_get_xl(CPURISCVState *env) -{ -#if defined(TARGET_RISCV32) - return MXL_RV32; -#elif defined(CONFIG_USER_ONLY) - return MXL_RV64; -#else - RISCVMXL xl =3D riscv_cpu_mxl(env); - - /* - * When emulating a 32-bit-only cpu, use RV32. - * When emulating a 64-bit cpu, and MXL has been reduced to RV32, - * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened - * back to RV64 for lower privs. - */ - if (xl !=3D MXL_RV32) { - switch (env->priv) { - case PRV_M: - break; - case PRV_U: - xl =3D get_field(env->mstatus, MSTATUS64_UXL); - break; - default: /* PRV_S | PRV_H */ - xl =3D get_field(env->mstatus, MSTATUS64_SXL); - break; - } - } - return xl; -#endif -} - void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -148,7 +117,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ul= ong *pc, } #endif =20 - flags =3D FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); =20 *pflags =3D flags; } @@ -364,6 +333,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulon= g newpriv) } /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv =3D newpriv; + env->xl =3D cpu_recompute_xl(env); =20 /* * Clear the load reservation - otherwise a reservation placed in one diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6bc7ee780c..9be2820d2b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -589,6 +589,7 @@ static RISCVException write_mstatus(CPURISCVState *env,= int csrno, mstatus =3D set_field(mstatus, MSTATUS64_UXL, xl); } env->mstatus =3D mstatus; + env->xl =3D cpu_recompute_xl(env); =20 return RISCV_EXCP_NONE; } @@ -704,6 +705,7 @@ static RISCVException write_misa(CPURISCVState *env, in= t csrno, /* flush translation cache */ tb_flush(env_cpu(env)); env->misa_ext =3D val; + env->xl =3D riscv_cpu_mxl(env); return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 098670e680..b76e4db99c 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -214,10 +214,20 @@ static const VMStateDescription vmstate_kvmtimer =3D { } }; =20 +static int riscv_cpu_post_load(void *opaque, int version_id) +{ + RISCVCPU *cpu =3D opaque; + CPURISCVState *env =3D &cpu->env; + + env->xl =3D cpu_recompute_xl(env); + return 0; +} + const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", .version_id =3D 3, .minimum_version_id =3D 3, + .post_load =3D riscv_cpu_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642695041262320.20592746638954; Thu, 20 Jan 2022 08:10:41 -0800 (PST) Received: from localhost ([::1]:53878 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAa1I-0007Tv-8u for importer@patchew.org; Thu, 20 Jan 2022 11:10:40 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38910) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWVF-00069o-Ui; Thu, 20 Jan 2022 07:25:23 -0500 Received: from out28-1.mail.aliyun.com ([115.124.28.1]:39954) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWV3-00080r-4N; Thu, 20 Jan 2022 07:25:14 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfxKnQ0_1642681504) by smtp.aliyun-inc.com(10.147.40.200); Thu, 20 Jan 2022 20:25:04 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1744883|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0435317-0.00254838-0.95392; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047194; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfxKnQ0_1642681504; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 06/23] target/riscv: Ignore the pc bits above XLEN Date: Thu, 20 Jan 2022 20:20:33 +0800 Message-Id: <20220120122050.41546-7-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.1; envelope-from=zhiwei_liu@c-sky.com; helo=out28-1.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642695045835100001 Content-Type: text/plain; charset="utf-8" The read from PC for translation is in cpu_get_tb_cpu_state, before transla= tion. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8ebcd57af0..d73925a823 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -43,7 +43,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, =20 uint32_t flags =3D 0; =20 - *pc =3D env->pc; + *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; *cs_base =3D 0; =20 if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve= 64f) { --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642695303870898.498990931787; Thu, 20 Jan 2022 08:15:03 -0800 (PST) Received: from localhost ([::1]:33950 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAa5W-0004pd-QZ for importer@patchew.org; Thu, 20 Jan 2022 11:15:02 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39062) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWVa-0006Ln-UV; Thu, 20 Jan 2022 07:25:50 -0500 Received: from out28-147.mail.aliyun.com ([115.124.28.147]:35329) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWVY-0008Ec-Lo; Thu, 20 Jan 2022 07:25:42 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfxOzV3_1642681534) by smtp.aliyun-inc.com(10.147.42.16); Thu, 20 Jan 2022 20:25:34 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07938297|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.35604-0.000583857-0.643376; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047199; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfxOzV3_1642681534; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 07/23] target/riscv: Extend pc for runtime pc write Date: Thu, 20 Jan 2022 20:20:34 +0800 Message-Id: <20220120122050.41546-8-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.147; envelope-from=zhiwei_liu@c-sky.com; helo=out28-147.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642695305436100003 Content-Type: text/plain; charset="utf-8" In some cases, we must restore the guest PC to the address of the start of the TB, such as when the instruction counter hits zero. So extend pc regist= er according to current xlen for these cases. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 736cf1d4e7..eac5f7bf03 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -355,7 +355,12 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - env->pc =3D value; + + if (env->xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t)value; + } else { + env->pc =3D value; + } } =20 static void riscv_cpu_synchronize_from_tb(CPUState *cs, @@ -363,7 +368,13 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - env->pc =3D tb->pc; + RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); + + if (xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t)tb->pc; + } else { + env->pc =3D tb->pc; + } } =20 static bool riscv_cpu_has_work(CPUState *cs) @@ -384,7 +395,12 @@ static bool riscv_cpu_has_work(CPUState *cs) void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, target_ulong *data) { - env->pc =3D data[0]; + RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); + if (xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t)data[0]; + } else { + env->pc =3D data[0]; + } } =20 static void riscv_cpu_reset(DeviceState *dev) --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642698267705781.8796693168597; Thu, 20 Jan 2022 09:04:27 -0800 (PST) Received: from localhost ([::1]:32914 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAarK-00024o-D1 for importer@patchew.org; Thu, 20 Jan 2022 12:04:26 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39248) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWW4-00075Y-PE; Thu, 20 Jan 2022 07:26:14 -0500 Received: from out28-123.mail.aliyun.com ([115.124.28.123]:46034) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWW2-0008Ot-Hn; Thu, 20 Jan 2022 07:26:12 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Mfx8ck2_1642681565) by smtp.aliyun-inc.com(10.147.41.178); Thu, 20 Jan 2022 20:26:05 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436375|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0231685-0.000144035-0.976687; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047213; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.Mfx8ck2_1642681565; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 08/23] target/riscv: Use gdb xml according to max mxlen Date: Thu, 20 Jan 2022 20:20:35 +0800 Message-Id: <20220120122050.41546-9-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.123; envelope-from=zhiwei_liu@c-sky.com; helo=out28-123.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642698269870100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 8 ++--- target/riscv/gdbstub.c | 71 +++++++++++++++++++++++++++++++----------- 2 files changed, 55 insertions(+), 24 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eac5f7bf03..690c879901 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -466,6 +466,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) RISCVCPU *cpu =3D RISCV_CPU(dev); CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); + CPUClass *cc =3D CPU_CLASS(mcc); int priv_version =3D 0; Error *local_err =3D NULL; =20 @@ -516,11 +517,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) switch (env->misa_mxl_max) { #ifdef TARGET_RISCV64 case MXL_RV64: + cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; break; case MXL_RV128: break; #endif case MXL_RV32: + cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; break; default: g_assert_not_reached(); @@ -802,11 +805,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void = *data) cc->gdb_read_register =3D riscv_cpu_gdb_read_register; cc->gdb_write_register =3D riscv_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 33; -#if defined(TARGET_RISCV32) - cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; -#elif defined(TARGET_RISCV64) - cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; -#endif cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index a5429b92d4..f531a74c2f 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -50,11 +50,23 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArra= y *mem_buf, int n) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + target_ulong tmp; =20 if (n < 32) { - return gdb_get_regl(mem_buf, env->gpr[n]); + tmp =3D env->gpr[n]; } else if (n =3D=3D 32) { - return gdb_get_regl(mem_buf, env->pc); + tmp =3D env->pc; + } else { + return 0; + } + + switch (env->misa_mxl_max) { + case MXL_RV32: + return gdb_get_reg32(mem_buf, tmp); + case MXL_RV64: + return gdb_get_reg64(mem_buf, tmp); + default: + g_assert_not_reached(); } return 0; } @@ -63,18 +75,32 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - - if (n =3D=3D 0) { - /* discard writes to x0 */ - return sizeof(target_ulong); - } else if (n < 32) { - env->gpr[n] =3D ldtul_p(mem_buf); - return sizeof(target_ulong); + int length =3D 0; + target_ulong tmp; + + switch (env->misa_mxl_max) { + case MXL_RV32: + tmp =3D (int32_t)ldl_p(mem_buf); + length =3D 4; + break; + case MXL_RV64: + if (env->xl < MXL_RV64) { + tmp =3D (int32_t)ldq_p(mem_buf); + } else { + tmp =3D ldq_p(mem_buf); + } + length =3D 8; + break; + default: + g_assert_not_reached(); + } + if (n > 0 && n < 32) { + env->gpr[n] =3D tmp; } else if (n =3D=3D 32) { - env->pc =3D ldtul_p(mem_buf); - return sizeof(target_ulong); + env->pc =3D tmp; } - return 0; + + return length; } =20 static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) @@ -387,13 +413,20 @@ void riscv_cpu_register_gdb_regs_for_features(CPUStat= e *cs) cs->gdb_num_= regs), "riscv-vector.xml", 0); } -#if defined(TARGET_RISCV32) - gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virt= ual, - 1, "riscv-32bit-virtual.xml", 0); -#elif defined(TARGET_RISCV64) - gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virt= ual, - 1, "riscv-64bit-virtual.xml", 0); -#endif + switch (env->misa_mxl_max) { + case MXL_RV32: + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, + riscv_gdb_set_virtual, + 1, "riscv-32bit-virtual.xml", 0); + break; + case MXL_RV64: + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, + riscv_gdb_set_virtual, + 1, "riscv-64bit-virtual.xml", 0); + break; + default: + g_assert_not_reached(); + } =20 gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_reg= s), --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642695818676267.8472518274946; Thu, 20 Jan 2022 08:23:38 -0800 (PST) Received: from localhost ([::1]:44890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAaDp-00046y-Nm for importer@patchew.org; Thu, 20 Jan 2022 11:23:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39374) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWWa-0007E0-LT; Thu, 20 Jan 2022 07:26:48 -0500 Received: from out28-5.mail.aliyun.com ([115.124.28.5]:37894) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWWY-0008T6-59; Thu, 20 Jan 2022 07:26:43 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfxkfRu_1642681595) by smtp.aliyun-inc.com(10.147.41.137); Thu, 20 Jan 2022 20:26:35 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.2578434|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0196484-0.00170744-0.978644; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047193; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfxkfRu_1642681595; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 09/23] target/riscv: Relax debug check for pm write Date: Thu, 20 Jan 2022 20:20:36 +0800 Message-Id: <20220120122050.41546-10-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.5; envelope-from=zhiwei_liu@c-sky.com; helo=out28-5.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642695821607100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9be2820d2b..c00a82022e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1556,6 +1556,9 @@ static bool check_pm_current_disabled(CPURISCVState *= env, int csrno) int csr_priv =3D get_field(csrno, 0x300); int pm_current; =20 + if (env->debugger) { + return false; + } /* * If priv lvls differ that means we're accessing csr from higher priv= lvl, * so allow the access --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642696155259742.9052097043354; Thu, 20 Jan 2022 08:29:15 -0800 (PST) Received: from localhost ([::1]:53212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAaJG-0001QA-6b for importer@patchew.org; Thu, 20 Jan 2022 11:29:14 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39436) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWX2-0007dZ-FC; Thu, 20 Jan 2022 07:27:12 -0500 Received: from out28-5.mail.aliyun.com ([115.124.28.5]:50735) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWX0-0008Uf-Ku; Thu, 20 Jan 2022 07:27:12 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfyGv8l_1642681626) by smtp.aliyun-inc.com(10.147.41.143); Thu, 20 Jan 2022 20:27:06 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07556053|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.00456155-0.000179524-0.995259; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047202; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfyGv8l_1642681626; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 10/23] target/riscv: Adjust csr write mask with XLEN Date: Thu, 20 Jan 2022 20:20:37 +0800 Message-Id: <20220120122050.41546-11-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.5; envelope-from=zhiwei_liu@c-sky.com; helo=out28-5.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642696155831100001 Content-Type: text/plain; charset="utf-8" Write mask is representing the bits we care about. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 12 ++++++++---- target/riscv/op_helper.c | 3 ++- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 04d3ea237f..631bc1f09e 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -924,7 +924,8 @@ static bool do_csrrw_i128(DisasContext *ctx, int rd, in= t rc, =20 static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a) { - if (get_xl(ctx) < MXL_RV128) { + RISCVMXL xl =3D get_xl(ctx); + if (xl < MXL_RV128) { TCGv src =3D get_gpr(ctx, a->rs1, EXT_NONE); =20 /* @@ -935,7 +936,8 @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a) return do_csrw(ctx, a->csr, src); } =20 - TCGv mask =3D tcg_constant_tl(-1); + TCGv mask =3D tcg_constant_tl(xl =3D=3D MXL_RV32 ? UINT32_MAX : + (target_ulong)-1); return do_csrrw(ctx, a->rd, a->csr, src, mask); } else { TCGv srcl =3D get_gpr(ctx, a->rs1, EXT_NONE); @@ -1013,7 +1015,8 @@ static bool trans_csrrc(DisasContext *ctx, arg_csrrc = *a) =20 static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a) { - if (get_xl(ctx) < MXL_RV128) { + RISCVMXL xl =3D get_xl(ctx); + if (xl < MXL_RV128) { TCGv src =3D tcg_constant_tl(a->rs1); =20 /* @@ -1024,7 +1027,8 @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrw= i *a) return do_csrw(ctx, a->csr, src); } =20 - TCGv mask =3D tcg_constant_tl(-1); + TCGv mask =3D tcg_constant_tl(xl =3D=3D MXL_RV32 ? UINT32_MAX : + (target_ulong)-1); return do_csrrw(ctx, a->rd, a->csr, src, mask); } else { TCGv src =3D tcg_constant_tl(a->rs1); diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 67693cb42b..1a75ba11e6 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -50,7 +50,8 @@ target_ulong helper_csrr(CPURISCVState *env, int csr) =20 void helper_csrw(CPURISCVState *env, int csr, target_ulong src) { - RISCVException ret =3D riscv_csrrw(env, csr, NULL, src, -1); + target_ulong mask =3D env->xl =3D=3D MXL_RV32 ? UINT32_MAX : (target_u= long)-1; + RISCVException ret =3D riscv_csrrw(env, csr, NULL, src, mask); =20 if (ret !=3D RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642696859117849.8158971153583; Thu, 20 Jan 2022 08:40:59 -0800 (PST) Received: from localhost ([::1]:34932 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAaUc-000092-3n for importer@patchew.org; Thu, 20 Jan 2022 11:40:58 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39674) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWYF-0007qJ-9x; Thu, 20 Jan 2022 07:28:27 -0500 Received: from out28-123.mail.aliyun.com ([115.124.28.123]:32823) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWYB-0000Bs-MT; Thu, 20 Jan 2022 07:28:26 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfwHrrd_1642681656) by smtp.aliyun-inc.com(10.147.40.233); Thu, 20 Jan 2022 20:27:36 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436283|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0680127-0.00242263-0.929565; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047208; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfwHrrd_1642681656; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 11/23] target/riscv: Create current pm fields in env Date: Thu, 20 Jan 2022 20:20:38 +0800 Message-Id: <20220120122050.41546-12-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.123; envelope-from=zhiwei_liu@c-sky.com; helo=out28-123.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642696860191100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 4 ++++ target/riscv/cpu_helper.c | 43 +++++++++++++++++++++++++++++++++++++++ target/riscv/csr.c | 19 +++++++++++++++++ target/riscv/machine.c | 1 + 5 files changed, 68 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 690c879901..a120d474df 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -430,6 +430,7 @@ static void riscv_cpu_reset(DeviceState *dev) env->mmte |=3D (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); #endif env->xl =3D riscv_cpu_mxl(env); + riscv_cpu_update_mask(env); cs->exception_index =3D RISCV_EXCP_NONE; env->load_res =3D -1; set_default_nan_mode(1, &env->fp_status); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7657e22a56..6fe842edfd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -266,6 +266,8 @@ struct CPURISCVState { target_ulong upmmask; target_ulong upmbase; #endif + target_ulong cur_pmmask; + target_ulong cur_pmbase; =20 float_status fp_status; =20 @@ -515,6 +517,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, ta= rget_ulong vtype) void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags); =20 +void riscv_cpu_update_mask(CPURISCVState *env); + RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask= ); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d73925a823..b239d721f4 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -122,6 +122,48 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_u= long *pc, *pflags =3D flags; } =20 +void riscv_cpu_update_mask(CPURISCVState *env) +{ + target_ulong mask =3D -1, base =3D 0; + /* + * TODO: Current RVJ spec does not specify + * how the extension interacts with XLEN. + */ +#ifndef CONFIG_USER_ONLY + if (riscv_has_ext(env, RVJ)) { + switch (env->priv) { + case PRV_M: + if (env->mmte & M_PM_ENABLE) { + mask =3D env->mpmmask; + base =3D env->mpmbase; + } + break; + case PRV_S: + if (env->mmte & S_PM_ENABLE) { + mask =3D env->spmmask; + base =3D env->spmbase; + } + break; + case PRV_U: + if (env->mmte & U_PM_ENABLE) { + mask =3D env->upmmask; + base =3D env->upmbase; + } + break; + default: + g_assert_not_reached(); + } + } +#endif + if (env->xl =3D=3D MXL_RV32) { + env->cur_pmmask =3D mask & UINT32_MAX; + env->cur_pmbase =3D base & UINT32_MAX; + } else { + env->cur_pmmask =3D mask; + env->cur_pmbase =3D base; + } +} + #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) { @@ -334,6 +376,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulon= g newpriv) /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv =3D newpriv; env->xl =3D cpu_recompute_xl(env); + riscv_cpu_update_mask(env); =20 /* * Clear the load reservation - otherwise a reservation placed in one diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c00a82022e..292f7e1624 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1607,6 +1607,7 @@ static RISCVException write_mmte(CPURISCVState *env, = int csrno, /* hardwiring pm.instruction bit to 0, since it's not supported yet */ wpri_val &=3D ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); env->mmte =3D wpri_val | PM_EXT_DIRTY; + riscv_cpu_update_mask(env); =20 /* Set XS and SD bits, since PM CSRs are dirty */ mstatus =3D env->mstatus | MSTATUS_XS; @@ -1682,6 +1683,9 @@ static RISCVException write_mpmmask(CPURISCVState *en= v, int csrno, uint64_t mstatus; =20 env->mpmmask =3D val; + if ((env->priv =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE)) { + env->cur_pmmask =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1707,6 +1711,9 @@ static RISCVException write_spmmask(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } env->spmmask =3D val; + if ((env->priv =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE)) { + env->cur_pmmask =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1732,6 +1739,9 @@ static RISCVException write_upmmask(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } env->upmmask =3D val; + if ((env->priv =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE)) { + env->cur_pmmask =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1753,6 +1763,9 @@ static RISCVException write_mpmbase(CPURISCVState *en= v, int csrno, uint64_t mstatus; =20 env->mpmbase =3D val; + if ((env->priv =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE)) { + env->cur_pmbase =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1778,6 +1791,9 @@ static RISCVException write_spmbase(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } env->spmbase =3D val; + if ((env->priv =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE)) { + env->cur_pmbase =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1803,6 +1819,9 @@ static RISCVException write_upmbase(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } env->upmbase =3D val; + if ((env->priv =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE)) { + env->cur_pmbase =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ diff --git a/target/riscv/machine.c b/target/riscv/machine.c index b76e4db99c..a4b7859c2a 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -220,6 +220,7 @@ static int riscv_cpu_post_load(void *opaque, int versio= n_id) CPURISCVState *env =3D &cpu->env; =20 env->xl =3D cpu_recompute_xl(env); + riscv_cpu_update_mask(env); return 0; } =20 --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642697471707306.49030067816705; Thu, 20 Jan 2022 08:51:11 -0800 (PST) Received: from localhost ([::1]:43616 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAaeU-0006U5-JT for importer@patchew.org; Thu, 20 Jan 2022 11:51:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39678) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWYF-0007qg-EH; Thu, 20 Jan 2022 07:28:27 -0500 Received: from out28-97.mail.aliyun.com ([115.124.28.97]:58851) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWYB-0000DA-M5; Thu, 20 Jan 2022 07:28:27 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfxfjN1_1642681687) by smtp.aliyun-inc.com(10.147.43.230); Thu, 20 Jan 2022 20:28:07 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07450344|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0061735-0.00216247-0.991664; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047204; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfxfjN1_1642681687; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 12/23] target/riscv: Alloc tcg global for cur_pm[mask|base] Date: Thu, 20 Jan 2022 20:20:39 +0800 Message-Id: <20220120122050.41546-13-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.97; envelope-from=zhiwei_liu@c-sky.com; helo=out28-97.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642697473673100001 Content-Type: text/plain; charset="utf-8" Replace the array of pm_mask/pm_base with scalar variables. Remove the cached array value in DisasContext. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 32 ++++++++------------------------ 1 file changed, 8 insertions(+), 24 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2a88bd99dc..43e2ec6dce 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -38,8 +38,8 @@ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions= */ static TCGv load_res; static TCGv load_val; /* globals for PM CSRs */ -static TCGv pm_mask[4]; -static TCGv pm_base[4]; +static TCGv pm_mask; +static TCGv pm_base; =20 #include "exec/gen-icount.h" =20 @@ -109,8 +109,6 @@ typedef struct DisasContext { TCGv temp[4]; /* PointerMasking extension */ bool pm_enabled; - TCGv pm_mask; - TCGv pm_base; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -403,8 +401,8 @@ static TCGv gen_pm_adjust_address(DisasContext *s, TCGv= src) return src; } else { temp =3D temp_new(s); - tcg_gen_andc_tl(temp, src, s->pm_mask); - tcg_gen_or_tl(temp, temp, s->pm_base); + tcg_gen_andc_tl(temp, src, pm_mask); + tcg_gen_or_tl(temp, temp, pm_base); return temp; } } @@ -929,10 +927,6 @@ static void riscv_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->ntemp =3D 0; memset(ctx->temp, 0, sizeof(ctx->temp)); ctx->pm_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); - int priv =3D tb_flags & TB_FLAGS_PRIV_MMU_MASK; - ctx->pm_mask =3D pm_mask[priv]; - ctx->pm_base =3D pm_base[priv]; - ctx->zero =3D tcg_constant_tl(0); } =20 @@ -1050,19 +1044,9 @@ void riscv_translate_init(void) "load_res"); load_val =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_= val), "load_val"); -#ifndef CONFIG_USER_ONLY /* Assign PM CSRs to tcg globals */ - pm_mask[PRV_U] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmma= sk"); - pm_base[PRV_U] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmba= se"); - pm_mask[PRV_S] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmma= sk"); - pm_base[PRV_S] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmba= se"); - pm_mask[PRV_M] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmma= sk"); - pm_base[PRV_M] =3D - tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmba= se"); -#endif + pm_mask =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pm= mask), + "pmmask"); + pm_base =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pm= base), + "pmbase"); } --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642697887341160.49271539583265; Thu, 20 Jan 2022 08:58:07 -0800 (PST) Received: from localhost ([::1]:52204 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAalC-00048o-9f for importer@patchew.org; Thu, 20 Jan 2022 11:58:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39764) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWYX-000080-0l; Thu, 20 Jan 2022 07:28:45 -0500 Received: from out28-220.mail.aliyun.com ([115.124.28.220]:51646) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWYU-0000Ht-Pg; Thu, 20 Jan 2022 07:28:44 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Mfy.0xc_1642681717) by smtp.aliyun-inc.com(10.147.40.44); Thu, 20 Jan 2022 20:28:38 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0112046-0.000181959-0.988613; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047213; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.Mfy.0xc_1642681717; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 13/23] target/riscv: Calculate address according to XLEN Date: Thu, 20 Jan 2022 20:20:40 +0800 Message-Id: <20220120122050.41546-14-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.220; envelope-from=zhiwei_liu@c-sky.com; helo=out28-220.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642697889706100001 Content-Type: text/plain; charset="utf-8" Define one common function to compute a canonical address from a register plus offset. Merge gen_pm_adjust_address into this function. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 9 +++------ target/riscv/insn_trans/trans_rvd.c.inc | 19 ++----------------- target/riscv/insn_trans/trans_rvf.c.inc | 19 ++----------------- target/riscv/insn_trans/trans_rvi.c.inc | 18 ++---------------- target/riscv/translate.c | 25 ++++++++++++------------- 5 files changed, 21 insertions(+), 69 deletions(-) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index 86032fa9a7..45db82c9be 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -20,12 +20,11 @@ =20 static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) { - TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); + TCGv src1 =3D get_address(ctx, a->rs1, 0); =20 if (a->rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - src1 =3D gen_pm_adjust_address(ctx, src1); tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); if (a->aq) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -44,8 +43,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemO= p mop) TCGLabel *l1 =3D gen_new_label(); TCGLabel *l2 =3D gen_new_label(); =20 - src1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); - src1 =3D gen_pm_adjust_address(ctx, src1); + src1 =3D get_address(ctx, a->rs1, 0); tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); =20 /* @@ -83,10 +81,9 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, MemOp mop) { TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src1 =3D get_address(ctx, a->rs1, 0); TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 - src1 =3D gen_pm_adjust_address(ctx, src1); func(dest, src1, src2, ctx->mem_idx, mop); =20 gen_set_gpr(ctx, a->rd, dest); diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index ed444b042a..091ed3a8ad 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -25,14 +25,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - + addr =3D get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEUQ); =20 mark_fs_dirty(ctx); @@ -46,16 +39,8 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - + addr =3D get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUQ); - return true; } =20 diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index b5459249c4..0aac87f7db 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -31,14 +31,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - + addr =3D get_address(ctx, a->rs1, a->imm); dest =3D cpu_fpr[a->rd]; tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL); gen_nanbox_s(dest, dest); @@ -54,16 +47,8 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - if (a->imm) { - TCGv temp =3D tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - + addr =3D get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL); - return true; } =20 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 631bc1f09e..3cd1b3f877 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -226,14 +226,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop) { TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); + TCGv addr =3D get_address(ctx, a->rs1, a->imm); =20 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop); gen_set_gpr(ctx, a->rd, dest); @@ -330,16 +323,9 @@ static bool trans_ldu(DisasContext *ctx, arg_ldu *a) =20 static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop) { - TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv addr =3D get_address(ctx, a->rs1, a->imm); TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); return true; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 43e2ec6dce..33564d059d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -390,21 +390,20 @@ static void gen_jal(DisasContext *ctx, int rd, target= _ulong imm) ctx->base.is_jmp =3D DISAS_NORETURN; } =20 -/* - * Generates address adjustment for PointerMasking - */ -static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src) +/* Compute a canonical address from a register plus offset. */ +static TCGv get_address(DisasContext *ctx, int rs1, int imm) { - TCGv temp; - if (!s->pm_enabled) { - /* Load unmodified address */ - return src; - } else { - temp =3D temp_new(s); - tcg_gen_andc_tl(temp, src, pm_mask); - tcg_gen_or_tl(temp, temp, pm_base); - return temp; + TCGv addr =3D temp_new(ctx); + TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); + + tcg_gen_addi_tl(addr, src1, imm); + if (ctx->pm_enabled) { + tcg_gen_and_tl(addr, addr, pm_mask); + tcg_gen_or_tl(addr, addr, pm_base); + } else if (get_xl(ctx) =3D=3D MXL_RV32) { + tcg_gen_ext32u_tl(addr, addr); } + return addr; } =20 #ifndef CONFIG_USER_ONLY --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642698758875744.0229559033723; Thu, 20 Jan 2022 09:12:38 -0800 (PST) Received: from localhost ([::1]:41550 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAazF-0008CL-N5 for importer@patchew.org; Thu, 20 Jan 2022 12:12:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40586) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWZ1-0000TU-Oi; Thu, 20 Jan 2022 07:29:15 -0500 Received: from out28-51.mail.aliyun.com ([115.124.28.51]:41987) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWYy-0000LO-Ob; Thu, 20 Jan 2022 07:29:15 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfxgUMJ_1642681748) by smtp.aliyun-inc.com(10.147.41.120); Thu, 20 Jan 2022 20:29:08 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07438365|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.00462344-3.32179e-05-0.995343; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047198; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfxgUMJ_1642681748; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 14/23] target/riscv: Split pm_enabled into mask and base Date: Thu, 20 Jan 2022 20:20:41 +0800 Message-Id: <20220120122050.41546-15-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.51; envelope-from=zhiwei_liu@c-sky.com; helo=out28-51.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642698761084100001 Content-Type: text/plain; charset="utf-8" Use cached cur_pmmask and cur_pmbase to infer the current PM mode. This may decrease the TCG IR by one when pm_enabled is true and pm_base_enabled is false. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 3 ++- target/riscv/cpu_helper.c | 24 ++++++------------------ target/riscv/translate.c | 12 ++++++++---- 3 files changed, 16 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6fe842edfd..89621e1996 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -448,7 +448,8 @@ FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ FIELD(TB_FLAGS, XL, 20, 2) /* If PointerMasking should be applied */ -FIELD(TB_FLAGS, PM_ENABLED, 22, 1) +FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) +FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b239d721f4..502aee84ab 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -97,27 +97,15 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ul= ong *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, get_field(env->mstatus_hs, MSTATUS_VS)); } - if (riscv_has_ext(env, RVJ)) { - int priv =3D flags & TB_FLAGS_PRIV_MMU_MASK; - bool pm_enabled =3D false; - switch (priv) { - case PRV_U: - pm_enabled =3D env->mmte & U_PM_ENABLE; - break; - case PRV_S: - pm_enabled =3D env->mmte & S_PM_ENABLE; - break; - case PRV_M: - pm_enabled =3D env->mmte & M_PM_ENABLE; - break; - default: - g_assert_not_reached(); - } - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled); - } #endif =20 flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); + if (env->cur_pmmask < (env->xl =3D=3D MXL_RV32 ? UINT32_MAX : UINT64_M= AX)) { + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); + } + if (env->cur_pmbase !=3D 0) { + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); + } =20 *pflags =3D flags; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 33564d059d..f0bbe80875 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -108,7 +108,8 @@ typedef struct DisasContext { /* Space for 3 operands plus 1 extra for address computation. */ TCGv temp[4]; /* PointerMasking extension */ - bool pm_enabled; + bool pm_mask_enabled; + bool pm_base_enabled; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -397,12 +398,14 @@ static TCGv get_address(DisasContext *ctx, int rs1, i= nt imm) TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_addi_tl(addr, src1, imm); - if (ctx->pm_enabled) { + if (ctx->pm_mask_enabled) { tcg_gen_and_tl(addr, addr, pm_mask); - tcg_gen_or_tl(addr, addr, pm_base); } else if (get_xl(ctx) =3D=3D MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } + if (ctx->pm_base_enabled) { + tcg_gen_or_tl(addr, addr, pm_base); + } return addr; } =20 @@ -925,7 +928,8 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->cs =3D cs; ctx->ntemp =3D 0; memset(ctx->temp, 0, sizeof(ctx->temp)); - ctx->pm_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); + ctx->pm_mask_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLE= D); + ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); ctx->zero =3D tcg_constant_tl(0); } =20 --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642698262526305.54103833644; Thu, 20 Jan 2022 09:04:22 -0800 (PST) Received: from localhost ([::1]:60752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAarF-0001ov-2m for importer@patchew.org; Thu, 20 Jan 2022 12:04:21 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWZb-00014S-9Y; Thu, 20 Jan 2022 07:29:51 -0500 Received: from out28-97.mail.aliyun.com ([115.124.28.97]:37065) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWZT-0000Pp-T9; Thu, 20 Jan 2022 07:29:45 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfyHI8C_1642681778) by smtp.aliyun-inc.com(10.147.41.199); Thu, 20 Jan 2022 20:29:39 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436661|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0405165-0.00021043-0.959273; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047212; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfyHI8C_1642681778; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 15/23] target/riscv: Split out the vill from vtype Date: Thu, 20 Jan 2022 20:20:42 +0800 Message-Id: <20220120122050.41546-16-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.97; envelope-from=zhiwei_liu@c-sky.com; helo=out28-97.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642698266077100001 Content-Type: text/plain; charset="utf-8" We need not specially process vtype when XLEN changes. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 3 +-- target/riscv/csr.c | 13 ++++++++++++- target/riscv/machine.c | 5 +++-- target/riscv/vector_helper.c | 3 ++- 5 files changed, 19 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 89621e1996..6c740b92c1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -125,6 +125,7 @@ struct CPURISCVState { target_ulong vl; target_ulong vstart; target_ulong vtype; + bool vill; =20 target_ulong pc; target_ulong load_res; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 502aee84ab..327a2c4f1d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -60,8 +60,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, uint32_t maxsz =3D vlmax << sew; bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) && (maxsz >=3D 8); - flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, - FIELD_EX64(env->vtype, VTYPE, VILL)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, sew); flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, FIELD_EX64(env->vtype, VTYPE, VLMUL)); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 292f7e1624..b11d92b51b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -283,7 +283,18 @@ static RISCVException write_fcsr(CPURISCVState *env, i= nt csrno, static RISCVException read_vtype(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->vtype; + uint64_t vill; + switch (env->xl) { + case MXL_RV32: + vill =3D (uint32_t)env->vill << 31; + break; + case MXL_RV64: + vill =3D (uint64_t)env->vill << 63; + break; + default: + g_assert_not_reached(); + } + *val =3D (target_ulong)vill | env->vtype; return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index a4b7859c2a..740e11fcff 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -124,8 +124,8 @@ static bool vector_needed(void *opaque) =20 static const VMStateDescription vmstate_vector =3D { .name =3D "cpu/vector", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .needed =3D vector_needed, .fields =3D (VMStateField[]) { VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64= ), @@ -134,6 +134,7 @@ static const VMStateDescription vmstate_vector =3D { VMSTATE_UINTTL(env.vl, RISCVCPU), VMSTATE_UINTTL(env.vstart, RISCVCPU), VMSTATE_UINTTL(env.vtype, RISCVCPU), + VMSTATE_BOOL(env.vill, RISCVCPU), VMSTATE_END_OF_LIST() } }; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ad505ec9b2..a9484c22ea 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -52,7 +52,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ul= ong s1, || (ediv !=3D 0) || (reserved !=3D 0)) { /* only set vill bit. */ - env->vtype =3D FIELD_DP64(0, VTYPE, VILL, 1); + env->vill =3D 1; + env->vtype =3D 0; env->vl =3D 0; env->vstart =3D 0; return 0; --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164269941461438.95715939925799; Thu, 20 Jan 2022 09:23:34 -0800 (PST) Received: from localhost ([::1]:51366 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAb9p-0007Dt-6P for importer@patchew.org; Thu, 20 Jan 2022 12:23:33 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40862) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWaE-0001ew-OD; Thu, 20 Jan 2022 07:30:32 -0500 Received: from out28-1.mail.aliyun.com ([115.124.28.1]:50022) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWaC-0000V0-7s; Thu, 20 Jan 2022 07:30:30 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfwUPk6_1642681809) by smtp.aliyun-inc.com(10.147.40.7); Thu, 20 Jan 2022 20:30:09 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.08933485|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.00746413-0.000532751-0.992003; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047207; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfwUPk6_1642681809; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 16/23] target/riscv: Adjust vsetvl according to XLEN Date: Thu, 20 Jan 2022 20:20:43 +0800 Message-Id: <20220120122050.41546-17-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.1; envelope-from=zhiwei_liu@c-sky.com; helo=out28-1.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642699416882100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 5 +++++ target/riscv/vector_helper.c | 7 +++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6c740b92c1..fe58ccaeae 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -491,6 +491,11 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState = *env) } #endif =20 +static inline int riscv_cpu_xlen(CPURISCVState *env) +{ + return 16 << env->xl; +} + /* * Encode LMUL to lmul as follows: * LMUL vlmul lmul diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a9484c22ea..8b7c9ec890 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -36,8 +36,11 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_u= long s1, uint64_t lmul =3D FIELD_EX64(s2, VTYPE, VLMUL); uint16_t sew =3D 8 << FIELD_EX64(s2, VTYPE, VSEW); uint8_t ediv =3D FIELD_EX64(s2, VTYPE, VEDIV); - bool vill =3D FIELD_EX64(s2, VTYPE, VILL); - target_ulong reserved =3D FIELD_EX64(s2, VTYPE, RESERVED); + int xlen =3D riscv_cpu_xlen(env); + bool vill =3D (s2 >> (xlen - 1)) & 0x1; + target_ulong reserved =3D s2 & + MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, + xlen - 1 - R_VTYPE_RESERVED_SH= IFT); =20 if (lmul & 4) { /* Fractional LMUL. */ --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642700054331477.2868583517808; Thu, 20 Jan 2022 09:34:14 -0800 (PST) Received: from localhost ([::1]:59950 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAbK9-0004xq-0v for importer@patchew.org; Thu, 20 Jan 2022 12:34:13 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40980) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWak-0001k2-Rd; Thu, 20 Jan 2022 07:31:08 -0500 Received: from out28-197.mail.aliyun.com ([115.124.28.197]:57077) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWai-0000i0-0h; Thu, 20 Jan 2022 07:31:02 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Mfxlpbl_1642681839) by smtp.aliyun-inc.com(10.147.40.2); Thu, 20 Jan 2022 20:30:40 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1636855|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0698312-0.000432218-0.929737; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047202; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.Mfxlpbl_1642681839; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 17/23] target/riscv: Remove VILL field in VTYPE Date: Thu, 20 Jan 2022 20:20:44 +0800 Message-Id: <20220120122050.41546-18-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.197; envelope-from=zhiwei_liu@c-sky.com; helo=out28-197.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642700056488100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Acked-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fe58ccaeae..55635d68d5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -111,7 +111,6 @@ FIELD(VTYPE, VTA, 6, 1) FIELD(VTYPE, VMA, 7, 1) FIELD(VTYPE, VEDIV, 8, 2) FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) -FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) =20 struct CPURISCVState { target_ulong gpr[32]; --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642700620811417.7576627491958; Thu, 20 Jan 2022 09:43:40 -0800 (PST) Received: from localhost ([::1]:40110 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAbTH-0002oW-QG for importer@patchew.org; Thu, 20 Jan 2022 12:43:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41110) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWb3-0001td-Ku; Thu, 20 Jan 2022 07:31:25 -0500 Received: from out28-74.mail.aliyun.com ([115.124.28.74]:45047) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWax-0000vb-UQ; Thu, 20 Jan 2022 07:31:21 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfwiV7I_1642681870) by smtp.aliyun-inc.com(10.147.40.26); Thu, 20 Jan 2022 20:31:10 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1406242|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0508573-0.000449781-0.948693; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047209; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfwiV7I_1642681870; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 18/23] target/riscv: Fix check range for first fault only Date: Thu, 20 Jan 2022 20:20:45 +0800 Message-Id: <20220120122050.41546-19-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.74; envelope-from=zhiwei_liu@c-sky.com; helo=out28-74.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642700624922100003 Content-Type: text/plain; charset="utf-8" Only check the range that has passed the address translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 8b7c9ec890..efb3129532 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -500,12 +500,12 @@ vext_ldff(void *vd, void *v0, target_ulong base, cpu_mmu_index(env, false)); if (host) { #ifdef CONFIG_USER_ONLY - if (page_check_range(addr, nf << esz, PAGE_READ) < 0) { + if (page_check_range(addr, offset, PAGE_READ) < 0) { vl =3D i; goto ProbeSuccess; } #else - probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD); + probe_pages(env, addr, offset, ra, MMU_DATA_LOAD); #endif } else { vl =3D i; --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164269876090185.234159145391; Thu, 20 Jan 2022 09:12:40 -0800 (PST) Received: from localhost ([::1]:41638 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAazH-0008GS-GV for importer@patchew.org; Thu, 20 Jan 2022 12:12:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41224) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWbU-0002Au-Me; Thu, 20 Jan 2022 07:31:48 -0500 Received: from out28-145.mail.aliyun.com ([115.124.28.145]:34717) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWbR-0000z6-NH; Thu, 20 Jan 2022 07:31:48 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfxQutw_1642681900) by smtp.aliyun-inc.com(10.147.43.95); Thu, 20 Jan 2022 20:31:40 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436795|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0540385-0.000931329-0.94503; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047202; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfxQutw_1642681900; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 19/23] target/riscv: Adjust vector address with mask Date: Thu, 20 Jan 2022 20:20:46 +0800 Message-Id: <20220120122050.41546-20-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.145; envelope-from=zhiwei_liu@c-sky.com; helo=out28-145.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642698762638100005 Content-Type: text/plain; charset="utf-8" The mask comes from the pointer masking extension, or the max value corresponding to XLEN bits. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index efb3129532..020d2e841f 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -139,6 +139,11 @@ static inline uint32_t vext_max_elems(uint32_t desc, u= int32_t esz) return scale < 0 ? vlenb >> -scale : vlenb << scale; } =20 +static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad= dr) +{ + return (addr & env->cur_pmmask) | env->cur_pmbase; +} + /* * This function checks watchpoint before real load operation. * @@ -156,12 +161,12 @@ static void probe_pages(CPURISCVState *env, target_ul= ong addr, target_ulong pagelen =3D -(addr | TARGET_PAGE_MASK); target_ulong curlen =3D MIN(pagelen, len); =20 - probe_access(env, addr, curlen, access_type, + probe_access(env, adjust_addr(env, addr), curlen, access_type, cpu_mmu_index(env, false), ra); if (len > curlen) { addr +=3D curlen; curlen =3D len - curlen; - probe_access(env, addr, curlen, access_type, + probe_access(env, adjust_addr(env, addr), curlen, access_type, cpu_mmu_index(env, false), ra); } } @@ -239,7 +244,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, k =3D 0; while (k < nf) { target_ulong addr =3D base + stride * i + (k << esz); - ldst_elem(env, addr, i + k * max_elems, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, = ra); k++; } } @@ -295,7 +300,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState= *env, uint32_t desc, k =3D 0; while (k < nf) { target_ulong addr =3D base + ((i * nf + k) << esz); - ldst_elem(env, addr, i + k * max_elems, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, = ra); k++; } } @@ -409,7 +414,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, k =3D 0; while (k < nf) { abi_ptr addr =3D get_index_addr(base, i, vs2) + (k << esz); - ldst_elem(env, addr, i + k * max_elems, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, = ra); k++; } } @@ -488,7 +493,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, if (!vm && !vext_elem_mask(v0, i)) { continue; } - addr =3D base + i * (nf << esz); + addr =3D adjust_addr(env, base + i * (nf << esz)); if (i =3D=3D 0) { probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD); } else { @@ -515,7 +520,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, break; } remain -=3D offset; - addr +=3D offset; + addr =3D adjust_addr(env, addr + offset); } } } @@ -531,7 +536,7 @@ ProbeSuccess: } while (k < nf) { target_ulong addr =3D base + ((i * nf + k) << esz); - ldst_elem(env, addr, i + k * max_elems, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, = ra); k++; } } @@ -585,7 +590,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVSt= ate *env, uint32_t desc, /* load/store rest of elements of current segment pointed by vstar= t */ for (pos =3D off; pos < max_elems; pos++, env->vstart++) { target_ulong addr =3D base + ((pos + k * max_elems) << esz); - ldst_elem(env, addr, pos + k * max_elems, vd, ra); + ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd= , ra); } k++; } @@ -594,7 +599,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVSt= ate *env, uint32_t desc, for (; k < nf; k++) { for (i =3D 0; i < max_elems; i++, env->vstart++) { target_ulong addr =3D base + ((i + k * max_elems) << esz); - ldst_elem(env, addr, i + k * max_elems, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, = ra); } } =20 --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16426968803791008.369562940383; Thu, 20 Jan 2022 08:41:20 -0800 (PST) Received: from localhost ([::1]:35226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAaUw-0000Kf-97 for importer@patchew.org; Thu, 20 Jan 2022 11:41:18 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41390) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWc2-00032a-GR; Thu, 20 Jan 2022 07:32:22 -0500 Received: from out28-98.mail.aliyun.com ([115.124.28.98]:43628) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWbz-00013S-DP; Thu, 20 Jan 2022 07:32:22 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfxfkRC_1642681931) by smtp.aliyun-inc.com(10.147.43.230); Thu, 20 Jan 2022 20:32:11 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1794379|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.00632418-5.02523e-05-0.993626; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047188; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfxfkRC_1642681931; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 20/23] target/riscv: Adjust scalar reg in vector with XLEN Date: Thu, 20 Jan 2022 20:20:47 +0800 Message-Id: <20220120122050.41546-21-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.98; envelope-from=zhiwei_liu@c-sky.com; helo=out28-98.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642696881582100002 Content-Type: text/plain; charset="utf-8" When sew <=3D 32bits, not need to extend scalar reg. When sew > 32bits, if xlen is less that sew, we should sign extend the scalar register, except explicitly specified by the spec. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index e03959c46f..f85a9e83b4 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1258,7 +1258,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, uint32_t vm, dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); - src1 =3D get_gpr(s, rs1, EXT_NONE); + src1 =3D get_gpr(s, rs1, EXT_SIGN); =20 data =3D FIELD_DP32(data, VDATA, VM, vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164269931714654.44768769763084; Thu, 20 Jan 2022 09:21:57 -0800 (PST) Received: from localhost ([::1]:50382 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAb8F-0006RD-Mq for importer@patchew.org; Thu, 20 Jan 2022 12:21:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41552) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWda-00038B-9l; Thu, 20 Jan 2022 07:34:00 -0500 Received: from out28-1.mail.aliyun.com ([115.124.28.1]:41464) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWch-000164-8P; Thu, 20 Jan 2022 07:33:18 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfwiVX9_1642681961) by smtp.aliyun-inc.com(10.147.40.26); Thu, 20 Jan 2022 20:32:41 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.08822103|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.261329-0.000289173-0.738382; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047205; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=8; SR=0; TI=SMTPD_---.MfwiVX9_1642681961; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor Date: Thu, 20 Jan 2022 20:20:48 +0800 Message-Id: <20220120122050.41546-22-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.1; envelope-from=zhiwei_liu@c-sky.com; helo=out28-1.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642699321016100001 Content-Type: text/plain; charset="utf-8" When swap regs for hypervisor, the value of vsstatus or mstatus_hs should have the right XLEN. Otherwise, it will propagate to mstatus. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a120d474df..1cb0436187 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -422,6 +422,16 @@ static void riscv_cpu_reset(DeviceState *dev) */ env->mstatus =3D set_field(env->mstatus, MSTATUS64_SXL, env->misa_= mxl); env->mstatus =3D set_field(env->mstatus, MSTATUS64_UXL, env->misa_= mxl); + if (riscv_has_ext(env, RVH)) { + env->vsstatus =3D set_field(env->vsstatus, + MSTATUS64_SXL, env->misa_mxl); + env->vsstatus =3D set_field(env->vsstatus, + MSTATUS64_UXL, env->misa_mxl); + env->mstatus_hs =3D set_field(env->mstatus_hs, + MSTATUS64_SXL, env->misa_mxl); + env->mstatus_hs =3D set_field(env->mstatus_hs, + MSTATUS64_UXL, env->misa_mxl); + } } env->mcause =3D 0; env->pc =3D env->resetvec; --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16427009659471014.9429029330065; Thu, 20 Jan 2022 09:49:25 -0800 (PST) Received: from localhost ([::1]:49238 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAbYq-0000mY-Oi for importer@patchew.org; Thu, 20 Jan 2022 12:49:24 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41598) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWde-00038U-4l; Thu, 20 Jan 2022 07:34:03 -0500 Received: from out28-99.mail.aliyun.com ([115.124.28.99]:37280) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWdP-0001xU-Kh; Thu, 20 Jan 2022 07:33:59 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Mfx8eZi_1642681992) by smtp.aliyun-inc.com(10.147.41.178); Thu, 20 Jan 2022 20:33:12 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07600669|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.070847-5.90399e-06-0.929147; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047188; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.Mfx8eZi_1642681992; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 22/23] target/riscv: Enable uxl field write Date: Thu, 20 Jan 2022 20:20:49 +0800 Message-Id: <20220120122050.41546-23-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.99; envelope-from=zhiwei_liu@c-sky.com; helo=out28-99.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642700967924100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 28 ++++++++++++++++++++++------ 2 files changed, 25 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 5a6d49aa64..7c87433645 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -449,6 +449,9 @@ typedef enum { #define COUNTEREN_IR (1 << 2) #define COUNTEREN_HPM3 (1 << 3) =20 +/* vsstatus CSR bits */ +#define VSSTATUS64_UXL 0x0000000300000000ULL + /* Privilege modes */ #define PRV_U 0 #define PRV_S 1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b11d92b51b..523d07a95e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -496,7 +496,7 @@ static const target_ulong vs_delegable_excps =3D DELEGA= BLE_EXCPS & (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | - SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS | (target_ulong)SSTATUS64_UXL; + SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP; static const target_ulong hip_writable_mask =3D MIP_VSSIP; static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | M= IP_VSEIP; @@ -572,6 +572,7 @@ static RISCVException write_mstatus(CPURISCVState *env,= int csrno, { uint64_t mstatus =3D env->mstatus; uint64_t mask =3D 0; + RISCVMXL xl =3D riscv_cpu_mxl(env); =20 /* flush tlb on mstatus fields that affect VM */ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | @@ -583,21 +584,22 @@ static RISCVException write_mstatus(CPURISCVState *en= v, int csrno, MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | MSTATUS_TW | MSTATUS_VS; =20 - if (riscv_cpu_mxl(env) !=3D MXL_RV32) { + if (xl !=3D MXL_RV32) { /* * RV32: MPV and GVA are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. */ mask |=3D MSTATUS_MPV | MSTATUS_GVA; + if ((val & MSTATUS64_UXL) !=3D 0) { + mask |=3D MSTATUS64_UXL; + } } =20 mstatus =3D (mstatus & ~mask) | (val & mask); =20 - RISCVMXL xl =3D riscv_cpu_mxl(env); if (xl > MXL_RV32) { - /* SXL and UXL fields are for now read only */ + /* SXL field is for now read only */ mstatus =3D set_field(mstatus, MSTATUS64_SXL, xl); - mstatus =3D set_field(mstatus, MSTATUS64_UXL, xl); } env->mstatus =3D mstatus; env->xl =3D cpu_recompute_xl(env); @@ -898,6 +900,9 @@ static RISCVException read_sstatus_i128(CPURISCVState *= env, int csrno, { uint64_t mask =3D sstatus_v1_10_mask; uint64_t sstatus =3D env->mstatus & mask; + if (env->xl !=3D MXL_RV32) { + mask |=3D SSTATUS64_UXL; + } =20 *val =3D int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); return RISCV_EXCP_NONE; @@ -907,7 +912,9 @@ static RISCVException read_sstatus(CPURISCVState *env, = int csrno, target_ulong *val) { target_ulong mask =3D (sstatus_v1_10_mask); - + if (env->xl !=3D MXL_RV32) { + mask |=3D SSTATUS64_UXL; + } /* TODO: Use SXL not MXL. */ *val =3D add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); return RISCV_EXCP_NONE; @@ -917,6 +924,12 @@ static RISCVException write_sstatus(CPURISCVState *env= , int csrno, target_ulong val) { target_ulong mask =3D (sstatus_v1_10_mask); + + if (env->xl !=3D MXL_RV32) { + if ((val & SSTATUS64_UXL) !=3D 0) { + mask |=3D SSTATUS64_UXL; + } + } target_ulong newval =3D (env->mstatus & ~mask) | (val & mask); return write_mstatus(env, CSR_MSTATUS, newval); } @@ -1380,6 +1393,9 @@ static RISCVException write_vsstatus(CPURISCVState *e= nv, int csrno, target_ulong val) { uint64_t mask =3D (target_ulong)-1; + if ((val & VSSTATUS64_UXL) =3D=3D 0) { + mask &=3D ~VSSTATUS64_UXL; + } env->vsstatus =3D (env->vsstatus & ~mask) | (uint64_t)val; return RISCV_EXCP_NONE; } --=20 2.25.1 From nobody Mon Apr 29 12:39:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642697553050553.7826157019332; Thu, 20 Jan 2022 08:52:33 -0800 (PST) Received: from localhost ([::1]:44730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAafl-0007HI-Ur for importer@patchew.org; Thu, 20 Jan 2022 11:52:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41692) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWdj-00039d-L6; Thu, 20 Jan 2022 07:34:10 -0500 Received: from out28-220.mail.aliyun.com ([115.124.28.220]:46392) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAWdf-0001zR-I5; Thu, 20 Jan 2022 07:34:06 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.MfwUQha_1642682022) by smtp.aliyun-inc.com(10.147.40.7); Thu, 20 Jan 2022 20:33:42 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1040515|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0299025-1.5058e-05-0.970082; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047187; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=8; SR=0; TI=SMTPD_---.MfwUQha_1642682022; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 23/23] target/riscv: Relax UXL field for debugging Date: Thu, 20 Jan 2022 20:20:50 +0800 Message-Id: <20220120122050.41546-24-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com> References: <20220120122050.41546-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.220; envelope-from=zhiwei_liu@c-sky.com; helo=out28-220.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642697556367100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/csr.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 523d07a95e..e5f9d4ef93 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -584,7 +584,7 @@ static RISCVException write_mstatus(CPURISCVState *env,= int csrno, MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | MSTATUS_TW | MSTATUS_VS; =20 - if (xl !=3D MXL_RV32) { + if (xl !=3D MXL_RV32 || env->debugger) { /* * RV32: MPV and GVA are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. @@ -900,7 +900,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *= env, int csrno, { uint64_t mask =3D sstatus_v1_10_mask; uint64_t sstatus =3D env->mstatus & mask; - if (env->xl !=3D MXL_RV32) { + if (env->xl !=3D MXL_RV32 || env->debugger) { mask |=3D SSTATUS64_UXL; } =20 @@ -912,7 +912,7 @@ static RISCVException read_sstatus(CPURISCVState *env, = int csrno, target_ulong *val) { target_ulong mask =3D (sstatus_v1_10_mask); - if (env->xl !=3D MXL_RV32) { + if (env->xl !=3D MXL_RV32 || env->debugger) { mask |=3D SSTATUS64_UXL; } /* TODO: Use SXL not MXL. */ @@ -925,7 +925,7 @@ static RISCVException write_sstatus(CPURISCVState *env,= int csrno, { target_ulong mask =3D (sstatus_v1_10_mask); =20 - if (env->xl !=3D MXL_RV32) { + if (env->xl !=3D MXL_RV32 || env->debugger) { if ((val & SSTATUS64_UXL) !=3D 0) { mask |=3D SSTATUS64_UXL; } --=20 2.25.1