From nobody Sun May 5 16:41:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164246888756710.040162012010228; Mon, 17 Jan 2022 17:21:27 -0800 (PST) Received: from localhost ([::1]:41454 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n9dBd-0002AO-Kn for importer@patchew.org; Mon, 17 Jan 2022 20:21:25 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47460) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n9d7z-00086S-Is; Mon, 17 Jan 2022 20:17:39 -0500 Received: from smtp21.cstnet.cn ([159.226.251.21]:53698 helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n9d7w-0003qE-Gv; Mon, 17 Jan 2022 20:17:39 -0500 Received: from localhost.localdomain (unknown [180.156.147.178]) by APP-01 (Coremail) with SMTP id qwCowAD3_lYmFeZhTWGLBg--.14045S3; Tue, 18 Jan 2022 09:17:29 +0800 (CST) From: Weiwei Li To: anup@brainfault.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64 Date: Tue, 18 Jan 2022 09:17:07 +0800 Message-Id: <20220118011711.7243-2-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220118011711.7243-1-liweiwei@iscas.ac.cn> References: <20220118011711.7243-1-liweiwei@iscas.ac.cn> X-CM-TRANSID: qwCowAD3_lYmFeZhTWGLBg--.14045S3 X-Coremail-Antispam: 1UD129KBjvJXoW7Aw43Jr4DKFyUury8Jr43Wrg_yoW8Ar17pr WfW34Iy3ykJr93CayrKF4Yyr45JwsY9w1ruaykur1UCa1rJrWru3ZrKa10g3ZxXF1vvF1S 93Wq9r45ZF4DXFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9qb7Iv0xC_Cr1lb4IE77IF4wAFF20E14v26ryj6rWUM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI 8067AKxVWUGwA2048vs2IY020Ec7CjxVAFwI0_JFI_Gr1l8cAvFVAK0II2c7xJM28CjxkF 64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcV CY1x0267AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280 aVCY1x0267AKxVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64 kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm 72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2Ij64vIr41l4I8I3I 0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWU GVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI 0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0 rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r 4UJbIYCTnIWIevJa73UjIFyTuYvjxU7NeODUUUU X-Originating-IP: [180.156.147.178] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.226.251.21; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Guo Ren Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642468890002100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Guo Ren Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit Virtual-Memory System 2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.= pdf Signed-off-by: Guo Ren Tested-by: Bin Meng Reviewed-by: Liu Zhiwei Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 7 +++++++ target/riscv/cpu_helper.c | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 5a6d49aa64..282cd8eecd 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -490,6 +490,13 @@ typedef enum { /* Page table PPN shift amount */ #define PTE_PPN_SHIFT 10 =20 +/* Page table PPN mask */ +#if defined(TARGET_RISCV32) +#define PTE_PPN_MASK 0xffffffffUL +#elif defined(TARGET_RISCV64) +#define PTE_PPN_MASK 0x3fffffffffffffULL +#endif + /* Leaf page shift amount */ #define PGSHIFT 12 =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 434a83e66a..26608ddf1c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -619,7 +619,7 @@ restart: return TRANSLATE_FAIL; } =20 - hwaddr ppn =3D pte >> PTE_PPN_SHIFT; + hwaddr ppn =3D (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT; =20 if (!(pte & PTE_V)) { /* Invalid PTE */ --=20 2.17.1 From nobody Sun May 5 16:41:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642468856793939.2662055215482; Mon, 17 Jan 2022 17:20:56 -0800 (PST) Received: from localhost ([::1]:41212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n9dB9-00020d-A7 for importer@patchew.org; Mon, 17 Jan 2022 20:20:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47504) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n9d80-00087m-UK; Mon, 17 Jan 2022 20:17:40 -0500 Received: from smtp21.cstnet.cn ([159.226.251.21]:53700 helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n9d7w-0003qF-Hk; Mon, 17 Jan 2022 20:17:40 -0500 Received: from localhost.localdomain (unknown [180.156.147.178]) by APP-01 (Coremail) with SMTP id qwCowAD3_lYmFeZhTWGLBg--.14045S4; Tue, 18 Jan 2022 09:17:30 +0800 (CST) From: Weiwei Li To: anup@brainfault.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v5 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Date: Tue, 18 Jan 2022 09:17:08 +0800 Message-Id: <20220118011711.7243-3-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220118011711.7243-1-liweiwei@iscas.ac.cn> References: <20220118011711.7243-1-liweiwei@iscas.ac.cn> X-CM-TRANSID: qwCowAD3_lYmFeZhTWGLBg--.14045S4 X-Coremail-Antispam: 1UD129KBjvdXoW7GFyUXr4ktr13Ar13Cw4kZwb_yoW3GFb_CF W0gFn7uw1ku3WvkFsYyryqqr1Ig3s5GF10ka17GF48Gryjgry3Cw1ktws5CryUur15ArnF y3ZrJry3Cr15CjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUbTxFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k26cxKx2IYs7xG 6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUXwA2048vs2IY02 0Ec7CjxVAFwI0_Gr0_Xr1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr1l84 ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_Cr1U M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxAIw28IcxkI7VAKI48JMx C20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAF wI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20x vE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v2 0xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxV W8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUjJKsUUUUUU== X-Originating-IP: [180.156.147.178] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.226.251.21; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wangjunqiang@iscas.ac.cn, Weiwei Li , lazyparser@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642468858982100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel --- target/riscv/cpu_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 26608ddf1c..1820188f41 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -626,6 +626,9 @@ restart: return TRANSLATE_FAIL; } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { /* Inner PTE, continue walking */ + if (pte & (PTE_D | PTE_A | PTE_U)) { + return TRANSLATE_FAIL; + } base =3D ppn << PGSHIFT; } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D PTE_W) { /* Reserved leaf PTE flags: PTE_W */ --=20 2.17.1 From nobody Sun May 5 16:41:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642469180282245.18192363612252; Mon, 17 Jan 2022 17:26:20 -0800 (PST) Received: from localhost ([::1]:47786 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n9dGN-0006ma-Bg for importer@patchew.org; Mon, 17 Jan 2022 20:26:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47506) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n9d80-00087n-Uq; Mon, 17 Jan 2022 20:17:40 -0500 Received: from smtp21.cstnet.cn ([159.226.251.21]:53706 helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n9d7w-0003qG-HX; Mon, 17 Jan 2022 20:17:40 -0500 Received: from localhost.localdomain (unknown [180.156.147.178]) by APP-01 (Coremail) with SMTP id qwCowAD3_lYmFeZhTWGLBg--.14045S5; Tue, 18 Jan 2022 09:17:31 +0800 (CST) From: Weiwei Li To: anup@brainfault.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v5 3/5] target/riscv: add support for svnapot extension Date: Tue, 18 Jan 2022 09:17:09 +0800 Message-Id: <20220118011711.7243-4-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220118011711.7243-1-liweiwei@iscas.ac.cn> References: <20220118011711.7243-1-liweiwei@iscas.ac.cn> X-CM-TRANSID: qwCowAD3_lYmFeZhTWGLBg--.14045S5 X-Coremail-Antispam: 1UD129KBjvJXoWxCr4kXw4Dtr1kWrykZF4ruFg_yoW5Zr18pr Z8G39FkrZ7JFWaya1fKF4Dtw1rGws09ayF9ws7Ars7Jw4rJrW5W3Wqkws8uF15XF48Zr1Y 9an8uF1Yyr4UZaDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9C14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr1j6F4U JwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCF04k20xvY0x0EwIxGrw CFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE 14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2 IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxK x2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI 0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUCXdbUUUUU= X-Originating-IP: [180.156.147.178] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.226.251.21; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wangjunqiang@iscas.ac.cn, Weiwei Li , lazyparser@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642469181395100003 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" - add PTE_N bit - add PTE_N bit check for inner PTE - update address translation to support 64KiB continuous region (napot_bits= =3D 4) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Cc: Anup Patel Reviewed-by: Anup Patel --- target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 18 +++++++++++++++--- 4 files changed, 19 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9bc25d3055..ff6c86c85b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -668,6 +668,8 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 + DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), + DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4d63086765..d3d17cde82 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -327,6 +327,7 @@ struct RISCVCPU { bool ext_counters; bool ext_ifencei; bool ext_icsr; + bool ext_svnapot; bool ext_zfh; bool ext_zfhmin; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 282cd8eecd..5501e9698b 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -486,6 +486,7 @@ typedef enum { #define PTE_A 0x040 /* Accessed */ #define PTE_D 0x080 /* Dirty */ #define PTE_SOFT 0x300 /* Reserved for Software */ +#define PTE_N 0x8000000000000000 /* NAPOT translation */ =20 /* Page table PPN shift amount */ #define PTE_PPN_SHIFT 10 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1820188f41..c276760c7f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -621,12 +621,13 @@ restart: =20 hwaddr ppn =3D (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT; =20 + RISCVCPU *cpu =3D env_archcpu(env); if (!(pte & PTE_V)) { /* Invalid PTE */ return TRANSLATE_FAIL; } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { /* Inner PTE, continue walking */ - if (pte & (PTE_D | PTE_A | PTE_U)) { + if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_N)) { return TRANSLATE_FAIL; } base =3D ppn << PGSHIFT; @@ -702,8 +703,19 @@ restart: /* for superpage mappings, make a fake leaf PTE for the TLB's benefit. */ target_ulong vpn =3D addr >> PGSHIFT; - *physical =3D ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIF= T) | - (addr & ~TARGET_PAGE_MASK); + + int napot_bits =3D 0; + if (cpu->cfg.ext_svnapot && (pte & (target_ulong)PTE_N)) { + napot_bits =3D ctzl(ppn) + 1; + if ((i !=3D (levels - 1)) || (napot_bits !=3D 4)) { + return TRANSLATE_FAIL; + } + } + + *physical =3D (((ppn & ~(((target_ulong)1 << napot_bits) - 1))= | + (vpn & (((target_ulong)1 << napot_bits) - 1)) | + (vpn & (((target_ulong)1 << ptshift) - 1)) + ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); =20 /* set permissions on the TLB entry */ if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { --=20 2.17.1 From nobody Sun May 5 16:41:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642469319346890.3982160440336; Mon, 17 Jan 2022 17:28:39 -0800 (PST) Received: from localhost ([::1]:51096 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n9dIc-0000pO-Da for importer@patchew.org; Mon, 17 Jan 2022 20:28:38 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47510) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n9d81-0008AV-OG; Mon, 17 Jan 2022 20:17:41 -0500 Received: from smtp21.cstnet.cn ([159.226.251.21]:53786 helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n9d7z-0003qe-5r; Mon, 17 Jan 2022 20:17:41 -0500 Received: from localhost.localdomain (unknown [180.156.147.178]) by APP-01 (Coremail) with SMTP id qwCowAD3_lYmFeZhTWGLBg--.14045S6; Tue, 18 Jan 2022 09:17:31 +0800 (CST) From: Weiwei Li To: anup@brainfault.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v5 4/5] target/riscv: add support for svinval extension Date: Tue, 18 Jan 2022 09:17:10 +0800 Message-Id: <20220118011711.7243-5-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220118011711.7243-1-liweiwei@iscas.ac.cn> References: <20220118011711.7243-1-liweiwei@iscas.ac.cn> X-CM-TRANSID: qwCowAD3_lYmFeZhTWGLBg--.14045S6 X-Coremail-Antispam: 1UD129KBjvJXoW3XrykAF4rJr15Jw48Kr47XFb_yoW7WF4DpF 4UKrW7Gr4kJryfAa4ftr45JFy8Grs3CayUG3saywn5Xa15GrWDJr1DKrW7KrZ8JF4kWr1Y 9F4jyryjyrW8XaDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUB014x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr1j 6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7V C0I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j 6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCF04k20xvY0x0EwI xGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480 Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7 IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UMIIF0xvE42xK 8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I 0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUF18BUUUUU X-Originating-IP: [180.156.147.178] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.226.251.21; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wangjunqiang@iscas.ac.cn, Weiwei Li , lazyparser@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642469320706100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" - sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence= .vvma and hfence.gvma except extension check - do nothing other than extension check for sfence.w.inval and sfence.inval= .ir Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++ target/riscv/translate.c | 1 + 5 files changed, 85 insertions(+) create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ff6c86c85b..45ac98e06b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -668,6 +668,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 + DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), =20 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d3d17cde82..c3d1845ca1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -327,6 +327,7 @@ struct RISCVCPU { bool ext_counters; bool ext_ifencei; bool ext_icsr; + bool ext_svinval; bool ext_svnapot; bool ext_zfh; bool ext_zfhmin; diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 5bbedc254c..1d3ff1efe1 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -809,3 +809,10 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_= rm fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm + +# *** Svinval Standard Extension *** +sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma +sfence_w_inval 0001100 00000 00000 000 00000 1110011 +sfence_inval_ir 0001100 00001 00000 000 00000 1110011 +hinval_vvma 0010011 ..... ..... 000 00000 1110011 @hfence_vvma +hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/ins= n_trans/trans_svinval.c.inc new file mode 100644 index 0000000000..1dde665661 --- /dev/null +++ b/target/riscv/insn_trans/trans_svinval.c.inc @@ -0,0 +1,75 @@ +/* + * RISC-V translation routines for the Svinval Standard Instruction Set. + * + * Copyright (c) 2020-2021 PLCT lab + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#define REQUIRE_SVINVAL(ctx) do { \ + if (!RISCV_CPU(ctx->cs)->cfg.ext_svinval) { \ + return false; \ + } \ +} while (0) + +static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a) +{ + REQUIRE_SVINVAL(ctx); + /* Do the same as sfence.vma currently */ + REQUIRE_EXT(ctx, RVS); +#ifndef CONFIG_USER_ONLY + gen_helper_tlb_flush(cpu_env); + return true; +#endif + return false; +} + +static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a) +{ + REQUIRE_SVINVAL(ctx); + REQUIRE_EXT(ctx, RVS); + /* Do nothing currently */ + return true; +} + +static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *= a) +{ + REQUIRE_SVINVAL(ctx); + REQUIRE_EXT(ctx, RVS); + /* Do nothing currently */ + return true; +} + +static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a) +{ + REQUIRE_SVINVAL(ctx); + /* Do the same as hfence.vvma currently */ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + gen_helper_hyp_tlb_flush(cpu_env); + return true; +#endif + return false; +} + +static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a) +{ + REQUIRE_SVINVAL(ctx); + /* Do the same as hfence.gvma currently */ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + gen_helper_hyp_gvma_tlb_flush(cpu_env); + return true; +#endif + return false; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 615048ec87..4e5a9660a4 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -838,6 +838,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, tar= get_ulong pc) #include "insn_trans/trans_rvb.c.inc" #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_privileged.c.inc" +#include "insn_trans/trans_svinval.c.inc" =20 /* Include the auto-generated decoder for 16 bit insn */ #include "decode-insn16.c.inc" --=20 2.17.1 From nobody Sun May 5 16:41:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1642469177791833.6710523579649; Mon, 17 Jan 2022 17:26:17 -0800 (PST) Received: from localhost ([::1]:47528 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n9dGK-0006Wx-DA for importer@patchew.org; Mon, 17 Jan 2022 20:26:16 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47508) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n9d81-000890-BQ; Mon, 17 Jan 2022 20:17:41 -0500 Received: from smtp21.cstnet.cn ([159.226.251.21]:53784 helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n9d7z-0003qc-4B; Mon, 17 Jan 2022 20:17:41 -0500 Received: from localhost.localdomain (unknown [180.156.147.178]) by APP-01 (Coremail) with SMTP id qwCowAD3_lYmFeZhTWGLBg--.14045S7; Tue, 18 Jan 2022 09:17:33 +0800 (CST) From: Weiwei Li To: anup@brainfault.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v5 5/5] target/riscv: add support for svpbmt extension Date: Tue, 18 Jan 2022 09:17:11 +0800 Message-Id: <20220118011711.7243-6-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220118011711.7243-1-liweiwei@iscas.ac.cn> References: <20220118011711.7243-1-liweiwei@iscas.ac.cn> X-CM-TRANSID: qwCowAD3_lYmFeZhTWGLBg--.14045S7 X-Coremail-Antispam: 1UD129KBjvJXoWxCFWkZrWrGF1DCr4DWw45Wrg_yoW5Gw18pr s3G3yIk395JFW3Aa1xKF1UJw1UCws09F12kan7Zrs7Jr4rJ3y3JF1DKw47CF43XF18Zr1a 93Z0kF1Yvr4UXaDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPa14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr1j 6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7V C0I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j 6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x0262 8vn2kIc2xKxwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02 F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GF ylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7Cj xVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxV WUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfU F18BUUUUU X-Originating-IP: [180.156.147.178] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.226.251.21; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wangjunqiang@iscas.ac.cn, Weiwei Li , lazyparser@gmail.com, Heiko Stuebner Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1642469179859100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on Q= EMU, since QEMU is sequentially consistent and doesn't model PMAs currently - add PTE_PBMT bit check for inner PTE Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Cc: Heiko Stuebner Cc: Anup Patel Reviewed-by: Anup Patel --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 2 ++ target/riscv/cpu_helper.c | 4 +++- 4 files changed, 7 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 45ac98e06b..4f82bd00a3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] =3D { =20 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), =20 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c3d1845ca1..53f314c752 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -329,6 +329,7 @@ struct RISCVCPU { bool ext_icsr; bool ext_svinval; bool ext_svnapot; + bool ext_svpbmt; bool ext_zfh; bool ext_zfhmin; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 5501e9698b..24b7eb2b1f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -486,7 +486,9 @@ typedef enum { #define PTE_A 0x040 /* Accessed */ #define PTE_D 0x080 /* Dirty */ #define PTE_SOFT 0x300 /* Reserved for Software */ +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types = */ #define PTE_N 0x8000000000000000 /* NAPOT translation */ +#define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */ =20 /* Page table PPN shift amount */ #define PTE_PPN_SHIFT 10 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c276760c7f..9fffaccffb 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -625,9 +625,11 @@ restart: if (!(pte & PTE_V)) { /* Invalid PTE */ return TRANSLATE_FAIL; + } else if (!cpu->cfg.ext_svpbmt && (pte & (target_ulong)PTE_PBMT))= { + return TRANSLATE_FAIL; } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { /* Inner PTE, continue walking */ - if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_N)) { + if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_ATTR)) { return TRANSLATE_FAIL; } base =3D ppn << PGSHIFT; --=20 2.17.1