[PATCH v4 0/4] support subsets of virtual memory extension

Weiwei Li posted 4 patches 2 years, 2 months ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/20220116025925.29973-1-liweiwei@iscas.ac.cn
Maintainers: Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Bin Meng <bin.meng@windriver.com>
There is a newer version of this series
target/riscv/cpu.c                          |  4 ++
target/riscv/cpu.h                          |  3 +
target/riscv/cpu_bits.h                     |  4 ++
target/riscv/cpu_helper.c                   | 27 ++++++--
target/riscv/insn32.decode                  |  7 ++
target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
target/riscv/translate.c                    |  1 +
7 files changed, 117 insertions(+), 4 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
[PATCH v4 0/4] support subsets of virtual memory extension
Posted by Weiwei Li 2 years, 2 months ago
This patchset implements virtual memory related RISC-V extensions: Svnapot version 1.0, Svinval vesion 1.0, Svpbmt version 1.0. 

Specification:
https://github.com/riscv/virtual-memory/tree/main/specs

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v4

To test this implementation, specify cpu argument with 'svinval=true,svnapot=true,svpbmt=true'.

This implementation can pass the riscv-tests for rv64ssvnapot.

v4:
* fix encodings for hinval_vvma and hinval_gvma
* partition inner PTE check into several steps added in first, second and fourth commits
* improve commit messages to describe changes

v3:
* drop "x-" in exposed properties

v2:
* add extension check for svnapot and svpbmt

Weiwei Li (4):
  target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
  target/riscv: add support for svnapot extension
  target/riscv: add support for svinval extension
  target/riscv: add support for svpbmt extension

 target/riscv/cpu.c                          |  4 ++
 target/riscv/cpu.h                          |  3 +
 target/riscv/cpu_bits.h                     |  4 ++
 target/riscv/cpu_helper.c                   | 27 ++++++--
 target/riscv/insn32.decode                  |  7 ++
 target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
 target/riscv/translate.c                    |  1 +
 7 files changed, 117 insertions(+), 4 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc

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2.17.1