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[79.176.122.157]) by smtp.gmail.com with ESMTPSA id l12sm1244108wrz.15.2022.01.13.16.40.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jan 2022 16:40:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=CddZa7T6MsJ8xpDZ5jTKr5EVCyIkXQhXTW/YgwH8P14=; b=mB1NEH8HN9BSCslLIamGzNIpzYU2Bq8P+5CDZHGp9bBGjQgB8QUm6qfWKQrA2pbo1X FzEsSy5oZx5onbQp6jtd7tSNUc7tvQFzeDEw60Tv9MX9N4WbBSix+V+crsrfKU5uhJg6 5ED1Wx+mah/85gZnd5JaPTMwpp2FwtYbHI1BLUeVZNdcsJZXGSJ8yELEnlD8GVR+KHT5 jWq2KM8ifGq9xObtkEYQ6uyqZiOljnS9QGKVIsw9usgq+rS45x4pgS12NbpA9AOpp3ux T/cGuIxX7oSH5MhIzp2KRybNiNik3p5B6L3WO0yi4uC4t4HoFi/eI5SF88yq8ZKZUSEm cXCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=CddZa7T6MsJ8xpDZ5jTKr5EVCyIkXQhXTW/YgwH8P14=; b=Mc55bb6SJfPubIJop8S6zshG5KLgA7RXhiXZCcGQEosPB9iypz73iazSylRqNGSAxV u9G3qgijkQAffNYrgetCpyQrxF5W7m2+uR4THBlhCn5j0yDRdXMWGRDbR/J9zh2b0CcQ yCdYLLR22BQDUSzb2ktTYYJ2WutjQmqmnX1XcUMWty2dYxn5ajVv7utyT6RlmSLdFh/t B2/2F9bs1WCt01+E1V3c1VtmUOhqbNGWfd1Hwwn+mnhE/Nbwh2d3zGVwWMgediuMuvVD p9QXRvoIcl53vTHgkA75CZBSC9K2sg0AUo+6gOnAT08Kqdl9h5v5cQft1o8obC9x/IJL FLvQ== X-Gm-Message-State: AOAM532AJ3es9bhx/4VuSm6R862/ePnHlFH0JjOiqjZDdhVLtsySnN0r IlAbxN9xpxPHVGCoB3Biy4qend6QtrE= X-Google-Smtp-Source: ABdhPJya7EoI0fPthEvzH7KCr/qr1MQu6kpcbBtXm4lQG043Ozx8gy9uYqsvv+T2pzpQ1j1Y430KHg== X-Received: by 2002:a5d:4352:: with SMTP id u18mr6121609wrr.266.1642120850342; Thu, 13 Jan 2022 16:40:50 -0800 (PST) From: Idan Horowitz To: qemu-arm@nongnu.org Subject: [PATCH] target/arm: Allow only specific instructions based on the SCTLR_EL1.UCI bit Date: Fri, 14 Jan 2022 02:40:33 +0200 Message-Id: <20220114004033.295199-1-idan.horowitz@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=idan.horowitz@gmail.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Idan Horowitz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1642121475700100009 Content-Type: text/plain; charset="utf-8" The SCTLR_EL1.UCI bit only affects a subset of cache maintenance instructions as specified by the specification. Any other cache maintenance instructions must still be trapped from EL0. Signed-off-by: Idan Horowitz --- target/arm/helper.c | 68 ++++++++++++++++++++++++++++++++++----------- 1 file changed, 52 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index cfca0f5ba6..ac75a268aa 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4217,7 +4217,7 @@ static const ARMCPRegInfo ssbs_reginfo =3D { .readfn =3D aa64_ssbs_read, .writefn =3D aa64_ssbs_write }; =20 -static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, +static CPAccessResult aa64_cacheop_poc_uci_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { @@ -4239,7 +4239,7 @@ static CPAccessResult aa64_cacheop_poc_access(CPUARMS= tate *env, return CP_ACCESS_OK; } =20 -static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, +static CPAccessResult aa64_cacheop_pou_uci_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { @@ -4261,6 +4261,42 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARM= State *env, return CP_ACCESS_OK; } =20 +static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* Cache invalidate/clean to Point of Coherency or Persistence... */ + switch (arm_current_el(env)) { + case 0: + return CP_ACCESS_TRAP; + case 1: + /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */ + if (arm_hcr_el2_eff(env) & HCR_TPCP) { + return CP_ACCESS_TRAP_EL2; + } + break; + } + return CP_ACCESS_OK; +} + +static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* Cache invalidate/clean to Point of Unification... */ + switch (arm_current_el(env)) { + case 0: + return CP_ACCESS_TRAP; + case 1: + /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */ + if (arm_hcr_el2_eff(env) & HCR_TPU) { + return CP_ACCESS_TRAP_EL2; + } + break; + } + return CP_ACCESS_OK; +} + /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions * Page D4-1736 (DDI0487A.b) */ @@ -4846,7 +4882,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "IC_IVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 5, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_pou_access }, + .accessfn =3D aa64_cacheop_pou_uci_access }, { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D aa64_cacheop_poc_access, @@ -4857,18 +4893,18 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_poc_access }, + .accessfn =3D aa64_cacheop_poc_uci_access }, { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_pou_access }, + .accessfn =3D aa64_cacheop_pou_uci_access }, { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_poc_access }, + .accessfn =3D aa64_cacheop_poc_uci_access }, { .name =3D "DC_CISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, @@ -7102,7 +7138,7 @@ static const ARMCPRegInfo dcpop_reg[] =3D { { .name =3D "DC_CVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, - .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, + .accessfn =3D aa64_cacheop_poc_uci_access, .writefn =3D dccvap_write= fn }, REGINFO_SENTINEL }; =20 @@ -7110,7 +7146,7 @@ static const ARMCPRegInfo dcpodp_reg[] =3D { { .name =3D "DC_CVADP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, - .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, + .accessfn =3D aa64_cacheop_poc_uci_access, .writefn =3D dccvap_write= fn }, REGINFO_SENTINEL }; #endif /*CONFIG_USER_ONLY*/ @@ -7227,35 +7263,35 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[]= =3D { { .name =3D "DC_CGVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL0_W, - .accessfn =3D aa64_cacheop_poc_access }, + .accessfn =3D aa64_cacheop_poc_uci_access }, { .name =3D "DC_CGDVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, - .accessfn =3D aa64_cacheop_poc_access }, + .accessfn =3D aa64_cacheop_poc_uci_access }, { .name =3D "DC_CGVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL0_W, - .accessfn =3D aa64_cacheop_poc_access }, + .accessfn =3D aa64_cacheop_poc_uci_access }, { .name =3D "DC_CGDVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, - .accessfn =3D aa64_cacheop_poc_access }, + .accessfn =3D aa64_cacheop_poc_uci_access }, { .name =3D "DC_CGVADP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL0_W, - .accessfn =3D aa64_cacheop_poc_access }, + .accessfn =3D aa64_cacheop_poc_uci_access }, { .name =3D "DC_CGDVADP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, - .accessfn =3D aa64_cacheop_poc_access }, + .accessfn =3D aa64_cacheop_poc_uci_access }, { .name =3D "DC_CIGVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 3, .type =3D ARM_CP_NOP, .access =3D PL0_W, - .accessfn =3D aa64_cacheop_poc_access }, + .accessfn =3D aa64_cacheop_poc_uci_access }, { .name =3D "DC_CIGDVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, - .accessfn =3D aa64_cacheop_poc_access }, + .accessfn =3D aa64_cacheop_poc_uci_access }, { .name =3D "DC_GVA", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 3, .access =3D PL0_W, .type =3D ARM_CP_DC_GVA, --=20 2.34.1