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b=LS0dsOwn3y41DWINocpQt+dXvpr9G+ji0B61+0+7xeg64lx+/MwiVdFkc0fHt0/24F6p f1aKSsQVOWtbcQdV4xGX5XwOdYxgxyY+Ywcz5ki3mubNaZi5Ccq8IPGArrCV4RhgtXUN hy7o4T9fdYzLwAERMwLWcSLBdu6xUSLwjIH23gMEh5L8i4uEi9MBncUn99jIzg/tRxG9 LJz4QrhYQlg23K36uhGRs/fi7rCUTqr0Oley7GCPSItOCKKt3NDylUipvefbJt6Pljft +bHsS22rigQyo+os4bMR5ZZCpkfOAhUCoL32XLSLUfxAkEBYjBrz7v0SPoxPblbX1v/H Ng== From: Ilya Leoshkevich To: Richard Henderson , David Hildenbrand , Cornelia Huck , Thomas Huth Subject: [PATCH v3 5/5] tests/tcg/s390x: Test shift instructions Date: Wed, 12 Jan 2022 14:17:51 +0100 Message-Id: <20220112131751.226011-6-iii@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220112131751.226011-1-iii@linux.ibm.com> References: <20220112131751.226011-1-iii@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: SZk--65v0YNh9H1umx86vHG5L3bALPEs X-Proofpoint-ORIG-GUID: cSnar6Q1gO-LsSxssglJ3m8CREHb_O6U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-12_04,2022-01-11_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 phishscore=0 impostorscore=0 mlxlogscore=999 mlxscore=0 spamscore=0 priorityscore=1501 adultscore=0 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201120086 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=iii@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christian Borntraeger , qemu-s390x@nongnu.org, qemu-devel@nongnu.org, Ilya Leoshkevich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641997275327100001 Content-Type: text/plain; charset="utf-8" Add a test for each shift instruction in order to to prevent regressions. Signed-off-by: Ilya Leoshkevich --- tests/tcg/s390x/Makefile.target | 1 + tests/tcg/s390x/shift.c | 270 ++++++++++++++++++++++++++++++++ 2 files changed, 271 insertions(+) create mode 100644 tests/tcg/s390x/shift.c diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.tar= get index cc64dd32d2..1a7238b4eb 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -9,6 +9,7 @@ TESTS+=3Dexrl-trtr TESTS+=3Dpack TESTS+=3Dmvo TESTS+=3Dmvc +TESTS+=3Dshift TESTS+=3Dtrap TESTS+=3Dsignals-s390x =20 diff --git a/tests/tcg/s390x/shift.c b/tests/tcg/s390x/shift.c new file mode 100644 index 0000000000..29594fec5c --- /dev/null +++ b/tests/tcg/s390x/shift.c @@ -0,0 +1,270 @@ +#include +#include +#include + +#define DEFINE_SHIFT_SINGLE_COMMON(_name, _insn_str) \ + static uint64_t _name(uint64_t op1, uint64_t op2, uint64_t *cc) \ + { \ + asm(" sll %[cc],28\n" \ + " spm %[cc]\n" \ + " " _insn_str "\n" \ + " ipm %[cc]\n" \ + " srl %[cc],28" \ + : [op1] "+&r" (op1), \ + [cc] "+&r" (*cc) \ + : [op2] "r" (op2) \ + : "cc"); \ + return op1; \ + } +#define DEFINE_SHIFT_SINGLE_2(_insn, _offset) \ + DEFINE_SHIFT_SINGLE_COMMON(_insn ## _ ## _offset, \ + #_insn " %[op1]," #_offset "(%[op2])") +#define DEFINE_SHIFT_SINGLE_3(_insn, _offset) \ + DEFINE_SHIFT_SINGLE_COMMON(_insn ## _ ## _offset, \ + #_insn " %[op1],%[op1]," #_offset "(%[op2])= ") +#define DEFINE_SHIFT_DOUBLE(_insn, _offset) \ + static uint64_t _insn ## _ ## _offset(uint64_t op1, uint64_t op2, \ + uint64_t *cc) \ + { \ + uint32_t op1h =3D op1 >> 32; \ + uint32_t op1l =3D op1 & 0xffffffff; \ + register uint32_t r2 asm("2") =3D op1h; \ + register uint32_t r3 asm("3") =3D op1l; \ + \ + asm(" sll %[cc],28\n" \ + " spm %[cc]\n" \ + " " #_insn " %[r2]," #_offset "(%[op2])\n" \ + " ipm %[cc]\n" \ + " srl %[cc],28" \ + : [r2] "+&r" (r2), \ + [r3] "+&r" (r3), \ + [cc] "+&r" (*cc) \ + : [op2] "r" (op2) \ + : "cc"); \ + op1h =3D r2; \ + op1l =3D r3; \ + return (((uint64_t)op1h) << 32) | op1l; \ + } + +DEFINE_SHIFT_SINGLE_3(rll, 0x4cf3b); +DEFINE_SHIFT_SINGLE_3(rllg, 0x697c9); +DEFINE_SHIFT_SINGLE_2(sla, 0x4b0); +DEFINE_SHIFT_SINGLE_2(sla, 0xd54); +DEFINE_SHIFT_SINGLE_3(slak, 0x2832c); +DEFINE_SHIFT_SINGLE_3(slag, 0x66cc4); +DEFINE_SHIFT_SINGLE_3(slag, 0xd54); +DEFINE_SHIFT_SINGLE_2(sll, 0xd04); +DEFINE_SHIFT_SINGLE_3(sllk, 0x2699f); +DEFINE_SHIFT_SINGLE_3(sllg, 0x59df9); +DEFINE_SHIFT_SINGLE_2(sra, 0x67e); +DEFINE_SHIFT_SINGLE_3(srak, 0x60943); +DEFINE_SHIFT_SINGLE_3(srag, 0x6b048); +DEFINE_SHIFT_SINGLE_2(srl, 0x035); +DEFINE_SHIFT_SINGLE_3(srlk, 0x43dfc); +DEFINE_SHIFT_SINGLE_3(srlg, 0x27227); +DEFINE_SHIFT_DOUBLE(slda, 0x38b); +DEFINE_SHIFT_DOUBLE(sldl, 0x031); +DEFINE_SHIFT_DOUBLE(srda, 0x36f); +DEFINE_SHIFT_DOUBLE(srdl, 0x99a); + +struct shift_test { + const char *name; + uint64_t (*insn)(uint64_t, uint64_t, uint64_t *); + uint64_t op1; + uint64_t op2; + uint64_t exp_result; + uint64_t exp_cc; +}; + +static const struct shift_test tests[] =3D { + { + .name =3D "rll", + .insn =3D rll_0x4cf3b, + .op1 =3D 0xecbd589a45c248f5ull, + .op2 =3D 0x62e5508ccb4c99fdull, + .exp_result =3D 0xecbd589af545c248ull, + .exp_cc =3D 0, + }, + { + .name =3D "rllg", + .insn =3D rllg_0x697c9, + .op1 =3D 0xaa2d54c1b729f7f4ull, + .op2 =3D 0x5ffcf7465f5cd71full, + .exp_result =3D 0x29f7f4aa2d54c1b7ull, + .exp_cc =3D 0, + }, + { + .name =3D "sla-1", + .insn =3D sla_0x4b0, + .op1 =3D 0x8bf21fb67cca0e96ull, + .op2 =3D 0x3ddf2f53347d3030ull, + .exp_result =3D 0x8bf21fb600000000ull, + .exp_cc =3D 3, + }, + { + .name =3D "sla-2", + .insn =3D sla_0xd54, + .op1 =3D 0xe4faaed5def0e926ull, + .op2 =3D 0x18d586fab239cbeeull, + .exp_result =3D 0xe4faaed5fbc3a498ull, + .exp_cc =3D 3, + }, + { + .name =3D "slak", + .insn =3D slak_0x2832c, + .op1 =3D 0x7300bf78707f09f9ull, + .op2 =3D 0x4d193b85bb5cb39bull, + .exp_result =3D 0x7300bf783f84fc80ull, + .exp_cc =3D 3, + }, + { + .name =3D "slag-1", + .insn =3D slag_0x66cc4, + .op1 =3D 0xe805966de1a77762ull, + .op2 =3D 0x0e92953f6aa91c6bull, + .exp_result =3D 0xbbb1000000000000ull, + .exp_cc =3D 3, + }, + { + .name =3D "slag-2", + .insn =3D slag_0xd54, + .op1 =3D 0xdef0e92600000000ull, + .op2 =3D 0x18d586fab239cbeeull, + .exp_result =3D 0xfbc3a49800000000ull, + .exp_cc =3D 3, + }, + { + .name =3D "sll", + .insn =3D sll_0xd04, + .op1 =3D 0xb90281a3105939dfull, + .op2 =3D 0xb5e4df7e082e4c5eull, + .exp_result =3D 0xb90281a300000000ull, + .exp_cc =3D 0, + }, + { + .name =3D "sllk", + .insn =3D sllk_0x2699f, + .op1 =3D 0x777c6cf116f99557ull, + .op2 =3D 0xe0556cf112e5a458ull, + .exp_result =3D 0x777c6cf100000000ull, + .exp_cc =3D 0, + }, + { + .name =3D "sllg", + .insn =3D sllg_0x59df9, + .op1 =3D 0xcdf86cbfbc0f3557ull, + .op2 =3D 0x325a45acf99c6d3dull, + .exp_result =3D 0x55c0000000000000ull, + .exp_cc =3D 0, + }, + { + .name =3D "sra", + .insn =3D sra_0x67e, + .op1 =3D 0xb878f048d5354183ull, + .op2 =3D 0x9e27d13195931f79ull, + .exp_result =3D 0xb878f048ffffffffull, + .exp_cc =3D 1, + }, + { + .name =3D "srak", + .insn =3D srak_0x60943, + .op1 =3D 0xb6ceb5a429cedb35ull, + .op2 =3D 0x352354900ae34d7aull, + .exp_result =3D 0xb6ceb5a400000000ull, + .exp_cc =3D 0, + }, + { + .name =3D "srag", + .insn =3D srag_0x6b048, + .op1 =3D 0xd54dd4468676c63bull, + .op2 =3D 0x84d026db7b4dca28ull, + .exp_result =3D 0xffffffffffffd54dull, + .exp_cc =3D 1, + }, + { + .name =3D "srl", + .insn =3D srl_0x035, + .op1 =3D 0x09be503ef826815full, + .op2 =3D 0xbba8d1a0e542d5c1ull, + .exp_result =3D 0x9be503e00000000ull, + .exp_cc =3D 0, + }, + { + .name =3D "srlk", + .insn =3D srlk_0x43dfc, + .op1 =3D 0x540d6c8de71aee2aull, + .op2 =3D 0x0000000000000000ull, + .exp_result =3D 0x540d6c8d00000000ull, + .exp_cc =3D 0, + }, + { + .name =3D "srlg", + .insn =3D srlg_0x27227, + .op1 =3D 0x26f7123c1c447a34ull, + .op2 =3D 0x0000000000000000ull, + .exp_result =3D 0x00000000004dee24ull, + .exp_cc =3D 0, + }, + { + .name =3D "slda", + .insn =3D slda_0x38b, + .op1 =3D 0x7988f722dd5bbe7cull, + .op2 =3D 0x9aed3f95b4d78cc2ull, + .exp_result =3D 0x1ee45bab77cf8000ull, + .exp_cc =3D 3, + }, + { + .name =3D "sldl", + .insn =3D sldl_0x031, + .op1 =3D 0xaae2918dce2b049aull, + .op2 =3D 0x0000000000000000ull, + .exp_result =3D 0x0934000000000000ull, + .exp_cc =3D 0, + }, + { + .name =3D "srda", + .insn =3D srda_0x36f, + .op1 =3D 0x0cd4ed9228a50978ull, + .op2 =3D 0x72b046f0848b8cc9ull, + .exp_result =3D 0x000000000000000cull, + .exp_cc =3D 2, + }, + { + .name =3D "srdl", + .insn =3D srdl_0x99a, + .op1 =3D 0x1018611c41689a1dull, + .op2 =3D 0x2907e150c50ba319ull, + .exp_result =3D 0x0000000000000203ull, + .exp_cc =3D 0, + }, +}; + +int main(void) +{ + int ret =3D 0; + size_t i; + + for (i =3D 0; i < sizeof(tests) / sizeof(tests[0]); i++) { + uint64_t result; + uint64_t cc =3D 0; + + result =3D tests[i].insn(tests[i].op1, tests[i].op2, &cc); + if (result !=3D tests[i].exp_result) { + fprintf(stderr, + "bad %s result:\n" + "actual =3D 0x%" PRIx64 "\n" + "expected =3D 0x%" PRIx64 "\n", + tests[i].name, result, tests[i].exp_result); + ret =3D 1; + } + if (cc !=3D tests[i].exp_cc) { + fprintf(stderr, + "bad %s cc:\n" + "actual =3D %" PRIu64 "\n" + "expected =3D %" PRIu64 "\n", + tests[i].name, cc, tests[i].exp_cc); + ret =3D 1; + } + } + return ret; +} --=20 2.31.1