The following changes since commit 7bb1272f40bdbdebcaec1737c412dcb52e414842: Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/python-pull-request' into staging (2022-01-11 14:20:42 +0000) are available in the Git repository at: https://github.com/legoater/qemu/ tags/pull-ppc-20220112 for you to fetch changes up to f83460bb203a49dd1693bf8b664d2a935a5be621: ppc/pnv: use stack->pci_regs[] in pnv_pec_stk_pci_xscom_write() (2022-01-12 11:28:27 +0100) ---------------------------------------------------------------- ppc 7.0 queue: * New SLOF for PPC970 and POWER5+ (Alexey) * Fixes for POWER5+ pseries (Cedric) * Updates of documentation (Leonardo and Thomas) * First step of exception model cleanup (Fabiano) * User created PHB3/PHB4 devices (Daniel and Cedric) ---------------------------------------------------------------- Alexey Kardashevskiy (1): pseries: Update SLOF firmware image Cédric Le Goater (9): Merge tag 'qemu-slof-20220110' of github.com:aik/qemu into ppc-7.0 target/ppc: Add popcntb instruction to POWER5+ processors spapr: Fix support of POWER5+ processors target/ppc: Add extra float instructions to POWER5P processors ppc/pnv: Attach PHB3 root port device when defaults are enabled ppc/pnv: Introduce support for user created PHB3 devices ppc/pnv: Reparent user created PHB3 devices to the PnvChip ppc/pnv: Complete user created PHB3 devices ppc/pnv: Move num_phbs under Pnv8Chip Daniel Henrique Barboza (14): pnv_phb3.c: add unique chassis and slot for pnv_phb3_root_port pnv_phb4.c: add unique chassis and slot for pnv_phb4_root_port pnv_phb4.c: make pnv-phb4-root-port user creatable pnv_phb4.c: check if root port exists in rc_config functions pnv_phb3.h: change TYPE_PNV_PHB3_ROOT_BUS name pnv_phb4.c: change TYPE_PNV_PHB4_ROOT_BUS name pnv_phb4_pec.c: move pnv_pec_phb_offset() to pnv_phb4.c pnv_phb4_pec: use pnv_phb4_pec_get_phb_id() in pnv_pec_dt_xscom() ppc/pnv: set phb4 properties in stk_realize() ppc/pnv: move PHB4 XSCOM init to phb4_realize() ppc/pnv: turn 'phb' into a pointer in struct PnvPhb4PecStack ppc/pnv: Introduce user creatable pnv-phb4 devices ppc/pnv: turn pnv_phb4_update_regions() into static ppc/pnv: use stack->pci_regs[] in pnv_pec_stk_pci_xscom_write() Fabiano Rosas (8): target/ppc: powerpc_excp: Extract software TLB logging into a function target/ppc: powerpc_excp: Keep 60x/7x5 soft MMU logs active target/ppc: powerpc_excp: Group unimplemented exceptions target/ppc: Add HV support to ppc_interrupts_little_endian target/ppc: Add MSR_ILE support to ppc_interrupts_little_endian target/ppc: Use ppc_interrupts_little_endian in powerpc_excp target/ppc: Introduce a wrapper for powerpc_excp target/ppc: Set the correct endianness for powernv memory dumps Leonardo Garcia (1): docs: Clarifications and formatting changes in ppc docs. Thomas Huth (2): docs/system/ppc: Merge the PEF information into the pseries page MAINTAINERS: Improve the PowerPC machines section docs/papr-pef.txt | 30 --- docs/specs/ppc-spapr-hcalls.rst | 21 +- docs/system/ppc/pseries.rst | 75 +++++-- include/hw/pci-host/pnv_phb3.h | 4 +- include/hw/pci-host/pnv_phb4.h | 14 +- include/hw/ppc/pnv.h | 8 +- target/ppc/cpu.h | 25 ++- hw/pci-host/pnv_phb3.c | 57 ++++- hw/pci-host/pnv_phb4.c | 486 ++++++++++++++++++++++++++++++++++++---- hw/pci-host/pnv_phb4_pec.c | 347 ++-------------------------- hw/ppc/pnv.c | 55 ++++- hw/ppc/spapr.c | 10 +- target/ppc/arch_dump.c | 2 +- target/ppc/cpu_init.c | 2 + target/ppc/excp_helper.c | 185 +++++---------- MAINTAINERS | 12 +- pc-bios/README | 2 +- pc-bios/slof.bin | Bin 991920 -> 992384 bytes roms/SLOF | 2 +- 19 files changed, 737 insertions(+), 600 deletions(-) delete mode 100644 docs/papr-pef.txt From: Alexey Kardashevskiy <aik@ozlabs.ru> The only change is that SLOF is compiled with -mcpu=power5 to make it work on PPC970 too. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> --- pc-bios/README | 2 +- pc-bios/slof.bin | Bin 991920 -> 992384 bytes roms/SLOF | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pc-bios/README b/pc-bios/README index XXXXXXX..XXXXXXX 100644 --- a/pc-bios/README +++ b/pc-bios/README @@ -XXX,XX +XXX,XX @@ - SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware implementation for certain IBM POWER hardware. The sources are at https://github.com/aik/SLOF, and the image currently in qemu is - built from git tag qemu-slof-20211112. + built from git tag qemu-slof-20220110. - VOF (Virtual Open Firmware) is a minimalistic firmware to work with -machine pseries,x-vof=on. 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Add support for POWER5+ processors since they implement ISA v2.03. PPC970 CPUs implement v2.01 and do not support popcntb. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220105095142.3990430-2-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- target/ppc/cpu_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index XXXXXXX..XXXXXXX 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_64B | + PPC_POPCNTB | PPC_SEGMENT_64B | PPC_SLBI; pcc->insns_flags2 = PPC2_FP_CVT_S64; pcc->msr_mask = (1ull << MSR_SF) | -- 2.31.1 POWER5+ (ISA v2.03) processors are supported by the pseries machine but they do not have Altivec instructions. Do not advertise support for it in the DT. To be noted that this test is in contradiction with the assert in cap_vsx_apply(). Signed-off-by: Cédric Le Goater <clg@kaod.org> Tested-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220105095142.3990430-3-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/ppc/spapr.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index XXXXXXX..XXXXXXX 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -XXX,XX +XXX,XX @@ static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, * * Only CPUs for which we create core types in spapr_cpu_core.c * are possible, and all of those have VMX */ - if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { - _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); - } else { - _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); + if (env->insns_flags & PPC_ALTIVEC) { + if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { + _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); + } else { + _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); + } } /* Advertise DFP (Decimal Floating Point) if available -- 2.31.1 ISA v2.03 introduced Floating Round to Integer instructions : frin, friz, frip, and frim. Add them to POWER5+. The PPC_FLOAT_EXT flag also includes the fre (Floating Reciprocal Estimate) instruction which was introduced in ISA v2.0x. The architecture document says its optional and that might be the reason why it has been kept under the PPC_FLOAT_EXT flag. This means 970 CPUs can not use it under QEMU, which doesn't seem to be a problem. Signed-off-by: Cédric Le Goater <clg@kaod.org> --- target/ppc/cpu_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index XXXXXXX..XXXXXXX 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | -- 2.31.1 From: Thomas Huth <thuth@redhat.com> The Protected Execution Facility is only available with the pseries machine, so let's merge the old ASCII text into the new RST file now. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220105103232.405204-1-thuth@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- docs/papr-pef.txt | 30 ------------------------------ docs/system/ppc/pseries.rst | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 30 deletions(-) delete mode 100644 docs/papr-pef.txt diff --git a/docs/papr-pef.txt b/docs/papr-pef.txt deleted file mode 100644 index XXXXXXX..XXXXXXX --- a/docs/papr-pef.txt +++ /dev/null @@ -XXX,XX +XXX,XX @@ -POWER (PAPR) Protected Execution Facility (PEF) -=============================================== - -Protected Execution Facility (PEF), also known as Secure Guest support -is a feature found on IBM POWER9 and POWER10 processors. - -If a suitable firmware including an Ultravisor is installed, it adds -an extra memory protection mode to the CPU. The ultravisor manages a -pool of secure memory which cannot be accessed by the hypervisor. - -When this feature is enabled in QEMU, a guest can use ultracalls to -enter "secure mode". This transfers most of its memory to secure -memory, where it cannot be eavesdropped by a compromised hypervisor. - -Launching ---------- - -To launch a guest which will be permitted to enter PEF secure mode: - -# ${QEMU} \ - -object pef-guest,id=pef0 \ - -machine confidential-guest-support=pef0 \ - ... - -Live Migration ----------------- - -Live migration is not yet implemented for PEF guests. For -consistency, we currently prevent migration if the PEF feature is -enabled, whether or not the guest has actually entered secure mode. diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst index XXXXXXX..XXXXXXX 100644 --- a/docs/system/ppc/pseries.rst +++ b/docs/system/ppc/pseries.rst @@ -XXX,XX +XXX,XX @@ nested. Combinations not shown in the table are not available. .. [3] Introduced on Power10 machines. + +POWER (PAPR) Protected Execution Facility (PEF) +----------------------------------------------- + +Protected Execution Facility (PEF), also known as Secure Guest support +is a feature found on IBM POWER9 and POWER10 processors. + +If a suitable firmware including an Ultravisor is installed, it adds +an extra memory protection mode to the CPU. The ultravisor manages a +pool of secure memory which cannot be accessed by the hypervisor. + +When this feature is enabled in QEMU, a guest can use ultracalls to +enter "secure mode". This transfers most of its memory to secure +memory, where it cannot be eavesdropped by a compromised hypervisor. + +Launching +^^^^^^^^^ + +To launch a guest which will be permitted to enter PEF secure mode:: + + $ qemu-system-ppc64 \ + -object pef-guest,id=pef0 \ + -machine confidential-guest-support=pef0 \ + ... + +Live Migration +^^^^^^^^^^^^^^ + +Live migration is not yet implemented for PEF guests. For +consistency, QEMU currently prevents migration if the PEF feature is +enabled, whether or not the guest has actually entered secure mode. + + Maintainer contact information ------------------------------ -- 2.31.1 From: Thomas Huth <thuth@redhat.com> Add some documentation files to the corresponding machine sections and mention the machine names in the section titles where it is not so obvious (e.g. that "taihu" is a 405 machine). Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220105104800.407570-1-thuth@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- MAINTAINERS | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: hw/openrisc/openrisc_sim.c PowerPC Machines ---------------- -405 +405 (ref405ep and taihu) L: qemu-ppc@nongnu.org S: Orphan F: hw/ppc/ppc405_boards.c @@ -XXX,XX +XXX,XX @@ New World (mac99) M: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> L: qemu-ppc@nongnu.org S: Odd Fixes +F: docs/system/ppc/powermac.rst F: hw/ppc/mac_newworld.c F: hw/pci-host/uninorth.c F: hw/pci-bridge/dec.[hc] @@ -XXX,XX +XXX,XX @@ Old World (g3beige) M: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> L: qemu-ppc@nongnu.org S: Odd Fixes +F: docs/system/ppc/powermac.rst F: hw/ppc/mac_oldworld.c F: hw/pci-host/grackle.c F: hw/misc/macio/ @@ -XXX,XX +XXX,XX @@ PReP M: Hervé Poussineau <hpoussin@reactos.org> L: qemu-ppc@nongnu.org S: Maintained +F: docs/system/ppc/prep.rst F: hw/ppc/prep.c F: hw/ppc/prep_systemio.c F: hw/ppc/rs6000_mc.c @@ -XXX,XX +XXX,XX @@ F: include/hw/isa/pc87312.h F: include/hw/rtc/m48t59.h F: tests/avocado/ppc_prep_40p.py -sPAPR +sPAPR (pseries) M: Cédric Le Goater <clg@kaod.org> M: Daniel Henrique Barboza <danielhb413@gmail.com> R: David Gibson <david@gibson.dropbear.id.au> @@ -XXX,XX +XXX,XX @@ F: include/hw/*/spapr* F: hw/*/xics* F: include/hw/*/xics* F: pc-bios/slof.bin -F: docs/specs/ppc-spapr-hcalls.txt -F: docs/specs/ppc-spapr-hotplug.txt +F: docs/system/ppc/pseries.rst +F: docs/specs/ppc-spapr-* F: tests/qtest/spapr* F: tests/qtest/libqos/*spapr* F: tests/qtest/rtas* @@ -XXX,XX +XXX,XX @@ PowerNV (Non-Virtualized) M: Cédric Le Goater <clg@kaod.org> L: qemu-ppc@nongnu.org S: Maintained +F: docs/system/ppc/powernv.rst F: hw/ppc/pnv* F: hw/intc/pnv* F: hw/intc/xics_pnv.c -- 2.31.1 From: Leonardo Garcia <lagarcia@br.ibm.com> Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <3b228af4785241c7fb4a2c70f0c495d2a9adea83.1641405872.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- docs/specs/ppc-spapr-hcalls.rst | 21 ++++++++--------- docs/system/ppc/pseries.rst | 42 ++++++++++++++++----------------- 2 files changed, 31 insertions(+), 32 deletions(-) diff --git a/docs/specs/ppc-spapr-hcalls.rst b/docs/specs/ppc-spapr-hcalls.rst index XXXXXXX..XXXXXXX 100644 --- a/docs/specs/ppc-spapr-hcalls.rst +++ b/docs/specs/ppc-spapr-hcalls.rst @@ -XXX,XX +XXX,XX @@ +====================== sPAPR hypervisor calls ----------------------- +====================== When used with the ``pseries`` machine type, ``qemu-system-ppc64`` implements -a set of hypervisor calls (a.k.a. hcalls) defined in the `Linux on Power -Architecture Reference document (LoPAR) -<https://cdn.openpowerfoundation.org/wp-content/uploads/2020/07/LoPAR-20200812.pdf>`_. -This document is a subset of the Power Architecture Platform Reference (PAPR+) -specification (IBM internal only), which is what PowerVM, the IBM proprietary -hypervisor, adheres to. +a set of hypervisor calls (a.k.a. hcalls) defined in the Linux on Power +Architecture Reference ([LoPAR]_) document. This document is a subset of the +Power Architecture Platform Reference (PAPR+) specification (IBM internal only), +which is what PowerVM, the IBM proprietary hypervisor, adheres to. The subset in LoPAR is selected based on the requirements of Linux as a guest. @@ -XXX,XX +XXX,XX @@ running in the guest and QEMU. All those hypercalls start at hcall number 0xf000 which correspond to an implementation specific range in PAPR. -H_RTAS (0xf000) -^^^^^^^^^^^^^^^ +``H_RTAS (0xf000)`` +=================== RTAS stands for Run-Time Abstraction Sercies and is a set of runtime services generally provided by the firmware inside the guest to the operating system. It @@ -XXX,XX +XXX,XX @@ Returns: ``H_PARAMETER``: Unknown token. -H_LOGICAL_MEMOP (0xf001) -^^^^^^^^^^^^^^^^^^^^^^^^ +``H_LOGICAL_MEMOP (0xf001)`` +============================ When the guest runs in "real mode" (in powerpc terminology this means with MMU disabled, i.e. guest effective address equals to guest physical address), it diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst index XXXXXXX..XXXXXXX 100644 --- a/docs/system/ppc/pseries.rst +++ b/docs/system/ppc/pseries.rst @@ -XXX,XX +XXX,XX @@ +=================================== pSeries family boards (``pseries``) =================================== -The Power machine para-virtualized environment described by the `Linux on Power -Architecture Reference document (LoPAR) -<https://openpowerfoundation.org/wp-content/uploads/2020/07/LoPAR-20200812.pdf>`_ -is called pSeries. This environment is also known as sPAPR, System p guests, or -simply Power Linux guests (although it is capable of running other operating -systems, such as AIX). +The Power machine para-virtualized environment described by the Linux on Power +Architecture Reference ([LoPAR]_) document is called pSeries. This environment +is also known as sPAPR, System p guests, or simply Power Linux guests (although +it is capable of running other operating systems, such as AIX). Even though pSeries is designed to behave as a guest environment, it is also capable of acting as a hypervisor OS, providing, on that role, nested virtualization capabilities. Supported devices ------------------ +================= * Multi processor support for many Power processors generations: POWER7, POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists, @@ -XXX,XX +XXX,XX @@ Supported devices * PCIe device pass through. Missing devices ---------------- +=============== * SPICE support. Firmware --------- +======== `SLOF <https://github.com/aik/SLOF>`_ (Slimline Open Firmware) is an implementation of the `IEEE 1275-1994, Standard for Boot (Initialization @@ -XXX,XX +XXX,XX @@ QEMU includes a prebuilt image of SLOF which is updated when a more recent version is required. Build directions ----------------- +================ .. code-block:: bash ./configure --target-list=ppc64-softmmu && make Running instructions --------------------- +==================== Someone can select the pSeries machine type by running QEMU with the following options: @@ -XXX,XX +XXX,XX @@ options: qemu-system-ppc64 -M pseries <other QEMU arguments> sPAPR devices -------------- +============= The sPAPR specification defines a set of para-virtualized devices, which are also supported by the pSeries machine in QEMU and can be instantiated with the @@ -XXX,XX +XXX,XX @@ device, or specify one with an ID NVRAM device with ``-global spapr-nvram.drive=pfid``. sPAPR specification -^^^^^^^^^^^^^^^^^^^ +------------------- -The main source of documentation on the sPAPR standard is the `Linux on Power -Architecture Reference document (LoPAR) -<https://openpowerfoundation.org/wp-content/uploads/2020/07/LoPAR-20200812.pdf>`_. +The main source of documentation on the sPAPR standard is the [LoPAR]_ document. However, documentation specific to QEMU's implementation of the specification can also be found in QEMU documentation: @@ -XXX,XX +XXX,XX @@ Other documentation available in QEMU docs directory: (``/docs/specs/ppc-spapr-uv-hcalls.txt``). Switching between the KVM-PR and KVM-HV kernel module ------------------------------------------------------ +===================================================== Currently, there are two implementations of KVM on Power, ``kvm_hv.ko`` and ``kvm_pr.ko``. @@ -XXX,XX +XXX,XX @@ possible to switch between the two modes with the ``kvm-type`` parameter: instead. KVM-PR -^^^^^^ +------ KVM-PR uses the so-called **PR**\ oblem state of the PPC CPUs to run the guests, i.e. the virtual machine is run in user mode and all privileged instructions @@ -XXX,XX +XXX,XX @@ In order to run KVM-PR guests with POWER9 processors, someone will need to start QEMU with ``kernel_irqchip=off`` command line option. KVM-HV -^^^^^^ +------ KVM-HV uses the hypervisor mode of more recent Power processors, that allow access to the bare metal hardware directly. Although POWER7 had this capability, @@ -XXX,XX +XXX,XX @@ CPUs generations, e.g. you can run a POWER7 guest on a POWER8 host by using ``-cpu POWER8,compat=power7`` as parameter to QEMU. Modules support ---------------- +=============== As noticed in the sections above, each module can run in a different environment. The following table shows with which environment each module can @@ -XXX,XX +XXX,XX @@ enabled, whether or not the guest has actually entered secure mode. Maintainer contact information ------------------------------- +============================== Cédric Le Goater <clg@kaod.org> Daniel Henrique Barboza <danielhb413@gmail.com> + +.. [LoPAR] `Linux on Power Architecture Reference document (LoPAR) revision + 2.9 <https://openpowerfoundation.org/wp-content/uploads/2020/07/LoPAR-20200812.pdf>`_. -- 2.31.1 From: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107222601.4101511-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- target/ppc/excp_helper.c | 65 +++++++++++++++++++++++----------------- 1 file changed, 37 insertions(+), 28 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -XXX,XX +XXX,XX @@ static void dump_hcall(CPUPPCState *env) env->nip); } +static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp) +{ +#if defined(DEBUG_SOFTWARE_TLB) + const char *es; + target_ulong *miss, *cmp; + int en; + + if (!qemu_log_enabled()) { + return; + } + + if (excp == POWERPC_EXCP_IFTLB) { + es = "I"; + en = 'I'; + miss = &env->spr[SPR_IMISS]; + cmp = &env->spr[SPR_ICMP]; + } else { + if (excp == POWERPC_EXCP_DLTLB) { + es = "DL"; + } else { + es = "DS"; + } + en = 'D'; + miss = &env->spr[SPR_DMISS]; + cmp = &env->spr[SPR_DCMP]; + } + qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " + TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 " + TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, + env->spr[SPR_HASH1], env->spr[SPR_HASH2], + env->error_code); +#endif +} + + static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp, target_ulong *msr) { @@ -XXX,XX +XXX,XX @@ static void powerpc_excp(PowerPCCPU *cpu, int excp) } /* fall through */ case POWERPC_EXCP_7x5: -#if defined(DEBUG_SOFTWARE_TLB) - if (qemu_log_enabled()) { - const char *es; - target_ulong *miss, *cmp; - int en; - - if (excp == POWERPC_EXCP_IFTLB) { - es = "I"; - en = 'I'; - miss = &env->spr[SPR_IMISS]; - cmp = &env->spr[SPR_ICMP]; - } else { - if (excp == POWERPC_EXCP_DLTLB) { - es = "DL"; - } else { - es = "DS"; - } - en = 'D'; - miss = &env->spr[SPR_DMISS]; - cmp = &env->spr[SPR_DCMP]; - } - qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " - TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 " - TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, - env->spr[SPR_HASH1], env->spr[SPR_HASH2], - env->error_code); - } -#endif + ppc_excp_debug_sw_tlb(env, excp); + msr |= env->crf[0] << 28; msr |= env->error_code; /* key, D/I, S/L bits */ /* Set way using a LRU mechanism */ -- 2.31.1 From: Fabiano Rosas <farosas@linux.ibm.com> Remove the compile time definition and make the logging be controlled by the `-d mmu` option in the cmdline. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220107222601.4101511-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- target/ppc/excp_helper.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -XXX,XX +XXX,XX @@ #include "exec/cpu_ldst.h" #endif -/* #define DEBUG_SOFTWARE_TLB */ - /*****************************************************************************/ /* Exception processing */ #if !defined(CONFIG_USER_ONLY) @@ -XXX,XX +XXX,XX @@ static void dump_hcall(CPUPPCState *env) static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp) { -#if defined(DEBUG_SOFTWARE_TLB) const char *es; target_ulong *miss, *cmp; int en; - if (!qemu_log_enabled()) { + if (!qemu_loglevel_mask(CPU_LOG_MMU)) { return; } @@ -XXX,XX +XXX,XX @@ static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp) TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, env->spr[SPR_HASH1], env->spr[SPR_HASH2], env->error_code); -#endif } -- 2.31.1 From: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107222601.4101511-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- target/ppc/excp_helper.c | 77 +++++----------------------------------- 1 file changed, 8 insertions(+), 69 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -XXX,XX +XXX,XX @@ static void powerpc_excp(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */ env->spr[SPR_BOOKE_ESR] = ESR_SPV; break; - case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ - /* XXX: TODO */ - cpu_abort(cs, "Embedded floating point data exception " - "is not implemented yet !\n"); - env->spr[SPR_BOOKE_ESR] = ESR_SPV; - break; - case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ - /* XXX: TODO */ - cpu_abort(cs, "Embedded floating point round exception " - "is not implemented yet !\n"); - env->spr[SPR_BOOKE_ESR] = ESR_SPV; - break; - case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ - /* XXX: TODO */ - cpu_abort(cs, - "Performance counter exception is not implemented yet !\n"); - break; case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ break; case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ @@ -XXX,XX +XXX,XX @@ static void powerpc_excp(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ trace_ppc_excp_print("PIT"); break; - case POWERPC_EXCP_IO: /* IO error exception */ - /* XXX: TODO */ - cpu_abort(cs, "601 IO error exception is not implemented yet !\n"); - break; - case POWERPC_EXCP_RUNM: /* Run mode exception */ - /* XXX: TODO */ - cpu_abort(cs, "601 run mode exception is not implemented yet !\n"); - break; - case POWERPC_EXCP_EMUL: /* Emulation trap exception */ - /* XXX: TODO */ - cpu_abort(cs, "602 emulation trap exception " - "is not implemented yet !\n"); - break; case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ @@ -XXX,XX +XXX,XX @@ static void powerpc_excp(PowerPCCPU *cpu, int excp) break; } break; + case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ + case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ + case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ + case POWERPC_EXCP_IO: /* IO error exception */ + case POWERPC_EXCP_RUNM: /* Run mode exception */ + case POWERPC_EXCP_EMUL: /* Emulation trap exception */ case POWERPC_EXCP_FPA: /* Floating-point assist exception */ - /* XXX: TODO */ - cpu_abort(cs, "Floating point assist exception " - "is not implemented yet !\n"); - break; case POWERPC_EXCP_DABR: /* Data address breakpoint */ - /* XXX: TODO */ - cpu_abort(cs, "DABR exception is not implemented yet !\n"); - break; case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ - /* XXX: TODO */ - cpu_abort(cs, "IABR exception is not implemented yet !\n"); - break; case POWERPC_EXCP_SMI: /* System management interrupt */ - /* XXX: TODO */ - cpu_abort(cs, "SMI exception is not implemented yet !\n"); - break; case POWERPC_EXCP_THERM: /* Thermal interrupt */ - /* XXX: TODO */ - cpu_abort(cs, "Thermal management exception " - "is not implemented yet !\n"); - break; case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ - /* XXX: TODO */ - cpu_abort(cs, - "Performance counter exception is not implemented yet !\n"); - break; case POWERPC_EXCP_VPUA: /* Vector assist exception */ - /* XXX: TODO */ - cpu_abort(cs, "VPU assist exception is not implemented yet !\n"); - break; case POWERPC_EXCP_SOFTP: /* Soft patch exception */ - /* XXX: TODO */ - cpu_abort(cs, - "970 soft-patch exception is not implemented yet !\n"); - break; case POWERPC_EXCP_MAINT: /* Maintenance exception */ - /* XXX: TODO */ - cpu_abort(cs, - "970 maintenance exception is not implemented yet !\n"); - break; case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ - /* XXX: TODO */ - cpu_abort(cs, "Maskable external exception " - "is not implemented yet !\n"); - break; case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ - /* XXX: TODO */ - cpu_abort(cs, "Non maskable external exception " - "is not implemented yet !\n"); + cpu_abort(cs, "%s exception not implemented\n", + powerpc_excp_name(excp)); break; default: excp_invalid: -- 2.31.1 From: Fabiano Rosas <farosas@linux.ibm.com> The ppc_interrupts_little_endian function could be used for interrupts delivered in Hypervisor mode, so add support for powernv8 and powernv9 to it. Also drop the comment because it is inaccurate, all CPUs that can run little endian can have interrupts in little endian. The point is whether they can take interrupts in an endianness different from MSR_LE. This change has no functional impact. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220107222601.4101511-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- target/ppc/cpu.h | 23 +++++++++++++++-------- target/ppc/arch_dump.c | 2 +- target/ppc/excp_helper.c | 2 +- 3 files changed, 17 insertions(+), 10 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -XXX,XX +XXX,XX @@ static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr) return cpu->env.spr_cb[spr].name != NULL; } -static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu) +#if !defined(CONFIG_USER_ONLY) +static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv) { PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + CPUPPCState *env = &cpu->env; + bool ile = false; + + if (hv && env->has_hv_mode) { + if (is_isa300(pcc)) { + ile = !!(env->spr[SPR_HID0] & HID0_POWER9_HILE); + } else { + ile = !!(env->spr[SPR_HID0] & HID0_HILE); + } - /* - * Only models that have an LPCR and know about LPCR_ILE can do little - * endian. - */ - if (pcc->lpcr_mask & LPCR_ILE) { - return !!(cpu->env.spr[SPR_LPCR] & LPCR_ILE); + } else if (pcc->lpcr_mask & LPCR_ILE) { + ile = !!(env->spr[SPR_LPCR] & LPCR_ILE); } - return false; + return ile; } +#endif void dump_mmu(CPUPPCState *env); diff --git a/target/ppc/arch_dump.c b/target/ppc/arch_dump.c index XXXXXXX..XXXXXXX 100644 --- a/target/ppc/arch_dump.c +++ b/target/ppc/arch_dump.c @@ -XXX,XX +XXX,XX @@ int cpu_get_dump_info(ArchDumpInfo *info, info->d_machine = PPC_ELF_MACHINE; info->d_class = ELFCLASS; - if (ppc_interrupts_little_endian(cpu)) { + if (ppc_interrupts_little_endian(cpu, false)) { info->d_endian = ELFDATA2LSB; } else { info->d_endian = ELFDATA2MSB; diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -XXX,XX +XXX,XX @@ void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector) */ msr = (1ULL << MSR_ME); msr |= env->msr & (1ULL << MSR_SF); - if (ppc_interrupts_little_endian(cpu)) { + if (ppc_interrupts_little_endian(cpu, false)) { msr |= (1ULL << MSR_LE); } -- 2.31.1 From: Fabiano Rosas <farosas@linux.ibm.com> Some CPUs set ILE via an MSR bit. We can make ppc_interrupts_little_endian handle that case as well. Now we have a centralized way of determining the endianness of interrupts. This change has no functional impact. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220107222601.4101511-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- target/ppc/cpu.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -XXX,XX +XXX,XX @@ static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv) { PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env = &cpu->env; - bool ile = false; + bool ile; if (hv && env->has_hv_mode) { if (is_isa300(pcc)) { @@ -XXX,XX +XXX,XX @@ static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv) } else if (pcc->lpcr_mask & LPCR_ILE) { ile = !!(env->spr[SPR_LPCR] & LPCR_ILE); + } else { + ile = !!(msr_ile); } return ile; -- 2.31.1 From: Fabiano Rosas <farosas@linux.ibm.com> The ppc_interrupts_little_endian function is now suitable for determining the endianness of interrupts for all CPUs. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220107222601.4101511-7-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- target/ppc/excp_helper.c | 29 +---------------------------- 1 file changed, 1 insertion(+), 28 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -XXX,XX +XXX,XX @@ static void powerpc_excp(PowerPCCPU *cpu, int excp) * Sort out endianness of interrupt, this differs depending on the * CPU, the HV mode, etc... */ -#ifdef TARGET_PPC64 - if (excp_model == POWERPC_EXCP_POWER7) { - if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) { - new_msr |= (target_ulong)1 << MSR_LE; - } - } else if (excp_model == POWERPC_EXCP_POWER8) { - if (new_msr & MSR_HVB) { - if (env->spr[SPR_HID0] & HID0_HILE) { - new_msr |= (target_ulong)1 << MSR_LE; - } - } else if (env->spr[SPR_LPCR] & LPCR_ILE) { - new_msr |= (target_ulong)1 << MSR_LE; - } - } else if (excp_model == POWERPC_EXCP_POWER9 || - excp_model == POWERPC_EXCP_POWER10) { - if (new_msr & MSR_HVB) { - if (env->spr[SPR_HID0] & HID0_POWER9_HILE) { - new_msr |= (target_ulong)1 << MSR_LE; - } - } else if (env->spr[SPR_LPCR] & LPCR_ILE) { - new_msr |= (target_ulong)1 << MSR_LE; - } - } else if (msr_ile) { - new_msr |= (target_ulong)1 << MSR_LE; - } -#else - if (msr_ile) { + if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { new_msr |= (target_ulong)1 << MSR_LE; } -#endif #if defined(TARGET_PPC64) if (excp_model == POWERPC_EXCP_BOOKE) { -- 2.31.1 From: Fabiano Rosas <farosas@linux.ibm.com> Next patches will split powerpc_excp in multiple family specific handlers. This patch adds a wrapper to make the transition clearer. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220107222601.4101511-8-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- target/ppc/excp_helper.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -XXX,XX +XXX,XX @@ static void powerpc_set_excp_state(PowerPCCPU *cpu, * Note that this function should be greatly optimized when called * with a constant excp, from ppc_hw_interrupt */ -static void powerpc_excp(PowerPCCPU *cpu, int excp) +static inline void powerpc_excp_legacy(PowerPCCPU *cpu, int excp) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; @@ -XXX,XX +XXX,XX @@ static void powerpc_excp(PowerPCCPU *cpu, int excp) powerpc_set_excp_state(cpu, vector, new_msr); } +static void powerpc_excp(PowerPCCPU *cpu, int excp) +{ + CPUPPCState *env = &cpu->env; + + switch (env->excp_model) { + default: + powerpc_excp_legacy(cpu, excp); + } +} + void ppc_cpu_do_interrupt(CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); -- 2.31.1 From: Fabiano Rosas <farosas@linux.ibm.com> We use the endianness of interrupts to determine which endianness to use for the guest kernel memory dump. For machines that support HILE (powernv8 and up) we have been always generating big endian dump files. This patch uses the HILE support recently added to ppc_interrupts_little_endian to fix the endianness of the dumps for powernv machines. Here are two dumps created at different moments: $ file skiboot.dump skiboot.dump: ELF 64-bit MSB core file, 64-bit PowerPC ... $ file kernel.dump kernel.dump: ELF 64-bit LSB core file, 64-bit PowerPC ... Suggested-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220107222601.4101511-9-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- target/ppc/arch_dump.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/arch_dump.c b/target/ppc/arch_dump.c index XXXXXXX..XXXXXXX 100644 --- a/target/ppc/arch_dump.c +++ b/target/ppc/arch_dump.c @@ -XXX,XX +XXX,XX @@ int cpu_get_dump_info(ArchDumpInfo *info, info->d_machine = PPC_ELF_MACHINE; info->d_class = ELFCLASS; - if (ppc_interrupts_little_endian(cpu, false)) { + if (ppc_interrupts_little_endian(cpu, cpu->env.has_hv_mode)) { info->d_endian = ELFDATA2LSB; } else { info->d_endian = ELFDATA2MSB; -- 2.31.1 From: Daniel Henrique Barboza <danielhb413@gmail.com> When creating a pnv_phb3_root_port using the command line, the first root port is created successfully, but the second fails with the following error: qemu-system-ppc64: -device pnv-phb3-root-port,bus=phb3-root.0,id=pcie.3: Can't add chassis slot, error -16 This error comes from the realize() function of its parent type, rp_realize() from TYPE_PCIE_ROOT_PORT. pcie_chassis_add_slot() fails with -EBUSY if there's an existing PCIESlot that has the same chassis/slot value, regardless of being in a different bus. One way to prevent this error is simply set chassis and slot values in the command line. However, since phb3 root buses only supports a single root port, we can just get an unique chassis/slot value by checking which root bus the pnv_phb3_root_port is going to be attached, get the equivalent phb3 device and use its chip-id and index values, which are guaranteed to be unique. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220105212338.49899-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/pci-host/pnv_phb3.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -XXX,XX +XXX,XX @@ static const TypeInfo pnv_phb3_root_bus_info = { static void pnv_phb3_root_port_realize(DeviceState *dev, Error **errp) { PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); + PCIDevice *pci = PCI_DEVICE(dev); + PCIBus *bus = pci_get_bus(pci); + PnvPHB3 *phb = NULL; Error *local_err = NULL; + phb = (PnvPHB3 *) object_dynamic_cast(OBJECT(bus->qbus.parent), + TYPE_PNV_PHB3); + + if (!phb) { + error_setg(errp, +"pnv_phb3_root_port devices must be connected to pnv-phb3 buses"); + return; + } + + /* Set unique chassis/slot values for the root port */ + qdev_prop_set_uint8(&pci->qdev, "chassis", phb->chip_id); + qdev_prop_set_uint16(&pci->qdev, "slot", phb->phb_id); + rpc->parent_realize(dev, &local_err); if (local_err) { error_propagate(errp, local_err); -- 2.31.1 From: Daniel Henrique Barboza <danielhb413@gmail.com> A similar situation as described previously with pnv_phb3_root_port devices also happens with pnv_phb4_root_ports. The solution is the same: assign an unique chassis/slot combo for them. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220105212338.49899-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/pci-host/pnv_phb4.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -XXX,XX +XXX,XX @@ static void pnv_phb4_root_port_reset(DeviceState *dev) static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp) { PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); + PCIDevice *pci = PCI_DEVICE(dev); + PCIBus *bus = pci_get_bus(pci); + PnvPHB4 *phb = NULL; Error *local_err = NULL; + phb = (PnvPHB4 *) object_dynamic_cast(OBJECT(bus->qbus.parent), + TYPE_PNV_PHB4); + + if (!phb) { + error_setg(errp, "%s must be connected to pnv-phb4 buses", dev->id); + return; + } + + /* Set unique chassis/slot values for the root port */ + qdev_prop_set_uint8(&pci->qdev, "chassis", phb->chip_id); + qdev_prop_set_uint16(&pci->qdev, "slot", phb->phb_id); + rpc->parent_realize(dev, &local_err); if (local_err) { error_propagate(errp, local_err); -- 2.31.1 This cleanups the PHB3 model a bit more since the root port is an independent device and it will ease our task when adding user created PHB3s. pnv_phb_attach_root_port() is made public in pnv.c so it can be reused with the pnv_phb4 root port later. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220105212338.49899-4-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- include/hw/pci-host/pnv_phb3.h | 2 -- include/hw/ppc/pnv.h | 1 + hw/pci-host/pnv_phb3.c | 15 ++++++--------- hw/ppc/pnv.c | 8 ++++++++ 4 files changed, 15 insertions(+), 11 deletions(-) diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/pci-host/pnv_phb3.h +++ b/include/hw/pci-host/pnv_phb3.h @@ -XXX,XX +XXX,XX @@ struct PnvPHB3 { PnvPBCQState pbcq; - PnvPHB3RootPort root; - QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces; PnvChip *chip; diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, TYPE_PNV_CHIP_POWER10) PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); +void pnv_phb_attach_root_port(PCIHostState *pci, const char *name); #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") typedef struct PnvMachineClass PnvMachineClass; diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -XXX,XX +XXX,XX @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "qom/object.h" +#include "sysemu/sysemu.h" #define phb3_error(phb, fmt, ...) \ qemu_log_mask(LOG_GUEST_ERROR, "phb3[%d:%d]: " fmt "\n", \ @@ -XXX,XX +XXX,XX @@ static void pnv_phb3_instance_init(Object *obj) /* Power Bus Common Queue */ object_initialize_child(obj, "pbcq", &phb->pbcq, TYPE_PNV_PBCQ); - /* Root Port */ - object_initialize_child(obj, "root", &phb->root, TYPE_PNV_PHB3_ROOT_PORT); - qdev_prop_set_int32(DEVICE(&phb->root), "addr", PCI_DEVFN(0, 0)); - qdev_prop_set_bit(DEVICE(&phb->root), "multifunction", false); } static void pnv_phb3_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp) pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb); - /* Add a single Root port */ - qdev_prop_set_uint8(DEVICE(&phb->root), "chassis", phb->chip_id); - qdev_prop_set_uint16(DEVICE(&phb->root), "slot", phb->phb_id); - qdev_realize(DEVICE(&phb->root), BUS(pci->bus), &error_fatal); + if (defaults_enabled()) { + pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), + TYPE_PNV_PHB3_ROOT_PORT); + } } void pnv_phb3_update_regions(PnvPHB3 *phb) @@ -XXX,XX +XXX,XX @@ static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data) device_class_set_parent_realize(dc, pnv_phb3_root_port_realize, &rpc->parent_realize); - dc->user_creatable = false; + dc->user_creatable = true; k->vendor_id = PCI_VENDOR_ID_IBM; k->device_id = 0x03dc; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index XXXXXXX..XXXXXXX 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -XXX,XX +XXX,XX @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) } } +/* Attach a root port device */ +void pnv_phb_attach_root_port(PCIHostState *pci, const char *name) +{ + PCIDevice *root = pci_new(PCI_DEVFN(0, 0), name); + + pci_realize_and_unref(root, pci->bus, &error_fatal); +} + static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) { PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); -- 2.31.1 From: Daniel Henrique Barboza <danielhb413@gmail.com> We want to create only the absolutely minimal amount of devices when running with -nodefaults. The root port is something that the machine can boot up without. But, to do that, we need to provide a way for the user to add them by hand. This patch makes pnv-phb4-root-port user creatable and then uses the pnv_phb_attach_root_port() helper to add a pnv_phb4_root_port only when running with default settings. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220105212338.49899-5-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- include/hw/pci-host/pnv_phb4.h | 2 -- hw/pci-host/pnv_phb4.c | 18 +++++++----------- 2 files changed, 7 insertions(+), 13 deletions(-) diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4) struct PnvPHB4 { PCIExpressHost parent_obj; - PnvPHB4RootPort root; - uint32_t chip_id; uint32_t phb_id; diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -XXX,XX +XXX,XX @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "qom/object.h" +#include "sysemu/sysemu.h" #include "trace.h" #define phb_error(phb, fmt, ...) \ @@ -XXX,XX +XXX,XX @@ static void pnv_phb4_instance_init(Object *obj) /* XIVE interrupt source object */ object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE); - - /* Root Port */ - object_initialize_child(obj, "root", &phb->root, TYPE_PNV_PHB4_ROOT_PORT); - - qdev_prop_set_int32(DEVICE(&phb->root), "addr", PCI_DEVFN(0, 0)); - qdev_prop_set_bit(DEVICE(&phb->root), "multifunction", false); } static void pnv_phb4_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp) pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb); pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; - /* Add a single Root port */ - qdev_prop_set_uint8(DEVICE(&phb->root), "chassis", phb->chip_id); - qdev_prop_set_uint16(DEVICE(&phb->root), "slot", phb->phb_id); - qdev_realize(DEVICE(&phb->root), BUS(pci->bus), &error_fatal); + /* Add a single Root port if running with defaults */ + if (defaults_enabled()) { + pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), + TYPE_PNV_PHB4_ROOT_PORT); + } /* Setup XIVE Source */ if (phb->big_phb) { @@ -XXX,XX +XXX,XX @@ static void pnv_phb4_root_port_class_init(ObjectClass *klass, void *data) PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); dc->desc = "IBM PHB4 PCIE Root Port"; - dc->user_creatable = false; + dc->user_creatable = true; device_class_set_parent_realize(dc, pnv_phb4_root_port_realize, &rpc->parent_realize); -- 2.31.1 From: Daniel Henrique Barboza <danielhb413@gmail.com> pnv_phb4_rc_config_read() and pnv_phb4_rc_config_write() are asserting the existence of the root port. The root port is now optional, and there will be cases where a pnv-phb4 device won't have a root port attached. Instead of asserting, check if the root port exists before read/writing into it. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220105212338.49899-6-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/pci-host/pnv_phb4.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -XXX,XX +XXX,XX @@ static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off, } pdev = pci_find_device(pci->bus, 0, 0); - assert(pdev); + if (!pdev) { + phb_error(phb, "rc_config_write device not found\n"); + return; + } pci_host_config_write_common(pdev, off, PHB_RC_CONFIG_SIZE, bswap32(val), 4); @@ -XXX,XX +XXX,XX @@ static uint64_t pnv_phb4_rc_config_read(PnvPHB4 *phb, unsigned off, } pdev = pci_find_device(pci->bus, 0, 0); - assert(pdev); + if (!pdev) { + phb_error(phb, "rc_config_read device not found\n"); + return ~0ull; + } val = pci_host_config_read_common(pdev, off, PHB_RC_CONFIG_SIZE, 4); return bswap32(val); -- 2.31.1 PHB3 devices and PCI devices can now be added to the powernv8 machine using : -device pnv-phb3,chip-id=0,index=1 \ -device nec-usb-xhci,bus=pci.1,addr=0x0 The 'index' property identifies the PHB3 in the chip. In case of user created devices, a lookup on 'chip-id' is required to assign the owning chip. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220105212338.49899-7-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- include/hw/ppc/pnv.h | 2 ++ hw/pci-host/pnv_phb3.c | 11 ++++++++++- hw/ppc/pnv.c | 23 ++++++++++++++++++----- 3 files changed, 30 insertions(+), 6 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -XXX,XX +XXX,XX @@ struct PnvMachineState { hwaddr fw_load_addr; }; +PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id); + #define PNV_FDT_ADDR 0x01000000 #define PNV_TIMEBASE_FREQ 512000000ULL diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -XXX,XX +XXX,XX @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp) PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); int i; + /* User created devices */ + if (!phb->chip) { + phb->chip = pnv_get_chip(pnv, phb->chip_id); + if (!phb->chip) { + error_setg(errp, "invalid chip id: %d", phb->chip_id); + return; + } + } + if (phb->phb_id >= PNV_CHIP_GET_CLASS(phb->chip)->num_phbs) { error_setg(errp, "invalid PHB index: %d", phb->phb_id); return; @@ -XXX,XX +XXX,XX @@ static void pnv_phb3_class_init(ObjectClass *klass, void *data) dc->realize = pnv_phb3_realize; device_class_set_props(dc, pnv_phb3_properties); set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->user_creatable = false; + dc->user_creatable = true; } static const TypeInfo pnv_phb3_type_info = { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index XXXXXXX..XXXXXXX 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -XXX,XX +XXX,XX @@ static void pnv_chip_power8_instance_init(Object *obj) object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); - for (i = 0; i < pcc->num_phbs; i++) { + if (defaults_enabled()) { + chip->num_phbs = pcc->num_phbs; + } + + for (i = 0; i < chip->num_phbs; i++) { object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); } - /* - * Number of PHBs is the chip default - */ - chip->num_phbs = pcc->num_phbs; } static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) @@ -XXX,XX +XXX,XX @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq) return NULL; } +PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) +{ + int i; + + for (i = 0; i < pnv->num_chips; i++) { + PnvChip *chip = pnv->chips[i]; + if (chip->chip_id == chip_id) { + return chip; + } + } + return NULL; +} + static int pnv_ics_resend_child(Object *child, void *opaque) { PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); -- 2.31.1 The powernv machine uses the object hierarchy to populate the device tree and each device should be parented to the chip it belongs to. This is not the case for user created devices which are parented to the container "/unattached". Make sure a PHB3 device is parented to its chip by reparenting the object if necessary. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220105212338.49899-8-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- include/hw/ppc/pnv.h | 1 + hw/pci-host/pnv_phb3.c | 6 ++++++ hw/ppc/pnv.c | 17 +++++++++++++++++ 3 files changed, 24 insertions(+) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); void pnv_phb_attach_root_port(PCIHostState *pci, const char *name); +void pnv_chip_parent_fixup(PnvChip *chip, Object *obj, int index); #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") typedef struct PnvMachineClass PnvMachineClass; diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -XXX,XX +XXX,XX @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp) error_setg(errp, "invalid chip id: %d", phb->chip_id); return; } + + /* + * Reparent user created devices to the chip to build + * correctly the device tree. + */ + pnv_chip_parent_fixup(phb->chip, OBJECT(phb), phb->phb_id); } if (phb->phb_id >= PNV_CHIP_GET_CLASS(phb->chip)->num_phbs) { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index XXXXXXX..XXXXXXX 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -XXX,XX +XXX,XX @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq) return NULL; } +void pnv_chip_parent_fixup(PnvChip *chip, Object *obj, int index) +{ + Object *parent = OBJECT(chip); + g_autofree char *default_id = + g_strdup_printf("%s[%d]", object_get_typename(obj), index); + + if (obj->parent == parent) { + return; + } + + object_ref(obj); + object_unparent(obj); + object_property_add_child( + parent, DEVICE(obj)->id ? DEVICE(obj)->id : default_id, obj); + object_unref(obj); +} + PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) { int i; -- 2.31.1 PHB3s ared SysBus devices and should be allowed to be dynamically created. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220105212338.49899-9-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/pci-host/pnv_phb3.c | 9 +++++++++ hw/ppc/pnv.c | 2 ++ 2 files changed, 11 insertions(+) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -XXX,XX +XXX,XX @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp) /* User created devices */ if (!phb->chip) { + Error *local_err = NULL; + BusState *s; + phb->chip = pnv_get_chip(pnv, phb->chip_id); if (!phb->chip) { error_setg(errp, "invalid chip id: %d", phb->chip_id); @@ -XXX,XX +XXX,XX @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp) * correctly the device tree. */ pnv_chip_parent_fixup(phb->chip, OBJECT(phb), phb->phb_id); + + s = qdev_get_parent_bus(DEVICE(phb->chip)); + if (!qdev_set_parent_bus(DEVICE(phb), s, &local_err)) { + error_propagate(errp, local_err); + return; + } } if (phb->phb_id >= PNV_CHIP_GET_CLASS(phb->chip)->num_phbs) { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index XXXXXXX..XXXXXXX 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -XXX,XX +XXX,XX @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) pmc->compat = compat; pmc->compat_size = sizeof(compat); + + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB3); } static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) -- 2.31.1 It is not used elsewhere so that's where it belongs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220105212338.49899-10-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- include/hw/ppc/pnv.h | 4 ++-- hw/ppc/pnv.c | 7 +++---- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -XXX,XX +XXX,XX @@ struct PnvChip { uint64_t cores_mask; PnvCore **cores; - uint32_t num_phbs; uint32_t num_pecs; MemoryRegion xscom_mmio; @@ -XXX,XX +XXX,XX @@ struct Pnv8Chip { #define PNV8_CHIP_PHB3_MAX 4 PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX]; + uint32_t num_phbs; XICSFabric *xics; }; @@ -XXX,XX +XXX,XX @@ struct PnvChipClass { /*< public >*/ uint64_t chip_cfam_id; uint64_t cores_mask; - uint32_t num_phbs; uint32_t num_pecs; + uint32_t num_phbs; DeviceRealize parent_realize; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index XXXXXXX..XXXXXXX 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -XXX,XX +XXX,XX @@ static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, static void pnv_chip_power8_instance_init(Object *obj) { - PnvChip *chip = PNV_CHIP(obj); Pnv8Chip *chip8 = PNV8_CHIP(obj); PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); int i; @@ -XXX,XX +XXX,XX @@ static void pnv_chip_power8_instance_init(Object *obj) object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); if (defaults_enabled()) { - chip->num_phbs = pcc->num_phbs; + chip8->num_phbs = pcc->num_phbs; } - for (i = 0; i < chip->num_phbs; i++) { + for (i = 0; i < chip8->num_phbs; i++) { object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); } @@ -XXX,XX +XXX,XX @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) &chip8->homer.regs); /* PHB3 controllers */ - for (i = 0; i < chip->num_phbs; i++) { + for (i = 0; i < chip8->num_phbs; i++) { PnvPHB3 *phb = &chip8->phbs[i]; object_property_set_int(OBJECT(phb), "index", i, &error_fatal); -- 2.31.1 From: Daniel Henrique Barboza <danielhb413@gmail.com> The TYPE_PNV_PHB3_ROOT_BUS name is used as the default bus name when the dev has no 'id'. However, pnv-phb3-root-bus is a bit too long to be used as a bus name. Most common QEMU buses and PCI controllers are named based on their bus type (e.g. pSeries spapr-pci-host-bridge is called 'pci'). The most common name for a PCIE bus controller in QEMU is 'pcie'. Naming it 'pcie' would break the documented use of the pnv-phb3 device, since 'pcie.0' would now refer to the root bus instead of the first root port. There's nothing particularly wrong with the 'root-bus' name used before, aside from the fact that 'root-bus' is being used for pnv-phb3 and pnv-phb4 created buses, which is not quite correct since these buses aren't implemented the same way in QEMU - you can't plug a pnv-phb4-root-port into a pnv-phb3 root bus, for example. This patch renames it as 'pnv-phb3-root', which is a compromise between the existing and the previously used name. Creating 3 phbs without ID will result in an "info qtree" output similar to this: bus: main-system-bus type System dev: pnv-phb3, id "" index = 2 (0x2) chip-id = 0 (0x0) x-config-reg-migration-enabled = true bypass-iommu = false bus: pnv-phb3-root.2 type pnv-phb3-root (...) dev: pnv-phb3, id "" index = 1 (0x1) chip-id = 0 (0x0) x-config-reg-migration-enabled = true bypass-iommu = false bus: pnv-phb3-root.1 type pnv-phb3-root (...) dev: pnv-phb3, id "" index = 0 (0x0) chip-id = 0 (0x0) x-config-reg-migration-enabled = true bypass-iommu = false bus: pnv-phb3-root.0 type pnv-phb3-root Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220105212338.49899-11-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- include/hw/pci-host/pnv_phb3.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/pci-host/pnv_phb3.h +++ b/include/hw/pci-host/pnv_phb3.h @@ -XXX,XX +XXX,XX @@ struct PnvPBCQState { /* * PHB3 PCIe Root port */ -#define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root-bus" +#define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root" #define TYPE_PNV_PHB3_ROOT_PORT "pnv-phb3-root-port" -- 2.31.1 From: Daniel Henrique Barboza <danielhb413@gmail.com> Similar to what was happening with pnv-phb3 buses, TYPE_PNV_PHB4_ROOT_BUS set to "pnv-phb4-root-bus" is a bit too long for a default root bus name. The usual default name for theses buses in QEMU are 'pcie', but we want to make a distinction between pnv-phb4 buses and other PCIE buses, at least as far as default name goes, because not all PCIE devices are attachable to a pnv-phb4 root-bus type. Changing the default to 'pnv-phb4-root' allow us to have a shorter name while making this bus distinct, and the user can always set its own bus naming via the "id" attribute anyway. This is the 'info qtree' output after this change, using a powernv9 domain with 2 sockets and default settings enabled: qemu-system-ppc64 -m 4G -machine powernv9,accel=tcg \ -smp 2,sockets=2,cores=1,threads=1 dev: pnv-phb4, id "" index = 5 (0x5) chip-id = 1 (0x1) version = 704374636546 (0xa400000002) device-id = 1217 (0x4c1) x-config-reg-migration-enabled = true bypass-iommu = false bus: pnv-phb4-root.11 type pnv-phb4-root dev: pnv-phb4-root-port, id "" (...) dev: pnv-phb4, id "" index = 0 (0x0) chip-id = 1 (0x1) version = 704374636546 (0xa400000002) device-id = 1217 (0x4c1) x-config-reg-migration-enabled = true bypass-iommu = false bus: pnv-phb4-root.6 type pnv-phb4-root dev: pnv-phb4-root-port, id "" (..) dev: pnv-phb4, id "" index = 5 (0x5) chip-id = 0 (0x0) version = 704374636546 (0xa400000002) device-id = 1217 (0x4c1) x-config-reg-migration-enabled = true bypass-iommu = false bus: pnv-phb4-root.5 type pnv-phb4-root dev: pnv-phb4-root-port, id "" (...) dev: pnv-phb4, id "" index = 0 (0x0) chip-id = 0 (0x0) version = 704374636546 (0xa400000002) device-id = 1217 (0x4c1) x-config-reg-migration-enabled = true bypass-iommu = false bus: pnv-phb4-root.0 type pnv-phb4-root dev: pnv-phb4-root-port, id "" Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220110143346.455901-11-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- include/hw/pci-host/pnv_phb4.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -XXX,XX +XXX,XX @@ typedef struct PnvPhb4DMASpace { /* * PHB4 PCIe Root port */ -#define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root-bus" +#define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root" #define TYPE_PNV_PHB4_ROOT_PORT "pnv-phb4-root-port" typedef struct PnvPHB4RootPort { -- 2.31.1 From: Daniel Henrique Barboza <danielhb413@gmail.com> The logic inside pnv_pec_phb_offset() will be useful in the next patch to determine the stack that should contain a PHB4 device. Move the function to pnv_phb4.c and make it public since there's no pnv_phb4_pec.h header. While we're at it, add 'stack_index' as a parameter and make the function return 'phb-id' directly. And rename it to pnv_phb4_pec_get_phb_id() to be even clearer about the function intent. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220110143346.455901-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- include/hw/pci-host/pnv_phb4.h | 2 ++ hw/pci-host/pnv_phb4.c | 17 +++++++++++++++++ hw/pci-host/pnv_phb4_pec.c | 15 +-------------- 3 files changed, 20 insertions(+), 14 deletions(-) diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -XXX,XX +XXX,XX @@ #include "hw/ppc/xive.h" #include "qom/object.h" +typedef struct PnvPhb4PecState PnvPhb4PecState; typedef struct PnvPhb4PecStack PnvPhb4PecStack; typedef struct PnvPHB4 PnvPHB4; typedef struct PnvChip PnvChip; @@ -XXX,XX +XXX,XX @@ struct PnvPHB4 { void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon); void pnv_phb4_update_regions(PnvPhb4PecStack *stack); +int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index); extern const MemoryRegionOps pnv_phb4_xscom_ops; /* diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -XXX,XX +XXX,XX @@ static const TypeInfo pnv_phb4_iommu_memory_region_info = { .class_init = pnv_phb4_iommu_memory_region_class_init, }; +/* + * Return the index/phb-id of a PHB4 that belongs to a + * pec->stacks[stack_index] stack. + */ +int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index) +{ + PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); + int index = pec->index; + int offset = 0; + + while (index--) { + offset += pecc->num_stacks[index]; + } + + return offset + stack_index; +} + /* * MSI/MSIX memory region implementation. * The handler handles both MSI and MSIX. diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -XXX,XX +XXX,XX @@ static void pnv_pec_instance_init(Object *obj) } } -static int pnv_pec_phb_offset(PnvPhb4PecState *pec) -{ - PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); - int index = pec->index; - int offset = 0; - - while (index--) { - offset += pecc->num_stacks[index]; - } - - return offset; -} - static void pnv_pec_realize(DeviceState *dev, Error **errp) { PnvPhb4PecState *pec = PNV_PHB4_PEC(dev); @@ -XXX,XX +XXX,XX @@ static void pnv_pec_realize(DeviceState *dev, Error **errp) for (i = 0; i < pec->num_stacks; i++) { PnvPhb4PecStack *stack = &pec->stacks[i]; Object *stk_obj = OBJECT(stack); - int phb_id = pnv_pec_phb_offset(pec) + i; + int phb_id = pnv_phb4_pec_get_phb_id(pec, i); object_property_set_int(stk_obj, "stack-no", i, &error_abort); object_property_set_int(stk_obj, "phb-id", phb_id, &error_abort); -- 2.31.1 From: Daniel Henrique Barboza <danielhb413@gmail.com> Relying on stack->phb to write the xscom DT of the PEC is something that we won't be able to do with user creatable pnv-phb4 devices. Hopefully, this can be done by using pnv_phb4_pec_get_phb_id(), which is already used by pnv_pec_realize() to set the phb-id of the stack. Use the same idea in pnv_pec_dt_xscom() to write ibm,phb-index without the need to accessing stack->phb, since stack->phb is not granted to be != NULL when user creatable phbs are introduced. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220110143346.455901-4-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/pci-host/pnv_phb4_pec.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -XXX,XX +XXX,XX @@ static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt, pecc->compat_size))); for (i = 0; i < pec->num_stacks; i++) { - PnvPhb4PecStack *stack = &pec->stacks[i]; - PnvPHB4 *phb = &stack->phb; + int phb_id = pnv_phb4_pec_get_phb_id(pec, i); int stk_offset; name = g_strdup_printf("stack@%x", i); @@ -XXX,XX +XXX,XX @@ static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt, _FDT((fdt_setprop(fdt, stk_offset, "compatible", pecc->stk_compat, pecc->stk_compat_size))); _FDT((fdt_setprop_cell(fdt, stk_offset, "reg", i))); - _FDT((fdt_setprop_cell(fdt, stk_offset, "ibm,phb-index", phb->phb_id))); + _FDT((fdt_setprop_cell(fdt, stk_offset, "ibm,phb-index", phb_id))); } return 0; -- 2.31.1 From: Daniel Henrique Barboza <danielhb413@gmail.com> Moving all phb4 properties setup to stk_realize() keeps this logic in a single place instead of having it scattered between stk_realize() and pec_realize(). 'phb->index' can be retrieved using stack->stack_no and pnv_phb4_pec_get_phb_id(), deprecating the use of 'phb-id' alias that was being used for this purpose in pec_realize(). Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220111131027.599784-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/pci-host/pnv_phb4_pec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -XXX,XX +XXX,XX @@ static void pnv_pec_realize(DeviceState *dev, Error **errp) for (i = 0; i < pec->num_stacks; i++) { PnvPhb4PecStack *stack = &pec->stacks[i]; Object *stk_obj = OBJECT(stack); - int phb_id = pnv_phb4_pec_get_phb_id(pec, i); object_property_set_int(stk_obj, "stack-no", i, &error_abort); - object_property_set_int(stk_obj, "phb-id", phb_id, &error_abort); object_property_set_link(stk_obj, "pec", OBJECT(pec), &error_abort); if (!qdev_realize(DEVICE(stk_obj), NULL, errp)) { return; @@ -XXX,XX +XXX,XX @@ static void pnv_pec_stk_instance_init(Object *obj) PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(obj); object_initialize_child(obj, "phb", &stack->phb, TYPE_PNV_PHB4); - object_property_add_alias(obj, "phb-id", OBJECT(&stack->phb), "index"); } static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) PnvPhb4PecState *pec = stack->pec; PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); PnvChip *chip = pec->chip; + int phb_id = pnv_phb4_pec_get_phb_id(pec, stack->stack_no); uint32_t pec_nest_base; uint32_t pec_pci_base; char name[64]; @@ -XXX,XX +XXX,XX @@ static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) object_property_set_int(OBJECT(&stack->phb), "chip-id", pec->chip_id, &error_fatal); + object_property_set_int(OBJECT(&stack->phb), "index", phb_id, + &error_fatal); object_property_set_int(OBJECT(&stack->phb), "version", pecc->version, &error_fatal); object_property_set_link(OBJECT(&stack->phb), "stack", OBJECT(stack), -- 2.31.1 From: Daniel Henrique Barboza <danielhb413@gmail.com> The 'stack->phb_regs_mr' PHB4 passthrough XSCOM initialization relies on 'stack->phb' being not NULL. Moving 'stack->phb_regs_mr' region_init() and add_subregion() to phb4_realize() time is a natural thing to do since it's strictly PHB related. The remaining XSCOM initialization is also related to 'stack->phb' but in a different manner. For instance, 'stack->nest_regs_mr' MemoryRegionOps, 'pnv_pec_stk_nest_xscom_ops', uses pnv_pec_stk_nest_xscom_write() as a write callback. When trying to write the PEC_NEST_STK_BAR_EN reg, pnv_pec_stk_update_map() is called. Inside this function, pnv_phb4_update_regions() is called twice. This function uses 'stack->phb' to manipulate memory regions of the phb. This is not a problem now but, when enabling user creatable phb4s, a stack that doesn't have an associated phb (i.e. stack->phb = NULL) it will cause a SIGINT during boot in pnv_phb4_update_regions(). All this can be avoided if all XSCOM realize is moved to phb4_realize(), when we have certainty about the existence of 'stack->phb'. A lot of code was moved from pnv_phb4_pec.c to pnv_phb4.c due to static constant and variables being used but the cleaner logic is worth the trouble. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220111131027.599784-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/pci-host/pnv_phb4.c | 304 +++++++++++++++++++++++++++++++++++++ hw/pci-host/pnv_phb4_pec.c | 292 ----------------------------------- 2 files changed, 304 insertions(+), 292 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -XXX,XX +XXX,XX @@ qemu_log_mask(LOG_GUEST_ERROR, "phb4[%d:%d]: " fmt "\n", \ (phb)->chip_id, (phb)->phb_id, ## __VA_ARGS__) +#define phb_pec_error(pec, fmt, ...) \ + qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n", \ + (pec)->chip_id, (pec)->index, ## __VA_ARGS__) + /* * QEMU version of the GETFIELD/SETFIELD macros * @@ -XXX,XX +XXX,XX @@ const MemoryRegionOps pnv_phb4_xscom_ops = { .endianness = DEVICE_BIG_ENDIAN, }; +static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr, + unsigned size) +{ + PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque); + uint32_t reg = addr >> 3; + + /* TODO: add list of allowed registers and error out if not */ + return stack->nest_regs[reg]; +} + +static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack) +{ + PnvPhb4PecState *pec = stack->pec; + MemoryRegion *sysmem = get_system_memory(); + uint64_t bar_en = stack->nest_regs[PEC_NEST_STK_BAR_EN]; + uint64_t bar, mask, size; + char name[64]; + + /* + * NOTE: This will really not work well if those are remapped + * after the PHB has created its sub regions. We could do better + * if we had a way to resize regions but we don't really care + * that much in practice as the stuff below really only happens + * once early during boot + */ + + /* Handle unmaps */ + if (memory_region_is_mapped(&stack->mmbar0) && + !(bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) { + memory_region_del_subregion(sysmem, &stack->mmbar0); + } + if (memory_region_is_mapped(&stack->mmbar1) && + !(bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) { + memory_region_del_subregion(sysmem, &stack->mmbar1); + } + if (memory_region_is_mapped(&stack->phbbar) && + !(bar_en & PEC_NEST_STK_BAR_EN_PHB)) { + memory_region_del_subregion(sysmem, &stack->phbbar); + } + if (memory_region_is_mapped(&stack->intbar) && + !(bar_en & PEC_NEST_STK_BAR_EN_INT)) { + memory_region_del_subregion(sysmem, &stack->intbar); + } + + /* Update PHB */ + pnv_phb4_update_regions(stack); + + /* Handle maps */ + if (!memory_region_is_mapped(&stack->mmbar0) && + (bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) { + bar = stack->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8; + mask = stack->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK]; + size = ((~mask) >> 8) + 1; + snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio0", + pec->chip_id, pec->index, stack->stack_no); + memory_region_init(&stack->mmbar0, OBJECT(stack), name, size); + memory_region_add_subregion(sysmem, bar, &stack->mmbar0); + stack->mmio0_base = bar; + stack->mmio0_size = size; + } + if (!memory_region_is_mapped(&stack->mmbar1) && + (bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) { + bar = stack->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8; + mask = stack->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK]; + size = ((~mask) >> 8) + 1; + snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio1", + pec->chip_id, pec->index, stack->stack_no); + memory_region_init(&stack->mmbar1, OBJECT(stack), name, size); + memory_region_add_subregion(sysmem, bar, &stack->mmbar1); + stack->mmio1_base = bar; + stack->mmio1_size = size; + } + if (!memory_region_is_mapped(&stack->phbbar) && + (bar_en & PEC_NEST_STK_BAR_EN_PHB)) { + bar = stack->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8; + size = PNV_PHB4_NUM_REGS << 3; + snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-phb", + pec->chip_id, pec->index, stack->stack_no); + memory_region_init(&stack->phbbar, OBJECT(stack), name, size); + memory_region_add_subregion(sysmem, bar, &stack->phbbar); + } + if (!memory_region_is_mapped(&stack->intbar) && + (bar_en & PEC_NEST_STK_BAR_EN_INT)) { + bar = stack->nest_regs[PEC_NEST_STK_INT_BAR] >> 8; + size = PNV_PHB4_MAX_INTs << 16; + snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-int", + stack->pec->chip_id, stack->pec->index, stack->stack_no); + memory_region_init(&stack->intbar, OBJECT(stack), name, size); + memory_region_add_subregion(sysmem, bar, &stack->intbar); + } + + /* Update PHB */ + pnv_phb4_update_regions(stack); +} + +static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque); + PnvPhb4PecState *pec = stack->pec; + uint32_t reg = addr >> 3; + + switch (reg) { + case PEC_NEST_STK_PCI_NEST_FIR: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_CLR: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_SET: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |= val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_MSK: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_MSKC: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &= val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_MSKS: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] |= val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_ACT0: + case PEC_NEST_STK_PCI_NEST_FIR_ACT1: + stack->nest_regs[reg] = val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_WOF: + stack->nest_regs[reg] = 0; + break; + case PEC_NEST_STK_ERR_REPORT_0: + case PEC_NEST_STK_ERR_REPORT_1: + case PEC_NEST_STK_PBCQ_GNRL_STATUS: + /* Flag error ? */ + break; + case PEC_NEST_STK_PBCQ_MODE: + stack->nest_regs[reg] = val & 0xff00000000000000ull; + break; + case PEC_NEST_STK_MMIO_BAR0: + case PEC_NEST_STK_MMIO_BAR0_MASK: + case PEC_NEST_STK_MMIO_BAR1: + case PEC_NEST_STK_MMIO_BAR1_MASK: + if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & + (PEC_NEST_STK_BAR_EN_MMIO0 | + PEC_NEST_STK_BAR_EN_MMIO1)) { + phb_pec_error(pec, "Changing enabled BAR unsupported\n"); + } + stack->nest_regs[reg] = val & 0xffffffffff000000ull; + break; + case PEC_NEST_STK_PHB_REGS_BAR: + if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PHB) { + phb_pec_error(pec, "Changing enabled BAR unsupported\n"); + } + stack->nest_regs[reg] = val & 0xffffffffffc00000ull; + break; + case PEC_NEST_STK_INT_BAR: + if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_INT) { + phb_pec_error(pec, "Changing enabled BAR unsupported\n"); + } + stack->nest_regs[reg] = val & 0xfffffff000000000ull; + break; + case PEC_NEST_STK_BAR_EN: + stack->nest_regs[reg] = val & 0xf000000000000000ull; + pnv_pec_stk_update_map(stack); + break; + case PEC_NEST_STK_DATA_FRZ_TYPE: + case PEC_NEST_STK_PBCQ_TUN_BAR: + /* Not used for now */ + stack->nest_regs[reg] = val; + break; + default: + qemu_log_mask(LOG_UNIMP, "phb4_pec: nest_xscom_write 0x%"HWADDR_PRIx + "=%"PRIx64"\n", addr, val); + } +} + +static const MemoryRegionOps pnv_pec_stk_nest_xscom_ops = { + .read = pnv_pec_stk_nest_xscom_read, + .write = pnv_pec_stk_nest_xscom_write, + .valid.min_access_size = 8, + .valid.max_access_size = 8, + .impl.min_access_size = 8, + .impl.max_access_size = 8, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, hwaddr addr, + unsigned size) +{ + PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque); + uint32_t reg = addr >> 3; + + /* TODO: add list of allowed registers and error out if not */ + return stack->pci_regs[reg]; +} + +static void pnv_pec_stk_pci_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque); + uint32_t reg = addr >> 3; + + switch (reg) { + case PEC_PCI_STK_PCI_FIR: + stack->nest_regs[reg] = val; + break; + case PEC_PCI_STK_PCI_FIR_CLR: + stack->nest_regs[PEC_PCI_STK_PCI_FIR] &= val; + break; + case PEC_PCI_STK_PCI_FIR_SET: + stack->nest_regs[PEC_PCI_STK_PCI_FIR] |= val; + break; + case PEC_PCI_STK_PCI_FIR_MSK: + stack->nest_regs[reg] = val; + break; + case PEC_PCI_STK_PCI_FIR_MSKC: + stack->nest_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val; + break; + case PEC_PCI_STK_PCI_FIR_MSKS: + stack->nest_regs[PEC_PCI_STK_PCI_FIR_MSK] |= val; + break; + case PEC_PCI_STK_PCI_FIR_ACT0: + case PEC_PCI_STK_PCI_FIR_ACT1: + stack->nest_regs[reg] = val; + break; + case PEC_PCI_STK_PCI_FIR_WOF: + stack->nest_regs[reg] = 0; + break; + case PEC_PCI_STK_ETU_RESET: + stack->nest_regs[reg] = val & 0x8000000000000000ull; + /* TODO: Implement reset */ + break; + case PEC_PCI_STK_PBAIB_ERR_REPORT: + break; + case PEC_PCI_STK_PBAIB_TX_CMD_CRED: + case PEC_PCI_STK_PBAIB_TX_DAT_CRED: + stack->nest_regs[reg] = val; + break; + default: + qemu_log_mask(LOG_UNIMP, "phb4_pec_stk: pci_xscom_write 0x%"HWADDR_PRIx + "=%"PRIx64"\n", addr, val); + } +} + +static const MemoryRegionOps pnv_pec_stk_pci_xscom_ops = { + .read = pnv_pec_stk_pci_xscom_read, + .write = pnv_pec_stk_pci_xscom_write, + .valid.min_access_size = 8, + .valid.max_access_size = 8, + .impl.min_access_size = 8, + .impl.max_access_size = 8, + .endianness = DEVICE_BIG_ENDIAN, +}; + static int pnv_phb4_map_irq(PCIDevice *pci_dev, int irq_num) { /* Check that out properly ... */ @@ -XXX,XX +XXX,XX @@ static AddressSpace *pnv_phb4_dma_iommu(PCIBus *bus, void *opaque, int devfn) return &ds->dma_as; } +static void pnv_phb4_xscom_realize(PnvPHB4 *phb) +{ + PnvPhb4PecStack *stack = phb->stack; + PnvPhb4PecState *pec = stack->pec; + PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); + uint32_t pec_nest_base; + uint32_t pec_pci_base; + char name[64]; + + assert(pec); + + /* Initialize the XSCOM regions for the stack registers */ + snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest-stack-%d", + pec->chip_id, pec->index, stack->stack_no); + pnv_xscom_region_init(&stack->nest_regs_mr, OBJECT(stack), + &pnv_pec_stk_nest_xscom_ops, stack, name, + PHB4_PEC_NEST_STK_REGS_COUNT); + + snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d", + pec->chip_id, pec->index, stack->stack_no); + pnv_xscom_region_init(&stack->pci_regs_mr, OBJECT(stack), + &pnv_pec_stk_pci_xscom_ops, stack, name, + PHB4_PEC_PCI_STK_REGS_COUNT); + + /* PHB pass-through */ + snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d-phb", + pec->chip_id, pec->index, stack->stack_no); + pnv_xscom_region_init(&stack->phb_regs_mr, OBJECT(phb), + &pnv_phb4_xscom_ops, phb, name, 0x40); + + pec_nest_base = pecc->xscom_nest_base(pec); + pec_pci_base = pecc->xscom_pci_base(pec); + + /* Populate the XSCOM address space. */ + pnv_xscom_add_subregion(pec->chip, + pec_nest_base + 0x40 * (stack->stack_no + 1), + &stack->nest_regs_mr); + pnv_xscom_add_subregion(pec->chip, + pec_pci_base + 0x40 * (stack->stack_no + 1), + &stack->pci_regs_mr); + pnv_xscom_add_subregion(pec->chip, + pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + + 0x40 * stack->stack_no, + &stack->phb_regs_mr); +} + static void pnv_phb4_instance_init(Object *obj) { PnvPHB4 *phb = PNV_PHB4(obj); @@ -XXX,XX +XXX,XX @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp) pnv_phb4_update_xsrc(phb); phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs); + + pnv_phb4_xscom_realize(phb); } static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge, diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps pnv_pec_pci_xscom_ops = { .endianness = DEVICE_BIG_ENDIAN, }; -static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr, - unsigned size) -{ - PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque); - uint32_t reg = addr >> 3; - - /* TODO: add list of allowed registers and error out if not */ - return stack->nest_regs[reg]; -} - -static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack) -{ - PnvPhb4PecState *pec = stack->pec; - MemoryRegion *sysmem = get_system_memory(); - uint64_t bar_en = stack->nest_regs[PEC_NEST_STK_BAR_EN]; - uint64_t bar, mask, size; - char name[64]; - - /* - * NOTE: This will really not work well if those are remapped - * after the PHB has created its sub regions. We could do better - * if we had a way to resize regions but we don't really care - * that much in practice as the stuff below really only happens - * once early during boot - */ - - /* Handle unmaps */ - if (memory_region_is_mapped(&stack->mmbar0) && - !(bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) { - memory_region_del_subregion(sysmem, &stack->mmbar0); - } - if (memory_region_is_mapped(&stack->mmbar1) && - !(bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) { - memory_region_del_subregion(sysmem, &stack->mmbar1); - } - if (memory_region_is_mapped(&stack->phbbar) && - !(bar_en & PEC_NEST_STK_BAR_EN_PHB)) { - memory_region_del_subregion(sysmem, &stack->phbbar); - } - if (memory_region_is_mapped(&stack->intbar) && - !(bar_en & PEC_NEST_STK_BAR_EN_INT)) { - memory_region_del_subregion(sysmem, &stack->intbar); - } - - /* Update PHB */ - pnv_phb4_update_regions(stack); - - /* Handle maps */ - if (!memory_region_is_mapped(&stack->mmbar0) && - (bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) { - bar = stack->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8; - mask = stack->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK]; - size = ((~mask) >> 8) + 1; - snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio0", - pec->chip_id, pec->index, stack->stack_no); - memory_region_init(&stack->mmbar0, OBJECT(stack), name, size); - memory_region_add_subregion(sysmem, bar, &stack->mmbar0); - stack->mmio0_base = bar; - stack->mmio0_size = size; - } - if (!memory_region_is_mapped(&stack->mmbar1) && - (bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) { - bar = stack->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8; - mask = stack->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK]; - size = ((~mask) >> 8) + 1; - snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio1", - pec->chip_id, pec->index, stack->stack_no); - memory_region_init(&stack->mmbar1, OBJECT(stack), name, size); - memory_region_add_subregion(sysmem, bar, &stack->mmbar1); - stack->mmio1_base = bar; - stack->mmio1_size = size; - } - if (!memory_region_is_mapped(&stack->phbbar) && - (bar_en & PEC_NEST_STK_BAR_EN_PHB)) { - bar = stack->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8; - size = PNV_PHB4_NUM_REGS << 3; - snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-phb", - pec->chip_id, pec->index, stack->stack_no); - memory_region_init(&stack->phbbar, OBJECT(stack), name, size); - memory_region_add_subregion(sysmem, bar, &stack->phbbar); - } - if (!memory_region_is_mapped(&stack->intbar) && - (bar_en & PEC_NEST_STK_BAR_EN_INT)) { - bar = stack->nest_regs[PEC_NEST_STK_INT_BAR] >> 8; - size = PNV_PHB4_MAX_INTs << 16; - snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-int", - stack->pec->chip_id, stack->pec->index, stack->stack_no); - memory_region_init(&stack->intbar, OBJECT(stack), name, size); - memory_region_add_subregion(sysmem, bar, &stack->intbar); - } - - /* Update PHB */ - pnv_phb4_update_regions(stack); -} - -static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque); - PnvPhb4PecState *pec = stack->pec; - uint32_t reg = addr >> 3; - - switch (reg) { - case PEC_NEST_STK_PCI_NEST_FIR: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_CLR: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_SET: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |= val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_MSK: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_MSKC: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &= val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_MSKS: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] |= val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_ACT0: - case PEC_NEST_STK_PCI_NEST_FIR_ACT1: - stack->nest_regs[reg] = val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_WOF: - stack->nest_regs[reg] = 0; - break; - case PEC_NEST_STK_ERR_REPORT_0: - case PEC_NEST_STK_ERR_REPORT_1: - case PEC_NEST_STK_PBCQ_GNRL_STATUS: - /* Flag error ? */ - break; - case PEC_NEST_STK_PBCQ_MODE: - stack->nest_regs[reg] = val & 0xff00000000000000ull; - break; - case PEC_NEST_STK_MMIO_BAR0: - case PEC_NEST_STK_MMIO_BAR0_MASK: - case PEC_NEST_STK_MMIO_BAR1: - case PEC_NEST_STK_MMIO_BAR1_MASK: - if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & - (PEC_NEST_STK_BAR_EN_MMIO0 | - PEC_NEST_STK_BAR_EN_MMIO1)) { - phb_pec_error(pec, "Changing enabled BAR unsupported\n"); - } - stack->nest_regs[reg] = val & 0xffffffffff000000ull; - break; - case PEC_NEST_STK_PHB_REGS_BAR: - if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PHB) { - phb_pec_error(pec, "Changing enabled BAR unsupported\n"); - } - stack->nest_regs[reg] = val & 0xffffffffffc00000ull; - break; - case PEC_NEST_STK_INT_BAR: - if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_INT) { - phb_pec_error(pec, "Changing enabled BAR unsupported\n"); - } - stack->nest_regs[reg] = val & 0xfffffff000000000ull; - break; - case PEC_NEST_STK_BAR_EN: - stack->nest_regs[reg] = val & 0xf000000000000000ull; - pnv_pec_stk_update_map(stack); - break; - case PEC_NEST_STK_DATA_FRZ_TYPE: - case PEC_NEST_STK_PBCQ_TUN_BAR: - /* Not used for now */ - stack->nest_regs[reg] = val; - break; - default: - qemu_log_mask(LOG_UNIMP, "phb4_pec: nest_xscom_write 0x%"HWADDR_PRIx - "=%"PRIx64"\n", addr, val); - } -} - -static const MemoryRegionOps pnv_pec_stk_nest_xscom_ops = { - .read = pnv_pec_stk_nest_xscom_read, - .write = pnv_pec_stk_nest_xscom_write, - .valid.min_access_size = 8, - .valid.max_access_size = 8, - .impl.min_access_size = 8, - .impl.max_access_size = 8, - .endianness = DEVICE_BIG_ENDIAN, -}; - -static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, hwaddr addr, - unsigned size) -{ - PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque); - uint32_t reg = addr >> 3; - - /* TODO: add list of allowed registers and error out if not */ - return stack->pci_regs[reg]; -} - -static void pnv_pec_stk_pci_xscom_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque); - uint32_t reg = addr >> 3; - - switch (reg) { - case PEC_PCI_STK_PCI_FIR: - stack->nest_regs[reg] = val; - break; - case PEC_PCI_STK_PCI_FIR_CLR: - stack->nest_regs[PEC_PCI_STK_PCI_FIR] &= val; - break; - case PEC_PCI_STK_PCI_FIR_SET: - stack->nest_regs[PEC_PCI_STK_PCI_FIR] |= val; - break; - case PEC_PCI_STK_PCI_FIR_MSK: - stack->nest_regs[reg] = val; - break; - case PEC_PCI_STK_PCI_FIR_MSKC: - stack->nest_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val; - break; - case PEC_PCI_STK_PCI_FIR_MSKS: - stack->nest_regs[PEC_PCI_STK_PCI_FIR_MSK] |= val; - break; - case PEC_PCI_STK_PCI_FIR_ACT0: - case PEC_PCI_STK_PCI_FIR_ACT1: - stack->nest_regs[reg] = val; - break; - case PEC_PCI_STK_PCI_FIR_WOF: - stack->nest_regs[reg] = 0; - break; - case PEC_PCI_STK_ETU_RESET: - stack->nest_regs[reg] = val & 0x8000000000000000ull; - /* TODO: Implement reset */ - break; - case PEC_PCI_STK_PBAIB_ERR_REPORT: - break; - case PEC_PCI_STK_PBAIB_TX_CMD_CRED: - case PEC_PCI_STK_PBAIB_TX_DAT_CRED: - stack->nest_regs[reg] = val; - break; - default: - qemu_log_mask(LOG_UNIMP, "phb4_pec_stk: pci_xscom_write 0x%"HWADDR_PRIx - "=%"PRIx64"\n", addr, val); - } -} - -static const MemoryRegionOps pnv_pec_stk_pci_xscom_ops = { - .read = pnv_pec_stk_pci_xscom_read, - .write = pnv_pec_stk_pci_xscom_write, - .valid.min_access_size = 8, - .valid.max_access_size = 8, - .impl.min_access_size = 8, - .impl.max_access_size = 8, - .endianness = DEVICE_BIG_ENDIAN, -}; - static void pnv_pec_instance_init(Object *obj) { PnvPhb4PecState *pec = PNV_PHB4_PEC(obj); @@ -XXX,XX +XXX,XX @@ static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(dev); PnvPhb4PecState *pec = stack->pec; PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); - PnvChip *chip = pec->chip; int phb_id = pnv_phb4_pec_get_phb_id(pec, stack->stack_no); - uint32_t pec_nest_base; - uint32_t pec_pci_base; - char name[64]; - - assert(pec); - - /* Initialize the XSCOM regions for the stack registers */ - snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest-stack-%d", - pec->chip_id, pec->index, stack->stack_no); - pnv_xscom_region_init(&stack->nest_regs_mr, OBJECT(stack), - &pnv_pec_stk_nest_xscom_ops, stack, name, - PHB4_PEC_NEST_STK_REGS_COUNT); - - snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d", - pec->chip_id, pec->index, stack->stack_no); - pnv_xscom_region_init(&stack->pci_regs_mr, OBJECT(stack), - &pnv_pec_stk_pci_xscom_ops, stack, name, - PHB4_PEC_PCI_STK_REGS_COUNT); - - /* PHB pass-through */ - snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d-phb", - pec->chip_id, pec->index, stack->stack_no); - pnv_xscom_region_init(&stack->phb_regs_mr, OBJECT(&stack->phb), - &pnv_phb4_xscom_ops, &stack->phb, name, 0x40); object_property_set_int(OBJECT(&stack->phb), "chip-id", pec->chip_id, &error_fatal); @@ -XXX,XX +XXX,XX @@ static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&stack->phb), errp)) { return; } - - pec_nest_base = pecc->xscom_nest_base(pec); - pec_pci_base = pecc->xscom_pci_base(pec); - - /* Populate the XSCOM address space. */ - pnv_xscom_add_subregion(chip, - pec_nest_base + 0x40 * (stack->stack_no + 1), - &stack->nest_regs_mr); - pnv_xscom_add_subregion(chip, - pec_pci_base + 0x40 * (stack->stack_no + 1), - &stack->pci_regs_mr); - pnv_xscom_add_subregion(chip, - pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + - 0x40 * stack->stack_no, - &stack->phb_regs_mr); } static Property pnv_pec_stk_properties[] = { -- 2.31.1 From: Daniel Henrique Barboza <danielhb413@gmail.com> At this moment, stack->phb is the plain PnvPHB4 device itself instead of a pointer to the device. This will present a problem when adding user creatable devices because we can't deal with this struct and the realize() callback from the user creatable device. We can't get rid of this attribute, similar to what we did when enabling pnv-phb3 user creatable devices, because pnv_phb4_update_regions() needs to access stack->phb to do its job. This function is called twice in pnv_pec_stk_update_map(), which is one of the nested xscom write callbacks (via pnv_pec_stk_nest_xscom_write()). In fact, pnv_pec_stk_update_map() code comment is explicit about how the order of the unmap/map operations relates with the PHB subregions. All of this indicates that this code is tied together in a way that we either go on a crusade, featuring lots of refactories and redesign and considerable pain, to decouple stack and phb mapping, or we allow stack update_map operations to access the associated PHB as it is today even after introducing pnv-phb4 user devices. This patch chooses the latter. Instead of getting rid of stack->phb, turn it into a PHB pointer. This will allow us to assign an user created PHB to an existing stack later. In this process, pnv_pec_stk_instance_init() is removed because stack->phb is being initialized in stk_realize() instead. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220111131027.599784-4-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- include/hw/pci-host/pnv_phb4.h | 7 +++++-- hw/pci-host/pnv_phb4.c | 2 +- hw/pci-host/pnv_phb4_pec.c | 20 +++++++------------- 3 files changed, 13 insertions(+), 16 deletions(-) diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -XXX,XX +XXX,XX @@ struct PnvPhb4PecStack { /* The owner PEC */ PnvPhb4PecState *pec; - /* The actual PHB */ - PnvPHB4 phb; + /* + * PHB4 pointer. pnv_phb4_update_regions() needs to access + * the PHB4 via a PnvPhb4PecStack pointer. + */ + PnvPHB4 *phb; }; struct PnvPhb4PecState { diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -XXX,XX +XXX,XX @@ type_init(pnv_phb4_register_types); void pnv_phb4_update_regions(PnvPhb4PecStack *stack) { - PnvPHB4 *phb = &stack->phb; + PnvPHB4 *phb = stack->phb; /* Unmap first always */ if (memory_region_is_mapped(&phb->mr_regs)) { diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -XXX,XX +XXX,XX @@ static const TypeInfo pnv_pec_type_info = { } }; -static void pnv_pec_stk_instance_init(Object *obj) -{ - PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(obj); - - object_initialize_child(obj, "phb", &stack->phb, TYPE_PNV_PHB4); -} - static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) { PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(dev); @@ -XXX,XX +XXX,XX @@ static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); int phb_id = pnv_phb4_pec_get_phb_id(pec, stack->stack_no); - object_property_set_int(OBJECT(&stack->phb), "chip-id", pec->chip_id, + stack->phb = PNV_PHB4(qdev_new(TYPE_PNV_PHB4)); + + object_property_set_int(OBJECT(stack->phb), "chip-id", pec->chip_id, &error_fatal); - object_property_set_int(OBJECT(&stack->phb), "index", phb_id, + object_property_set_int(OBJECT(stack->phb), "index", phb_id, &error_fatal); - object_property_set_int(OBJECT(&stack->phb), "version", pecc->version, + object_property_set_int(OBJECT(stack->phb), "version", pecc->version, &error_fatal); - object_property_set_link(OBJECT(&stack->phb), "stack", OBJECT(stack), + object_property_set_link(OBJECT(stack->phb), "stack", OBJECT(stack), &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(&stack->phb), errp)) { + if (!sysbus_realize(SYS_BUS_DEVICE(stack->phb), errp)) { return; } } @@ -XXX,XX +XXX,XX @@ static const TypeInfo pnv_pec_stk_type_info = { .name = TYPE_PNV_PHB4_PEC_STACK, .parent = TYPE_DEVICE, .instance_size = sizeof(PnvPhb4PecStack), - .instance_init = pnv_pec_stk_instance_init, .class_init = pnv_pec_stk_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_PNV_XSCOM_INTERFACE }, -- 2.31.1 From: Daniel Henrique Barboza <danielhb413@gmail.com> This patch introduces pnv-phb4 user creatable devices that are created in a similar manner as pnv-phb3 devices, allowing the user to interact with the PHBs directly instead of creating PCI Express Controllers that will create a certain amount of PHBs per controller index. We accomplish this by doing the following: - add a pnv_phb4_get_stack() helper to retrieve which stack an user created phb4 would occupy; - when dealing with an user created pnv-phb4 (detected by checking if phb->stack is NULL at the start of phb4_realize()), retrieve its stack and initialize its properties as done in stk_realize(); - use 'defaults_enabled()' in stk_realize() to avoid creating and initializing a 'stack->phb' qdev that might be overwritten by an user created pnv-phb4 device. This process is wrapped into a new helper called pnv_pec_stk_default_phb_realize(). Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220111131027.599784-5-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/pci-host/pnv_phb4.c | 74 ++++++++++++++++++++++++++++++++++++-- hw/pci-host/pnv_phb4_pec.c | 17 +++++++-- hw/ppc/pnv.c | 2 ++ 3 files changed, 89 insertions(+), 4 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -XXX,XX +XXX,XX @@ static void pnv_phb4_instance_init(Object *obj) object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE); } +static PnvPhb4PecStack *pnv_phb4_get_stack(PnvChip *chip, PnvPHB4 *phb, + Error **errp) +{ + Pnv9Chip *chip9 = PNV9_CHIP(chip); + int chip_id = phb->chip_id; + int index = phb->phb_id; + int i, j; + + for (i = 0; i < chip->num_pecs; i++) { + /* + * For each PEC, check the amount of stacks it supports + * and see if the given phb4 index matches a stack. + */ + PnvPhb4PecState *pec = &chip9->pecs[i]; + + for (j = 0; j < pec->num_stacks; j++) { + if (index == pnv_phb4_pec_get_phb_id(pec, j)) { + return &pec->stacks[j]; + } + } + } + + error_setg(errp, + "pnv-phb4 chip-id %d index %d didn't match any existing PEC", + chip_id, index); + + return NULL; +} + static void pnv_phb4_realize(DeviceState *dev, Error **errp) { PnvPHB4 *phb = PNV_PHB4(dev); PCIHostState *pci = PCI_HOST_BRIDGE(dev); XiveSource *xsrc = &phb->xsrc; + Error *local_err = NULL; int nr_irqs; char name[32]; - assert(phb->stack); + /* User created PHB */ + if (!phb->stack) { + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); + PnvChip *chip = pnv_get_chip(pnv, phb->chip_id); + PnvPhb4PecClass *pecc; + BusState *s; + + if (!chip) { + error_setg(errp, "invalid chip id: %d", phb->chip_id); + return; + } + + phb->stack = pnv_phb4_get_stack(chip, phb, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + /* All other phb properties but 'version' are already set */ + pecc = PNV_PHB4_PEC_GET_CLASS(phb->stack->pec); + object_property_set_int(OBJECT(phb), "version", pecc->version, + &error_fatal); + + /* + * Assign stack->phb since pnv_phb4_update_regions() uses it + * to access the phb. + */ + phb->stack->phb = phb; + + /* + * Reparent user created devices to the chip to build + * correctly the device tree. + */ + pnv_chip_parent_fixup(chip, OBJECT(phb), phb->phb_id); + + s = qdev_get_parent_bus(DEVICE(chip)); + if (!qdev_set_parent_bus(DEVICE(phb), s, &local_err)) { + error_propagate(errp, local_err); + return; + } + } /* Set the "big_phb" flag */ phb->big_phb = phb->phb_id == 0 || phb->phb_id == 3; @@ -XXX,XX +XXX,XX @@ static void pnv_phb4_class_init(ObjectClass *klass, void *data) dc->realize = pnv_phb4_realize; device_class_set_props(dc, pnv_phb4_properties); set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->user_creatable = false; + dc->user_creatable = true; xfc->notify = pnv_phb4_xive_notify; } diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -XXX,XX +XXX,XX @@ #include "hw/pci/pci_bus.h" #include "hw/ppc/pnv.h" #include "hw/qdev-properties.h" +#include "sysemu/sysemu.h" #include <libfdt.h> @@ -XXX,XX +XXX,XX @@ static const TypeInfo pnv_pec_type_info = { } }; -static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) +static void pnv_pec_stk_default_phb_realize(PnvPhb4PecStack *stack, + Error **errp) { - PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(dev); PnvPhb4PecState *pec = stack->pec; PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); int phb_id = pnv_phb4_pec_get_phb_id(pec, stack->stack_no); @@ -XXX,XX +XXX,XX @@ static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) &error_fatal); object_property_set_link(OBJECT(stack->phb), "stack", OBJECT(stack), &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(stack->phb), errp)) { return; } } +static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) +{ + PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(dev); + + if (!defaults_enabled()) { + return; + } + + pnv_pec_stk_default_phb_realize(stack, errp); +} + static Property pnv_pec_stk_properties[] = { DEFINE_PROP_UINT32("stack-no", PnvPhb4PecStack, stack_no, 0), DEFINE_PROP_LINK("pec", PnvPhb4PecStack, pec, TYPE_PNV_PHB4_PEC, diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index XXXXXXX..XXXXXXX 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -XXX,XX +XXX,XX @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) pmc->compat = compat; pmc->compat_size = sizeof(compat); pmc->dt_power_mgt = pnv_dt_power_mgt; + + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB4); } static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) -- 2.31.1 From: Daniel Henrique Barboza <danielhb413@gmail.com> Its only callers are inside pnv_phb4.c. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220111131027.599784-6-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- include/hw/pci-host/pnv_phb4.h | 1 - hw/pci-host/pnv_phb4.c | 52 +++++++++++++++++----------------- 2 files changed, 26 insertions(+), 27 deletions(-) diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -XXX,XX +XXX,XX @@ struct PnvPHB4 { }; void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon); -void pnv_phb4_update_regions(PnvPhb4PecStack *stack); int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index); extern const MemoryRegionOps pnv_phb4_xscom_ops; diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -XXX,XX +XXX,XX @@ static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr, return stack->nest_regs[reg]; } +static void pnv_phb4_update_regions(PnvPhb4PecStack *stack) +{ + PnvPHB4 *phb = stack->phb; + + /* Unmap first always */ + if (memory_region_is_mapped(&phb->mr_regs)) { + memory_region_del_subregion(&stack->phbbar, &phb->mr_regs); + } + if (memory_region_is_mapped(&phb->xsrc.esb_mmio)) { + memory_region_del_subregion(&stack->intbar, &phb->xsrc.esb_mmio); + } + + /* Map registers if enabled */ + if (memory_region_is_mapped(&stack->phbbar)) { + memory_region_add_subregion(&stack->phbbar, 0, &phb->mr_regs); + } + + /* Map ESB if enabled */ + if (memory_region_is_mapped(&stack->intbar)) { + memory_region_add_subregion(&stack->intbar, 0, &phb->xsrc.esb_mmio); + } + + /* Check/update m32 */ + pnv_phb4_check_all_mbt(phb); +} + static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack) { PnvPhb4PecState *pec = stack->pec; @@ -XXX,XX +XXX,XX @@ static void pnv_phb4_register_types(void) type_init(pnv_phb4_register_types); -void pnv_phb4_update_regions(PnvPhb4PecStack *stack) -{ - PnvPHB4 *phb = stack->phb; - - /* Unmap first always */ - if (memory_region_is_mapped(&phb->mr_regs)) { - memory_region_del_subregion(&stack->phbbar, &phb->mr_regs); - } - if (memory_region_is_mapped(&phb->xsrc.esb_mmio)) { - memory_region_del_subregion(&stack->intbar, &phb->xsrc.esb_mmio); - } - - /* Map registers if enabled */ - if (memory_region_is_mapped(&stack->phbbar)) { - memory_region_add_subregion(&stack->phbbar, 0, &phb->mr_regs); - } - - /* Map ESB if enabled */ - if (memory_region_is_mapped(&stack->intbar)) { - memory_region_add_subregion(&stack->intbar, 0, &phb->xsrc.esb_mmio); - } - - /* Check/update m32 */ - pnv_phb4_check_all_mbt(phb); -} - void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon) { uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3]; -- 2.31.1 From: Daniel Henrique Barboza <danielhb413@gmail.com> pnv_pec_stk_pci_xscom_write() is pnv_pec_stk_pci_xscom_ops write callback. It writes values into regs in the stack->nest_regs[] array. The pnv_pec_stk_pci_xscom_read read callback, on the other hand, returns values of the stack->pci_regs[]. In fact, at this moment, the only use of stack->pci_regs[] is in pnv_pec_stk_pci_xscom_read(). There's no code that is written anything in stack->pci_regs[], which is suspicious. Considering that stack->nest_regs[] is widely used by the nested MemoryOps pnv_pec_stk_nest_xscom_ops, in both read and write callbacks, the conclusion is that we're writing the wrong array in pnv_pec_stk_pci_xscom_write(). This function should write stack->pci_regs[] instead. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20220111200132.633896-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/pci-host/pnv_phb4.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index XXXXXXX..XXXXXXX 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -XXX,XX +XXX,XX @@ static void pnv_pec_stk_pci_xscom_write(void *opaque, hwaddr addr, switch (reg) { case PEC_PCI_STK_PCI_FIR: - stack->nest_regs[reg] = val; + stack->pci_regs[reg] = val; break; case PEC_PCI_STK_PCI_FIR_CLR: - stack->nest_regs[PEC_PCI_STK_PCI_FIR] &= val; + stack->pci_regs[PEC_PCI_STK_PCI_FIR] &= val; break; case PEC_PCI_STK_PCI_FIR_SET: - stack->nest_regs[PEC_PCI_STK_PCI_FIR] |= val; + stack->pci_regs[PEC_PCI_STK_PCI_FIR] |= val; break; case PEC_PCI_STK_PCI_FIR_MSK: - stack->nest_regs[reg] = val; + stack->pci_regs[reg] = val; break; case PEC_PCI_STK_PCI_FIR_MSKC: - stack->nest_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val; + stack->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val; break; case PEC_PCI_STK_PCI_FIR_MSKS: - stack->nest_regs[PEC_PCI_STK_PCI_FIR_MSK] |= val; + stack->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] |= val; break; case PEC_PCI_STK_PCI_FIR_ACT0: case PEC_PCI_STK_PCI_FIR_ACT1: - stack->nest_regs[reg] = val; + stack->pci_regs[reg] = val; break; case PEC_PCI_STK_PCI_FIR_WOF: - stack->nest_regs[reg] = 0; + stack->pci_regs[reg] = 0; break; case PEC_PCI_STK_ETU_RESET: - stack->nest_regs[reg] = val & 0x8000000000000000ull; + stack->pci_regs[reg] = val & 0x8000000000000000ull; /* TODO: Implement reset */ break; case PEC_PCI_STK_PBAIB_ERR_REPORT: break; case PEC_PCI_STK_PBAIB_TX_CMD_CRED: case PEC_PCI_STK_PBAIB_TX_DAT_CRED: - stack->nest_regs[reg] = val; + stack->pci_regs[reg] = val; break; default: qemu_log_mask(LOG_UNIMP, "phb4_pec_stk: pci_xscom_write 0x%"HWADDR_PRIx -- 2.31.1 The following changes since commit 76b56fdfc9fa43ec6e5986aee33f108c6c6a511e: Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2021-12-14 12:46:18 -0800) are available in the Git repository at: https://github.com/legoater/qemu/ tags/pull-ppc-20211217 for you to fetch changes up to 0e6232bc3cb96bdf6fac1b5d7659aa9887afe657: ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices (2021-12-17 17:57:19 +0100) Changes in v3: - Fixed patch "docs: Introducing pseries documentation" with a newline and checked documentation generation with : make docker-test-build@ubuntu1804 TARGET_LIST=i386-softmmu Changes in v2: - Fixed patch "docs: rSTify ppc-spapr-hcalls.txt" with a newline - dropped patch "target/ppc: do not silence SNaN in xscvspdpn" which still had some comments pending. ---------------------------------------------------------------- ppc 7.0 queue: * General cleanup for Mac machines (Peter) * Fixes for FPU exceptions (Lucas) * Support for new ISA31 instructions (Matheus) * Fixes for ivshmem (Daniel) * Cleanups for PowerNV PHB (Christophe and Cedric) * Updates of PowerNV and pSeries documentation (Leonardo and Daniel) * Fixes for PowerNV (Daniel) * Large cleanup of FPU implementation (Richard) * Removal of SoftTLBs support for PPC74x CPUs (Fabiano) * Fixes for exception models in MPCx and 60x CPUs (Fabiano) * Removal of 401/403 CPUs (Cedric) * Deprecation of taihu machine (Thomas) * Large rework of PPC405 machine (Cedric) * Fixes for VSX instructions (Victor and Matheus) * Fix for e6500 CPU (Fabiano) * Initial support for PMU (Daniel) ---------------------------------------------------------------- Alexey Kardashevskiy (1): pseries: Update SLOF firmware image Christophe Lombard (1): pci-host: Allow extended config space access for PowerNV PHB4 model Cédric Le Goater (28): Merge tag 'qemu-slof-20211112' of github.com:aik/qemu into ppc-next target/ppc: remove 401/403 CPUs ppc/ppc405: Change kernel load address ppc: Add trace-events for DCR accesses ppc/ppc405: Convert printfs to trace-events ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo() ppc/ppc405: Change ppc405ep_init() return value ppc/ppc405: Add some address space definitions ppc/ppc405: Remove flash support ppc/ppc405: Rework FW load ppc/ppc405: Introduce ppc405_set_default_bootinfo() ppc/ppc405: Fix boot from kernel ppc/ppc405: Change default PLL values at reset ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information ppc/ppc405: Add update of bi_procfreq field ppc/pnv: Introduce a "chip" property under PHB3 ppc/pnv: Use the chip class to check the index of PHB3 devices ppc/pnv: Drop the "num-phbs" property ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize() ppc/pnv: Use QOM hierarchy to scan PHB3 devices ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices ppc/pnv: Introduce version and device_id class atributes for PHB4 devices ppc/pnv: Introduce a "chip" property under the PHB4 model ppc/pnv: Introduce a num_stack class attribute ppc/pnv: Compute the PHB index from the PHB4 PEC model ppc/pnv: Remove "system-memory" property from PHB4 PEC ppc/pnv: Move realize of PEC stacks under the PEC model ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices Daniel Henrique Barboza (13): ivshmem.c: change endianness to LITTLE_ENDIAN ivshmem-test.c: enable test_ivshmem_server for ppc64 arch ppc/pnv.c: add a friendly warning when accel=kvm is used docs/system/ppc/powernv.rst: document KVM support status ppc/pnv.c: fix "system-id" FDT when -uuid is set target/ppc: introduce PMUEventType and PMU overflow timers target/ppc: PMU basic cycle count for pseries TCG target/ppc: PMU: update counters on PMCs r/w target/ppc: PMU: update counters on MMCR1 write target/ppc: enable PMU counter overflow with cycle events target/ppc: enable PMU instruction count target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event PPC64/TCG: Implement 'rfebb' instruction Fabiano Rosas (8): target/ppc: Disable software TLB for the 7450 family target/ppc: Disable unused facilities in the e600 CPU target/ppc: Remove the software TLB model of 7450 CPUs target/ppc: Fix MPCxxx FPU interrupt address target/ppc: Remove 603e exception model target/ppc: Set 601v exception model id target/ppc: Fix e6500 boot Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp" Leonardo Garcia (5): docs: Minor updates on the powernv documentation. docs: Introducing pseries documentation. docs: rSTify ppc-spapr-hcalls.txt docs: Rename ppc-spapr-hcalls.txt to ppc-spapr-hcalls.rst. Link new ppc-spapr-hcalls.rst file to pseries.rst. Lucas Mateus Castro (alqotel) (3): target/ppc: Fixed call to deferred exception test/tcg/ppc64le: test mtfsf target/ppc: ppc_store_fpscr doesn't update bits 0 to 28 and 52 Matheus Ferst (5): target/ppc: Implement Vector Expand Mask target/ppc: Implement Vector Extract Mask target/ppc: Implement Vector Mask Move insns target/ppc: fix xscvqpdp register access target/ppc: move xscvqpdp to decodetree Peter Maydell (1): hw/ppc/mac.h: Remove MAX_CPUS macro Richard Henderson (34): softfloat: Extend float_exception_flags to 16 bits softfloat: Add flag specific to Inf - Inf softfloat: Add flag specific to Inf * 0 softfloat: Add flags specific to Inf / Inf and 0 / 0 softfloat: Add flag specific to sqrt(-x) softfloat: Add flag specific to convert non-nan to int softfloat: Add flag specific to signaling nans target/ppc: Update float_invalid_op_addsub for new flags target/ppc: Update float_invalid_op_mul for new flags target/ppc: Update float_invalid_op_div for new flags target/ppc: Move float_check_status from FPU_FCTI to translate target/ppc: Update float_invalid_cvt for new flags target/ppc: Fix VXCVI return value target/ppc: Remove inline from do_fri target/ppc: Use FloatRoundMode in do_fri target/ppc: Tidy inexact handling in do_fri target/ppc: Clean up do_fri target/ppc: Update fmadd for new flags target/ppc: Split out do_fmadd target/ppc: Do not call do_float_check_status from do_fmadd target/ppc: Split out do_frsp target/ppc: Update do_frsp for new flags target/ppc: Use helper_todouble in do_frsp target/ppc: Update sqrt for new flags target/ppc: Update xsrqpi and xsrqpxp to new flags target/ppc: Update fre to new flags softfloat: Add float64r32 arithmetic routines target/ppc: Add helpers for fmadds et al target/ppc: Add helper for fsqrts target/ppc: Add helpers for fadds, fsubs, fdivs target/ppc: Add helper for fmuls target/ppc: Add helper for frsqrtes target/ppc: Update fres to new flags and float64r32 target/ppc: Use helper_todouble/tosingle in helper_xststdcsp Thomas Huth (1): ppc: Mark the 'taihu' machine as deprecated Victor Colombo (2): target/ppc: Fix xs{max, min}[cj]dp to use VSX registers target/ppc: Move xs{max,min}[cj]dp to decodetree docs/about/deprecated.rst | 9 + docs/specs/ppc-spapr-hcalls.rst | 100 +++++ docs/specs/ppc-spapr-hcalls.txt | 78 ---- docs/system/ppc/powernv.rst | 68 ++-- docs/system/ppc/pseries.rst | 226 +++++++++++ hw/ppc/mac.h | 3 - hw/ppc/ppc405.h | 14 +- include/fpu/softfloat-types.h | 23 +- include/fpu/softfloat.h | 14 +- include/hw/pci-host/pnv_phb3.h | 3 + include/hw/pci-host/pnv_phb4.h | 5 + include/hw/ppc/pnv.h | 2 + target/ppc/cpu-models.h | 19 - target/ppc/cpu-qom.h | 12 +- target/ppc/cpu.h | 63 +++- target/ppc/helper.h | 29 +- target/ppc/power8-pmu.h | 26 ++ target/ppc/spr_tcg.h | 5 + target/ppc/insn32.decode | 54 ++- fpu/softfloat.c | 114 +++++- hw/misc/ivshmem.c | 2 +- hw/pci-host/pnv_phb3.c | 3 +- hw/pci-host/pnv_phb3_pbcq.c | 11 + hw/pci-host/pnv_phb4.c | 1 + hw/pci-host/pnv_phb4_pec.c | 75 +++- hw/ppc/mac_newworld.c | 3 +- hw/ppc/mac_oldworld.c | 3 +- hw/ppc/pnv.c | 177 +++++---- hw/ppc/ppc.c | 2 + hw/ppc/ppc405_boards.c | 245 ++++++------ hw/ppc/ppc405_uc.c | 225 ++++++----- hw/ppc/spapr_cpu_core.c | 1 + target/ppc/cpu-models.c | 34 -- target/ppc/cpu.c | 2 +- target/ppc/cpu_init.c | 658 +++------------------------------ target/ppc/excp_helper.c | 95 +++-- target/ppc/fpu_helper.c | 593 +++++++++++++++-------------- target/ppc/helper_regs.c | 7 + target/ppc/mmu_common.c | 60 +-- target/ppc/mmu_helper.c | 32 -- target/ppc/power8-pmu.c | 350 ++++++++++++++++++ target/ppc/translate.c | 104 ++++-- tests/qtest/ivshmem-test.c | 5 +- tests/tcg/ppc64le/mtfsf.c | 61 +++ fpu/softfloat-parts.c.inc | 57 +-- fpu/softfloat-specialize.c.inc | 12 +- target/ppc/power8-pmu-regs.c.inc | 69 +++- target/ppc/translate/branch-impl.c.inc | 33 ++ target/ppc/translate/fp-impl.c.inc | 53 +-- target/ppc/translate/vmx-impl.c.inc | 231 ++++++++++++ target/ppc/translate/vsx-impl.c.inc | 55 ++- target/ppc/translate/vsx-ops.c.inc | 5 - hw/ppc/trace-events | 23 ++ pc-bios/README | 2 +- pc-bios/slof.bin | Bin 991744 -> 991920 bytes roms/SLOF | 2 +- target/ppc/meson.build | 1 + tests/tcg/ppc64/Makefile.target | 1 + tests/tcg/ppc64le/Makefile.target | 1 + 59 files changed, 2514 insertions(+), 1647 deletions(-) create mode 100644 docs/specs/ppc-spapr-hcalls.rst delete mode 100644 docs/specs/ppc-spapr-hcalls.txt create mode 100644 target/ppc/power8-pmu.h create mode 100644 target/ppc/power8-pmu.c create mode 100644 tests/tcg/ppc64le/mtfsf.c create mode 100644 target/ppc/translate/branch-impl.c.inc