From nobody Sat May 4 02:02:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641910045523124.35516710130958; Tue, 11 Jan 2022 06:07:25 -0800 (PST) Received: from localhost ([::1]:33860 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n7Ho4-0003tm-R3 for importer@patchew.org; Tue, 11 Jan 2022 09:07:24 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54328) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n7GvS-0003nO-KX; Tue, 11 Jan 2022 08:11:03 -0500 Received: from [2607:f8b0:4864:20::929] (port=40890 helo=mail-ua1-x929.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n7GvO-0007Qa-4I; Tue, 11 Jan 2022 08:10:58 -0500 Received: by mail-ua1-x929.google.com with SMTP id v12so29560056uar.7; Tue, 11 Jan 2022 05:10:38 -0800 (PST) Received: from rekt.COMFAST ([152.249.109.193]) by smtp.gmail.com with ESMTPSA id f1sm5386381uae.5.2022.01.11.05.10.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jan 2022 05:10:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mL32hyhTes7jx530XhjuJGDdDmqvwezifm77V28qMko=; b=FiYQtj9y+rUr16Qhxdj6Y7w8EtDY34s1uwX7QjbjtIAfan3Wy2AVoEVry1lMVk5Epo offz+nQv/cidQdoFqWc6HHMpq/DXZbX4+GLnsHhrUed4KStKB4cuu5F4TkcnYV1jH/C0 YVxEDYLkseRwB2qEVslKkGSnZ6+n5S7H/YkVQ2luFnruAsrB7s/amzcBSdOVmeI7dOOQ cINXhqp/V3VvYbb85QaQn76E5JW/1vYjtyHc1whZHF5oyz9wAtRQI3jJ3cLSk5EyLc4t 3ndzbR8KuFazFeDD8Qka4LuUh4/F1/AFxIVG8dVIuNoHa1o8BUSmLqKf18pb8A0OHI0g WHcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mL32hyhTes7jx530XhjuJGDdDmqvwezifm77V28qMko=; b=NbP+WwokLAywd4mS7eBCCZYwcvY284T50hch8FdJbBHycxQfLpehKIDIXGQkXkvXVT t+CaZvDvqCnhYro0sEWPmva4KQO57ly0zZrQHaD9MLQyOyH0PHZ+ZgLH1d7m7Gk6/01T 6046/kVxdt+8T3MtEMCrGJOeZwqR9OQavX4mjqJOW35yE2MgVS7spgTVJmeEZDqvkrxt UVOGdkefKaNAJD2EFCtp7Buav/8YyLe1Afe9o1wJipZpK9G0S+F2sWEnZWkFQx+whklW XsK9YdSEbu56tRoG1e/isKk1i3GyyIkVqdOym5qu/fbDoeC+tAXBkbZepNJt/ypmpJ1g HDHQ== X-Gm-Message-State: AOAM531GwnUnNK6LyF74LWLWIe56dVW1SGtc5rbOoYzE8KfGfR41G2DT QkMreliSoTS44j6hYYB6mJaeVzge7V7E/MTZ X-Google-Smtp-Source: ABdhPJwE1HjVEfpuj6ca43Ieey+IUD6+LctCFjCm0lHQzFpgkLRIMSW9xiTQ+G1vJv5U1uKEujxxeA== X-Received: by 2002:a05:6102:cca:: with SMTP id g10mr1829347vst.75.1641906637576; Tue, 11 Jan 2022 05:10:37 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v5 1/5] ppc/pnv: set phb4 properties in stk_realize() Date: Tue, 11 Jan 2022 10:10:23 -0300 Message-Id: <20220111131027.599784-2-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220111131027.599784-1-danielhb413@gmail.com> References: <20220111131027.599784-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::929 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::929; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x929.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641910048214100001 Moving all phb4 properties setup to stk_realize() keeps this logic in a single place instead of having it scattered between stk_realize() and pec_realize(). 'phb->index' can be retrieved using stack->stack_no and pnv_phb4_pec_get_phb_id(), deprecating the use of 'phb-id' alias that was being used for this purpose in pec_realize(). Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb4_pec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index d64310e7db..f8038dff17 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -392,10 +392,8 @@ static void pnv_pec_realize(DeviceState *dev, Error **= errp) for (i =3D 0; i < pec->num_stacks; i++) { PnvPhb4PecStack *stack =3D &pec->stacks[i]; Object *stk_obj =3D OBJECT(stack); - int phb_id =3D pnv_phb4_pec_get_phb_id(pec, i); =20 object_property_set_int(stk_obj, "stack-no", i, &error_abort); - object_property_set_int(stk_obj, "phb-id", phb_id, &error_abort); object_property_set_link(stk_obj, "pec", OBJECT(pec), &error_abort= ); if (!qdev_realize(DEVICE(stk_obj), NULL, errp)) { return; @@ -534,7 +532,6 @@ static void pnv_pec_stk_instance_init(Object *obj) PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(obj); =20 object_initialize_child(obj, "phb", &stack->phb, TYPE_PNV_PHB4); - object_property_add_alias(obj, "phb-id", OBJECT(&stack->phb), "index"); } =20 static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) @@ -543,6 +540,7 @@ static void pnv_pec_stk_realize(DeviceState *dev, Error= **errp) PnvPhb4PecState *pec =3D stack->pec; PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_GET_CLASS(pec); PnvChip *chip =3D pec->chip; + int phb_id =3D pnv_phb4_pec_get_phb_id(pec, stack->stack_no); uint32_t pec_nest_base; uint32_t pec_pci_base; char name[64]; @@ -570,6 +568,8 @@ static void pnv_pec_stk_realize(DeviceState *dev, Error= **errp) =20 object_property_set_int(OBJECT(&stack->phb), "chip-id", pec->chip_id, &error_fatal); + object_property_set_int(OBJECT(&stack->phb), "index", phb_id, + &error_fatal); object_property_set_int(OBJECT(&stack->phb), "version", pecc->version, &error_fatal); object_property_set_link(OBJECT(&stack->phb), "stack", OBJECT(stack), --=20 2.33.1 From nobody Sat May 4 02:02:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641911388823757.6768399691118; Tue, 11 Jan 2022 06:29:48 -0800 (PST) Received: from localhost ([::1]:48212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n7I9j-0008HH-OX for importer@patchew.org; Tue, 11 Jan 2022 09:29:47 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54290) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n7GvR-0003mj-8k; Tue, 11 Jan 2022 08:10:58 -0500 Received: from [2607:f8b0:4864:20::a2a] (port=37629 helo=mail-vk1-xa2a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n7GvO-0007Qr-4H; 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d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K+aWuRuKnWFIPnhtENPuD0T71uhVws5mGpzm8KEPHx8=; b=cpMd1nQimIWHXiwX3BoOvJYjBGgdwLUcnq2uQ9mAv1qAibMfvlAN/zAZxp34yBFCwE QFOegv0c7IwQ5aanncax4v9B/wbnWYzAtfVYR6hk0BKO4yU/XemJMD5Uv9ADjZl9eTqE cyKsHKGOPZ81IrMlsgAiQOSFMOTNt0cXVh0uhPIvPiOpgwRuj4x7yAlRIRJ4YbBdhnaL ckgPlPEbm4czxx4M1ZRZKhx3CBhTYlk9+FBgU5gULaIORAQFELtoNrQ2LVAWSf3hloGT GtFEWyjMjpqc88ur8W+hfSl+HkDbn7bnLgB/9g1Fn7WJohTw+P/0YaPYyTAcGETYtQ0h MRpw== X-Gm-Message-State: AOAM533Zj+XhA3aJCWewJ3oYtwSatdvReyc85Sri5TMoAqV2x+xdlFzO 3sYDdY3IbNMCQxEW2Mw42chjsJ5OTSmMIgP1 X-Google-Smtp-Source: ABdhPJz7M/1sska+HHyRtRszR0dhbnJtu9/zHBqMyB+DROEBjBj72Pnxeja3VfF/D6ct6aQQiCICFQ== X-Received: by 2002:a1f:df87:: with SMTP id w129mr2109878vkg.36.1641906639402; Tue, 11 Jan 2022 05:10:39 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v5 2/5] ppc/pnv: move PHB4 XSCOM init to phb4_realize() Date: Tue, 11 Jan 2022 10:10:24 -0300 Message-Id: <20220111131027.599784-3-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220111131027.599784-1-danielhb413@gmail.com> References: <20220111131027.599784-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::a2a (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::a2a; envelope-from=danielhb413@gmail.com; helo=mail-vk1-xa2a.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641911391237100001 The 'stack->phb_regs_mr' PHB4 passthrough XSCOM initialization relies on 'stack->phb' being not NULL. Moving 'stack->phb_regs_mr' region_init() and add_subregion() to phb4_realize() time is a natural thing to do since it's strictly PHB related. The remaining XSCOM initialization is also related to 'stack->phb' but in a different manner. For instance, 'stack->nest_regs_mr' MemoryRegionOps, 'pnv_pec_stk_nest_xscom_ops', uses pnv_pec_stk_nest_xscom_write() as a write callback. When trying to write the PEC_NEST_STK_BAR_EN reg, pnv_pec_stk_update_map() is called. Inside this function, pnv_phb4_update_regions() is called twice. This function uses 'stack->phb' to manipulate memory regions of the phb. This is not a problem now but, when enabling user creatable phb4s, a stack that doesn't have an associated phb (i.e. stack->phb =3D NULL) it will cause a SIGINT during boot in pnv_phb4_update_regions(). All this can be avoided if all XSCOM realize is moved to phb4_realize(), when we have certainty about the existence of 'stack->phb'. A lot of code was moved from pnv_phb4_pec.c to pnv_phb4.c due to static constant and variables being used but the cleaner logic is worth the trouble. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb4.c | 304 +++++++++++++++++++++++++++++++++++++ hw/pci-host/pnv_phb4_pec.c | 292 ----------------------------------- 2 files changed, 304 insertions(+), 292 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index b7b0091f93..94fd8c858d 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -29,6 +29,10 @@ qemu_log_mask(LOG_GUEST_ERROR, "phb4[%d:%d]: " fmt "\n", \ (phb)->chip_id, (phb)->phb_id, ## __VA_ARGS__) =20 +#define phb_pec_error(pec, fmt, ...) \ + qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n", \ + (pec)->chip_id, (pec)->index, ## __VA_ARGS__) + /* * QEMU version of the GETFIELD/SETFIELD macros * @@ -854,6 +858,258 @@ const MemoryRegionOps pnv_phb4_xscom_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 +static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr, + unsigned size) +{ + PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(opaque); + uint32_t reg =3D addr >> 3; + + /* TODO: add list of allowed registers and error out if not */ + return stack->nest_regs[reg]; +} + +static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack) +{ + PnvPhb4PecState *pec =3D stack->pec; + MemoryRegion *sysmem =3D get_system_memory(); + uint64_t bar_en =3D stack->nest_regs[PEC_NEST_STK_BAR_EN]; + uint64_t bar, mask, size; + char name[64]; + + /* + * NOTE: This will really not work well if those are remapped + * after the PHB has created its sub regions. We could do better + * if we had a way to resize regions but we don't really care + * that much in practice as the stuff below really only happens + * once early during boot + */ + + /* Handle unmaps */ + if (memory_region_is_mapped(&stack->mmbar0) && + !(bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) { + memory_region_del_subregion(sysmem, &stack->mmbar0); + } + if (memory_region_is_mapped(&stack->mmbar1) && + !(bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) { + memory_region_del_subregion(sysmem, &stack->mmbar1); + } + if (memory_region_is_mapped(&stack->phbbar) && + !(bar_en & PEC_NEST_STK_BAR_EN_PHB)) { + memory_region_del_subregion(sysmem, &stack->phbbar); + } + if (memory_region_is_mapped(&stack->intbar) && + !(bar_en & PEC_NEST_STK_BAR_EN_INT)) { + memory_region_del_subregion(sysmem, &stack->intbar); + } + + /* Update PHB */ + pnv_phb4_update_regions(stack); + + /* Handle maps */ + if (!memory_region_is_mapped(&stack->mmbar0) && + (bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) { + bar =3D stack->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8; + mask =3D stack->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK]; + size =3D ((~mask) >> 8) + 1; + snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio0", + pec->chip_id, pec->index, stack->stack_no); + memory_region_init(&stack->mmbar0, OBJECT(stack), name, size); + memory_region_add_subregion(sysmem, bar, &stack->mmbar0); + stack->mmio0_base =3D bar; + stack->mmio0_size =3D size; + } + if (!memory_region_is_mapped(&stack->mmbar1) && + (bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) { + bar =3D stack->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8; + mask =3D stack->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK]; + size =3D ((~mask) >> 8) + 1; + snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio1", + pec->chip_id, pec->index, stack->stack_no); + memory_region_init(&stack->mmbar1, OBJECT(stack), name, size); + memory_region_add_subregion(sysmem, bar, &stack->mmbar1); + stack->mmio1_base =3D bar; + stack->mmio1_size =3D size; + } + if (!memory_region_is_mapped(&stack->phbbar) && + (bar_en & PEC_NEST_STK_BAR_EN_PHB)) { + bar =3D stack->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8; + size =3D PNV_PHB4_NUM_REGS << 3; + snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-phb", + pec->chip_id, pec->index, stack->stack_no); + memory_region_init(&stack->phbbar, OBJECT(stack), name, size); + memory_region_add_subregion(sysmem, bar, &stack->phbbar); + } + if (!memory_region_is_mapped(&stack->intbar) && + (bar_en & PEC_NEST_STK_BAR_EN_INT)) { + bar =3D stack->nest_regs[PEC_NEST_STK_INT_BAR] >> 8; + size =3D PNV_PHB4_MAX_INTs << 16; + snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-int", + stack->pec->chip_id, stack->pec->index, stack->stack_no); + memory_region_init(&stack->intbar, OBJECT(stack), name, size); + memory_region_add_subregion(sysmem, bar, &stack->intbar); + } + + /* Update PHB */ + pnv_phb4_update_regions(stack); +} + +static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(opaque); + PnvPhb4PecState *pec =3D stack->pec; + uint32_t reg =3D addr >> 3; + + switch (reg) { + case PEC_NEST_STK_PCI_NEST_FIR: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] =3D val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_CLR: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &=3D val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_SET: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |=3D val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_MSK: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] =3D val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_MSKC: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &=3D val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_MSKS: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] |=3D val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_ACT0: + case PEC_NEST_STK_PCI_NEST_FIR_ACT1: + stack->nest_regs[reg] =3D val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_WOF: + stack->nest_regs[reg] =3D 0; + break; + case PEC_NEST_STK_ERR_REPORT_0: + case PEC_NEST_STK_ERR_REPORT_1: + case PEC_NEST_STK_PBCQ_GNRL_STATUS: + /* Flag error ? */ + break; + case PEC_NEST_STK_PBCQ_MODE: + stack->nest_regs[reg] =3D val & 0xff00000000000000ull; + break; + case PEC_NEST_STK_MMIO_BAR0: + case PEC_NEST_STK_MMIO_BAR0_MASK: + case PEC_NEST_STK_MMIO_BAR1: + case PEC_NEST_STK_MMIO_BAR1_MASK: + if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & + (PEC_NEST_STK_BAR_EN_MMIO0 | + PEC_NEST_STK_BAR_EN_MMIO1)) { + phb_pec_error(pec, "Changing enabled BAR unsupported\n"); + } + stack->nest_regs[reg] =3D val & 0xffffffffff000000ull; + break; + case PEC_NEST_STK_PHB_REGS_BAR: + if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PH= B) { + phb_pec_error(pec, "Changing enabled BAR unsupported\n"); + } + stack->nest_regs[reg] =3D val & 0xffffffffffc00000ull; + break; + case PEC_NEST_STK_INT_BAR: + if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_IN= T) { + phb_pec_error(pec, "Changing enabled BAR unsupported\n"); + } + stack->nest_regs[reg] =3D val & 0xfffffff000000000ull; + break; + case PEC_NEST_STK_BAR_EN: + stack->nest_regs[reg] =3D val & 0xf000000000000000ull; + pnv_pec_stk_update_map(stack); + break; + case PEC_NEST_STK_DATA_FRZ_TYPE: + case PEC_NEST_STK_PBCQ_TUN_BAR: + /* Not used for now */ + stack->nest_regs[reg] =3D val; + break; + default: + qemu_log_mask(LOG_UNIMP, "phb4_pec: nest_xscom_write 0x%"HWADDR_PR= Ix + "=3D%"PRIx64"\n", addr, val); + } +} + +static const MemoryRegionOps pnv_pec_stk_nest_xscom_ops =3D { + .read =3D pnv_pec_stk_nest_xscom_read, + .write =3D pnv_pec_stk_nest_xscom_write, + .valid.min_access_size =3D 8, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, hwaddr addr, + unsigned size) +{ + PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(opaque); + uint32_t reg =3D addr >> 3; + + /* TODO: add list of allowed registers and error out if not */ + return stack->pci_regs[reg]; +} + +static void pnv_pec_stk_pci_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(opaque); + uint32_t reg =3D addr >> 3; + + switch (reg) { + case PEC_PCI_STK_PCI_FIR: + stack->nest_regs[reg] =3D val; + break; + case PEC_PCI_STK_PCI_FIR_CLR: + stack->nest_regs[PEC_PCI_STK_PCI_FIR] &=3D val; + break; + case PEC_PCI_STK_PCI_FIR_SET: + stack->nest_regs[PEC_PCI_STK_PCI_FIR] |=3D val; + break; + case PEC_PCI_STK_PCI_FIR_MSK: + stack->nest_regs[reg] =3D val; + break; + case PEC_PCI_STK_PCI_FIR_MSKC: + stack->nest_regs[PEC_PCI_STK_PCI_FIR_MSK] &=3D val; + break; + case PEC_PCI_STK_PCI_FIR_MSKS: + stack->nest_regs[PEC_PCI_STK_PCI_FIR_MSK] |=3D val; + break; + case PEC_PCI_STK_PCI_FIR_ACT0: + case PEC_PCI_STK_PCI_FIR_ACT1: + stack->nest_regs[reg] =3D val; + break; + case PEC_PCI_STK_PCI_FIR_WOF: + stack->nest_regs[reg] =3D 0; + break; + case PEC_PCI_STK_ETU_RESET: + stack->nest_regs[reg] =3D val & 0x8000000000000000ull; + /* TODO: Implement reset */ + break; + case PEC_PCI_STK_PBAIB_ERR_REPORT: + break; + case PEC_PCI_STK_PBAIB_TX_CMD_CRED: + case PEC_PCI_STK_PBAIB_TX_DAT_CRED: + stack->nest_regs[reg] =3D val; + break; + default: + qemu_log_mask(LOG_UNIMP, "phb4_pec_stk: pci_xscom_write 0x%"HWADDR= _PRIx + "=3D%"PRIx64"\n", addr, val); + } +} + +static const MemoryRegionOps pnv_pec_stk_pci_xscom_ops =3D { + .read =3D pnv_pec_stk_pci_xscom_read, + .write =3D pnv_pec_stk_pci_xscom_write, + .valid.min_access_size =3D 8, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + static int pnv_phb4_map_irq(PCIDevice *pci_dev, int irq_num) { /* Check that out properly ... */ @@ -1175,6 +1431,52 @@ int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, in= t stack_index) return offset + stack_index; } =20 +static void pnv_phb4_xscom_realize(PnvPHB4 *phb) +{ + PnvPhb4PecStack *stack =3D phb->stack; + PnvPhb4PecState *pec =3D stack->pec; + PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_GET_CLASS(pec); + uint32_t pec_nest_base; + uint32_t pec_pci_base; + char name[64]; + + assert(pec); + + /* Initialize the XSCOM regions for the stack registers */ + snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest-stack-%d", + pec->chip_id, pec->index, stack->stack_no); + pnv_xscom_region_init(&stack->nest_regs_mr, OBJECT(stack), + &pnv_pec_stk_nest_xscom_ops, stack, name, + PHB4_PEC_NEST_STK_REGS_COUNT); + + snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d", + pec->chip_id, pec->index, stack->stack_no); + pnv_xscom_region_init(&stack->pci_regs_mr, OBJECT(stack), + &pnv_pec_stk_pci_xscom_ops, stack, name, + PHB4_PEC_PCI_STK_REGS_COUNT); + + /* PHB pass-through */ + snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d-phb", + pec->chip_id, pec->index, stack->stack_no); + pnv_xscom_region_init(&stack->phb_regs_mr, OBJECT(phb), + &pnv_phb4_xscom_ops, phb, name, 0x40); + + pec_nest_base =3D pecc->xscom_nest_base(pec); + pec_pci_base =3D pecc->xscom_pci_base(pec); + + /* Populate the XSCOM address space. */ + pnv_xscom_add_subregion(pec->chip, + pec_nest_base + 0x40 * (stack->stack_no + 1), + &stack->nest_regs_mr); + pnv_xscom_add_subregion(pec->chip, + pec_pci_base + 0x40 * (stack->stack_no + 1), + &stack->pci_regs_mr); + pnv_xscom_add_subregion(pec->chip, + pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + + 0x40 * stack->stack_no, + &stack->phb_regs_mr); +} + static void pnv_phb4_instance_init(Object *obj) { PnvPHB4 *phb =3D PNV_PHB4(obj); @@ -1247,6 +1549,8 @@ static void pnv_phb4_realize(DeviceState *dev, Error = **errp) pnv_phb4_update_xsrc(phb); =20 phb->qirqs =3D qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_= irqs); + + pnv_phb4_xscom_realize(phb); } =20 static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge, diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index f8038dff17..bf0fdf33fd 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -111,258 +111,6 @@ static const MemoryRegionOps pnv_pec_pci_xscom_ops = =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr, - unsigned size) -{ - PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(opaque); - uint32_t reg =3D addr >> 3; - - /* TODO: add list of allowed registers and error out if not */ - return stack->nest_regs[reg]; -} - -static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack) -{ - PnvPhb4PecState *pec =3D stack->pec; - MemoryRegion *sysmem =3D get_system_memory(); - uint64_t bar_en =3D stack->nest_regs[PEC_NEST_STK_BAR_EN]; - uint64_t bar, mask, size; - char name[64]; - - /* - * NOTE: This will really not work well if those are remapped - * after the PHB has created its sub regions. We could do better - * if we had a way to resize regions but we don't really care - * that much in practice as the stuff below really only happens - * once early during boot - */ - - /* Handle unmaps */ - if (memory_region_is_mapped(&stack->mmbar0) && - !(bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) { - memory_region_del_subregion(sysmem, &stack->mmbar0); - } - if (memory_region_is_mapped(&stack->mmbar1) && - !(bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) { - memory_region_del_subregion(sysmem, &stack->mmbar1); - } - if (memory_region_is_mapped(&stack->phbbar) && - !(bar_en & PEC_NEST_STK_BAR_EN_PHB)) { - memory_region_del_subregion(sysmem, &stack->phbbar); - } - if (memory_region_is_mapped(&stack->intbar) && - !(bar_en & PEC_NEST_STK_BAR_EN_INT)) { - memory_region_del_subregion(sysmem, &stack->intbar); - } - - /* Update PHB */ - pnv_phb4_update_regions(stack); - - /* Handle maps */ - if (!memory_region_is_mapped(&stack->mmbar0) && - (bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) { - bar =3D stack->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8; - mask =3D stack->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK]; - size =3D ((~mask) >> 8) + 1; - snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio0", - pec->chip_id, pec->index, stack->stack_no); - memory_region_init(&stack->mmbar0, OBJECT(stack), name, size); - memory_region_add_subregion(sysmem, bar, &stack->mmbar0); - stack->mmio0_base =3D bar; - stack->mmio0_size =3D size; - } - if (!memory_region_is_mapped(&stack->mmbar1) && - (bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) { - bar =3D stack->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8; - mask =3D stack->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK]; - size =3D ((~mask) >> 8) + 1; - snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio1", - pec->chip_id, pec->index, stack->stack_no); - memory_region_init(&stack->mmbar1, OBJECT(stack), name, size); - memory_region_add_subregion(sysmem, bar, &stack->mmbar1); - stack->mmio1_base =3D bar; - stack->mmio1_size =3D size; - } - if (!memory_region_is_mapped(&stack->phbbar) && - (bar_en & PEC_NEST_STK_BAR_EN_PHB)) { - bar =3D stack->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8; - size =3D PNV_PHB4_NUM_REGS << 3; - snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-phb", - pec->chip_id, pec->index, stack->stack_no); - memory_region_init(&stack->phbbar, OBJECT(stack), name, size); - memory_region_add_subregion(sysmem, bar, &stack->phbbar); - } - if (!memory_region_is_mapped(&stack->intbar) && - (bar_en & PEC_NEST_STK_BAR_EN_INT)) { - bar =3D stack->nest_regs[PEC_NEST_STK_INT_BAR] >> 8; - size =3D PNV_PHB4_MAX_INTs << 16; - snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-int", - stack->pec->chip_id, stack->pec->index, stack->stack_no); - memory_region_init(&stack->intbar, OBJECT(stack), name, size); - memory_region_add_subregion(sysmem, bar, &stack->intbar); - } - - /* Update PHB */ - pnv_phb4_update_regions(stack); -} - -static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(opaque); - PnvPhb4PecState *pec =3D stack->pec; - uint32_t reg =3D addr >> 3; - - switch (reg) { - case PEC_NEST_STK_PCI_NEST_FIR: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] =3D val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_CLR: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &=3D val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_SET: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |=3D val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_MSK: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] =3D val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_MSKC: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &=3D val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_MSKS: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] |=3D val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_ACT0: - case PEC_NEST_STK_PCI_NEST_FIR_ACT1: - stack->nest_regs[reg] =3D val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_WOF: - stack->nest_regs[reg] =3D 0; - break; - case PEC_NEST_STK_ERR_REPORT_0: - case PEC_NEST_STK_ERR_REPORT_1: - case PEC_NEST_STK_PBCQ_GNRL_STATUS: - /* Flag error ? */ - break; - case PEC_NEST_STK_PBCQ_MODE: - stack->nest_regs[reg] =3D val & 0xff00000000000000ull; - break; - case PEC_NEST_STK_MMIO_BAR0: - case PEC_NEST_STK_MMIO_BAR0_MASK: - case PEC_NEST_STK_MMIO_BAR1: - case PEC_NEST_STK_MMIO_BAR1_MASK: - if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & - (PEC_NEST_STK_BAR_EN_MMIO0 | - PEC_NEST_STK_BAR_EN_MMIO1)) { - phb_pec_error(pec, "Changing enabled BAR unsupported\n"); - } - stack->nest_regs[reg] =3D val & 0xffffffffff000000ull; - break; - case PEC_NEST_STK_PHB_REGS_BAR: - if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PH= B) { - phb_pec_error(pec, "Changing enabled BAR unsupported\n"); - } - stack->nest_regs[reg] =3D val & 0xffffffffffc00000ull; - break; - case PEC_NEST_STK_INT_BAR: - if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_IN= T) { - phb_pec_error(pec, "Changing enabled BAR unsupported\n"); - } - stack->nest_regs[reg] =3D val & 0xfffffff000000000ull; - break; - case PEC_NEST_STK_BAR_EN: - stack->nest_regs[reg] =3D val & 0xf000000000000000ull; - pnv_pec_stk_update_map(stack); - break; - case PEC_NEST_STK_DATA_FRZ_TYPE: - case PEC_NEST_STK_PBCQ_TUN_BAR: - /* Not used for now */ - stack->nest_regs[reg] =3D val; - break; - default: - qemu_log_mask(LOG_UNIMP, "phb4_pec: nest_xscom_write 0x%"HWADDR_PR= Ix - "=3D%"PRIx64"\n", addr, val); - } -} - -static const MemoryRegionOps pnv_pec_stk_nest_xscom_ops =3D { - .read =3D pnv_pec_stk_nest_xscom_read, - .write =3D pnv_pec_stk_nest_xscom_write, - .valid.min_access_size =3D 8, - .valid.max_access_size =3D 8, - .impl.min_access_size =3D 8, - .impl.max_access_size =3D 8, - .endianness =3D DEVICE_BIG_ENDIAN, -}; - -static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, hwaddr addr, - unsigned size) -{ - PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(opaque); - uint32_t reg =3D addr >> 3; - - /* TODO: add list of allowed registers and error out if not */ - return stack->pci_regs[reg]; -} - -static void pnv_pec_stk_pci_xscom_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(opaque); - uint32_t reg =3D addr >> 3; - - switch (reg) { - case PEC_PCI_STK_PCI_FIR: - stack->nest_regs[reg] =3D val; - break; - case PEC_PCI_STK_PCI_FIR_CLR: - stack->nest_regs[PEC_PCI_STK_PCI_FIR] &=3D val; - break; - case PEC_PCI_STK_PCI_FIR_SET: - stack->nest_regs[PEC_PCI_STK_PCI_FIR] |=3D val; - break; - case PEC_PCI_STK_PCI_FIR_MSK: - stack->nest_regs[reg] =3D val; - break; - case PEC_PCI_STK_PCI_FIR_MSKC: - stack->nest_regs[PEC_PCI_STK_PCI_FIR_MSK] &=3D val; - break; - case PEC_PCI_STK_PCI_FIR_MSKS: - stack->nest_regs[PEC_PCI_STK_PCI_FIR_MSK] |=3D val; - break; - case PEC_PCI_STK_PCI_FIR_ACT0: - case PEC_PCI_STK_PCI_FIR_ACT1: - stack->nest_regs[reg] =3D val; - break; - case PEC_PCI_STK_PCI_FIR_WOF: - stack->nest_regs[reg] =3D 0; - break; - case PEC_PCI_STK_ETU_RESET: - stack->nest_regs[reg] =3D val & 0x8000000000000000ull; - /* TODO: Implement reset */ - break; - case PEC_PCI_STK_PBAIB_ERR_REPORT: - break; - case PEC_PCI_STK_PBAIB_TX_CMD_CRED: - case PEC_PCI_STK_PBAIB_TX_DAT_CRED: - stack->nest_regs[reg] =3D val; - break; - default: - qemu_log_mask(LOG_UNIMP, "phb4_pec_stk: pci_xscom_write 0x%"HWADDR= _PRIx - "=3D%"PRIx64"\n", addr, val); - } -} - -static const MemoryRegionOps pnv_pec_stk_pci_xscom_ops =3D { - .read =3D pnv_pec_stk_pci_xscom_read, - .write =3D pnv_pec_stk_pci_xscom_write, - .valid.min_access_size =3D 8, - .valid.max_access_size =3D 8, - .impl.min_access_size =3D 8, - .impl.max_access_size =3D 8, - .endianness =3D DEVICE_BIG_ENDIAN, -}; - static void pnv_pec_instance_init(Object *obj) { PnvPhb4PecState *pec =3D PNV_PHB4_PEC(obj); @@ -539,32 +287,7 @@ static void pnv_pec_stk_realize(DeviceState *dev, Erro= r **errp) PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(dev); PnvPhb4PecState *pec =3D stack->pec; PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_GET_CLASS(pec); - PnvChip *chip =3D pec->chip; int phb_id =3D pnv_phb4_pec_get_phb_id(pec, stack->stack_no); - uint32_t pec_nest_base; - uint32_t pec_pci_base; - char name[64]; - - assert(pec); - - /* Initialize the XSCOM regions for the stack registers */ - snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest-stack-%d", - pec->chip_id, pec->index, stack->stack_no); - pnv_xscom_region_init(&stack->nest_regs_mr, OBJECT(stack), - &pnv_pec_stk_nest_xscom_ops, stack, name, - PHB4_PEC_NEST_STK_REGS_COUNT); - - snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d", - pec->chip_id, pec->index, stack->stack_no); - pnv_xscom_region_init(&stack->pci_regs_mr, OBJECT(stack), - &pnv_pec_stk_pci_xscom_ops, stack, name, - PHB4_PEC_PCI_STK_REGS_COUNT); - - /* PHB pass-through */ - snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d-phb", - pec->chip_id, pec->index, stack->stack_no); - pnv_xscom_region_init(&stack->phb_regs_mr, OBJECT(&stack->phb), - &pnv_phb4_xscom_ops, &stack->phb, name, 0x40); =20 object_property_set_int(OBJECT(&stack->phb), "chip-id", pec->chip_id, &error_fatal); @@ -577,21 +300,6 @@ static void pnv_pec_stk_realize(DeviceState *dev, Erro= r **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&stack->phb), errp)) { return; } - - pec_nest_base =3D pecc->xscom_nest_base(pec); - pec_pci_base =3D pecc->xscom_pci_base(pec); - - /* Populate the XSCOM address space. */ - pnv_xscom_add_subregion(chip, - pec_nest_base + 0x40 * (stack->stack_no + 1), - &stack->nest_regs_mr); - pnv_xscom_add_subregion(chip, - pec_pci_base + 0x40 * (stack->stack_no + 1), - &stack->pci_regs_mr); - pnv_xscom_add_subregion(chip, - pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + - 0x40 * stack->stack_no, - &stack->phb_regs_mr); } =20 static Property pnv_pec_stk_properties[] =3D { --=20 2.33.1 From nobody Sat May 4 02:02:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ugUtWpAHRMF5nzUo/rvlJcah7cbaFYhJwimtBiXs0uY=; b=EocSlElYw9ic3kuM6Y6qQ1jjmfGoKLfLcULPZk/r/Sw9n6LBVAREsDbPku82057LPq io2IO2RsHM08TuiAdlfvLnS17iSegakIkwzysPUu99aIOLngSCTM5TN4EW9f0dAvHd7n RzCokdaSP836KTDkom2dxhDrUlo9O3/M1jwwEUIvtUFtaQ/l3qZqxlkJR0J100pVy0KJ ilfzWdvgp/hd9RZewZswU9QGLfS+izvoVqfkTNh2oS3pxxc8f1H4BxHksHM2MJoCt9LE lRQKJ2L9kNfzP4ktwzC1YFztJA+BL6bCDJyyGfM+xofAqP7H58WZXCYHgU3c98qA3skX Qu8Q== X-Gm-Message-State: AOAM530kvJhsXJ5ul3i5TtMj9mvsxoh2yzranCQ3WhI24huUWssMyWAn SuM/scBlJo5+i0+5wSxAt214/6kORfKnzWw0 X-Google-Smtp-Source: ABdhPJxLytYMnUg4wasI0VvaT9LT4wfvIjDMteikxUoNZoSI9sxosRVIKyj/8NfPRrWSGhJXjYjubA== X-Received: by 2002:ab0:7c5c:: with SMTP id d28mr2045139uaw.123.1641906641137; Tue, 11 Jan 2022 05:10:41 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v5 3/5] ppc/pnv: turn 'phb' into a pointer in struct PnvPhb4PecStack Date: Tue, 11 Jan 2022 10:10:25 -0300 Message-Id: <20220111131027.599784-4-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220111131027.599784-1-danielhb413@gmail.com> References: <20220111131027.599784-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::934 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::934; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x934.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641909886820100001 At this moment, stack->phb is the plain PnvPHB4 device itself instead of a pointer to the device. This will present a problem when adding user creatable devices because we can't deal with this struct and the realize() callback from the user creatable device. We can't get rid of this attribute, similar to what we did when enabling pnv-phb3 user creatable devices, because pnv_phb4_update_regions() needs to access stack->phb to do its job. This function is called twice in pnv_pec_stk_update_map(), which is one of the nested xscom write callbacks (via pnv_pec_stk_nest_xscom_write()). In fact, pnv_pec_stk_update_map() code comment is explicit about how the order of the unmap/map operations relates with the PHB subregions. All of this indicates that this code is tied together in a way that we either go on a crusade, featuring lots of refactories and redesign and considerable pain, to decouple stack and phb mapping, or we allow stack update_map operations to access the associated PHB as it is today even after introducing pnv-phb4 user devices. This patch chooses the latter. Instead of getting rid of stack->phb, turn it into a PHB pointer. This will allow us to assign an user created PHB to an existing stack later. In this process, pnv_pec_stk_instance_init() is removed because stack->phb is being initialized in stk_realize() instead. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb4.c | 2 +- hw/pci-host/pnv_phb4_pec.c | 20 +++++++------------- include/hw/pci-host/pnv_phb4.h | 7 +++++-- 3 files changed, 13 insertions(+), 16 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 94fd8c858d..ee046725ac 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1728,7 +1728,7 @@ type_init(pnv_phb4_register_types); =20 void pnv_phb4_update_regions(PnvPhb4PecStack *stack) { - PnvPHB4 *phb =3D &stack->phb; + PnvPHB4 *phb =3D stack->phb; =20 /* Unmap first always */ if (memory_region_is_mapped(&phb->mr_regs)) { diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index bf0fdf33fd..d4c52a5d28 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -275,13 +275,6 @@ static const TypeInfo pnv_pec_type_info =3D { } }; =20 -static void pnv_pec_stk_instance_init(Object *obj) -{ - PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(obj); - - object_initialize_child(obj, "phb", &stack->phb, TYPE_PNV_PHB4); -} - static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) { PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(dev); @@ -289,15 +282,17 @@ static void pnv_pec_stk_realize(DeviceState *dev, Err= or **errp) PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_GET_CLASS(pec); int phb_id =3D pnv_phb4_pec_get_phb_id(pec, stack->stack_no); =20 - object_property_set_int(OBJECT(&stack->phb), "chip-id", pec->chip_id, + stack->phb =3D PNV_PHB4(qdev_new(TYPE_PNV_PHB4)); + + object_property_set_int(OBJECT(stack->phb), "chip-id", pec->chip_id, &error_fatal); - object_property_set_int(OBJECT(&stack->phb), "index", phb_id, + object_property_set_int(OBJECT(stack->phb), "index", phb_id, &error_fatal); - object_property_set_int(OBJECT(&stack->phb), "version", pecc->version, + object_property_set_int(OBJECT(stack->phb), "version", pecc->version, &error_fatal); - object_property_set_link(OBJECT(&stack->phb), "stack", OBJECT(stack), + object_property_set_link(OBJECT(stack->phb), "stack", OBJECT(stack), &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(&stack->phb), errp)) { + if (!sysbus_realize(SYS_BUS_DEVICE(stack->phb), errp)) { return; } } @@ -324,7 +319,6 @@ static const TypeInfo pnv_pec_stk_type_info =3D { .name =3D TYPE_PNV_PHB4_PEC_STACK, .parent =3D TYPE_DEVICE, .instance_size =3D sizeof(PnvPhb4PecStack), - .instance_init =3D pnv_pec_stk_instance_init, .class_init =3D pnv_pec_stk_class_init, .interfaces =3D (InterfaceInfo[]) { { TYPE_PNV_XSCOM_INTERFACE }, diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 5ee996ebc6..82f054cf21 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -177,8 +177,11 @@ struct PnvPhb4PecStack { /* The owner PEC */ PnvPhb4PecState *pec; =20 - /* The actual PHB */ - PnvPHB4 phb; + /* + * PHB4 pointer. pnv_phb4_update_regions() needs to access + * the PHB4 via a PnvPhb4PecStack pointer. + */ + PnvPHB4 *phb; }; =20 struct PnvPhb4PecState { --=20 2.33.1 From nobody Sat May 4 02:02:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" This patch introduces pnv-phb4 user creatable devices that are created in a similar manner as pnv-phb3 devices, allowing the user to interact with the PHBs directly instead of creating PCI Express Controllers that will create a certain amount of PHBs per controller index. We accomplish this by doing the following: - add a pnv_phb4_get_stack() helper to retrieve which stack an user created phb4 would occupy; - when dealing with an user created pnv-phb4 (detected by checking if phb->stack is NULL at the start of phb4_realize()), retrieve its stack and initialize its properties as done in stk_realize(); - use 'defaults_enabled()' in stk_realize() to avoid creating and initializing a 'stack->phb' qdev that might be overwritten by an user created pnv-phb4 device. This process is wrapped into a new helper called pnv_pec_stk_default_phb_realize(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: C=C3=A9dric Le Goater --- hw/pci-host/pnv_phb4.c | 74 ++++++++++++++++++++++++++++++++++++-- hw/pci-host/pnv_phb4_pec.c | 17 +++++++-- hw/ppc/pnv.c | 2 ++ 3 files changed, 89 insertions(+), 4 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index ee046725ac..ca2f4078e5 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1487,15 +1487,85 @@ static void pnv_phb4_instance_init(Object *obj) object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE); } =20 +static PnvPhb4PecStack *pnv_phb4_get_stack(PnvChip *chip, PnvPHB4 *phb, + Error **errp) +{ + Pnv9Chip *chip9 =3D PNV9_CHIP(chip); + int chip_id =3D phb->chip_id; + int index =3D phb->phb_id; + int i, j; + + for (i =3D 0; i < chip->num_pecs; i++) { + /* + * For each PEC, check the amount of stacks it supports + * and see if the given phb4 index matches a stack. + */ + PnvPhb4PecState *pec =3D &chip9->pecs[i]; + + for (j =3D 0; j < pec->num_stacks; j++) { + if (index =3D=3D pnv_phb4_pec_get_phb_id(pec, j)) { + return &pec->stacks[j]; + } + } + } + + error_setg(errp, + "pnv-phb4 chip-id %d index %d didn't match any existing PEC= ", + chip_id, index); + + return NULL; +} + static void pnv_phb4_realize(DeviceState *dev, Error **errp) { PnvPHB4 *phb =3D PNV_PHB4(dev); PCIHostState *pci =3D PCI_HOST_BRIDGE(dev); XiveSource *xsrc =3D &phb->xsrc; + Error *local_err =3D NULL; int nr_irqs; char name[32]; =20 - assert(phb->stack); + /* User created PHB */ + if (!phb->stack) { + PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); + PnvChip *chip =3D pnv_get_chip(pnv, phb->chip_id); + PnvPhb4PecClass *pecc; + BusState *s; + + if (!chip) { + error_setg(errp, "invalid chip id: %d", phb->chip_id); + return; + } + + phb->stack =3D pnv_phb4_get_stack(chip, phb, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + /* All other phb properties but 'version' are already set */ + pecc =3D PNV_PHB4_PEC_GET_CLASS(phb->stack->pec); + object_property_set_int(OBJECT(phb), "version", pecc->version, + &error_fatal); + + /* + * Assign stack->phb since pnv_phb4_update_regions() uses it + * to access the phb. + */ + phb->stack->phb =3D phb; + + /* + * Reparent user created devices to the chip to build + * correctly the device tree. + */ + pnv_chip_parent_fixup(chip, OBJECT(phb), phb->phb_id); + + s =3D qdev_get_parent_bus(DEVICE(chip)); + if (!qdev_set_parent_bus(DEVICE(phb), s, &local_err)) { + error_propagate(errp, local_err); + return; + } + } =20 /* Set the "big_phb" flag */ phb->big_phb =3D phb->phb_id =3D=3D 0 || phb->phb_id =3D=3D 3; @@ -1600,7 +1670,7 @@ static void pnv_phb4_class_init(ObjectClass *klass, v= oid *data) dc->realize =3D pnv_phb4_realize; device_class_set_props(dc, pnv_phb4_properties); set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->user_creatable =3D false; + dc->user_creatable =3D true; =20 xfc->notify =3D pnv_phb4_xive_notify; } diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index d4c52a5d28..7fe7f1f007 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -19,6 +19,7 @@ #include "hw/pci/pci_bus.h" #include "hw/ppc/pnv.h" #include "hw/qdev-properties.h" +#include "sysemu/sysemu.h" =20 #include =20 @@ -275,9 +276,9 @@ static const TypeInfo pnv_pec_type_info =3D { } }; =20 -static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) +static void pnv_pec_stk_default_phb_realize(PnvPhb4PecStack *stack, + Error **errp) { - PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(dev); PnvPhb4PecState *pec =3D stack->pec; PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_GET_CLASS(pec); int phb_id =3D pnv_phb4_pec_get_phb_id(pec, stack->stack_no); @@ -292,11 +293,23 @@ static void pnv_pec_stk_realize(DeviceState *dev, Err= or **errp) &error_fatal); object_property_set_link(OBJECT(stack->phb), "stack", OBJECT(stack), &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(stack->phb), errp)) { return; } } =20 +static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) +{ + PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(dev); + + if (!defaults_enabled()) { + return; + } + + pnv_pec_stk_default_phb_realize(stack, errp); +} + static Property pnv_pec_stk_properties[] =3D { DEFINE_PROP_UINT32("stack-no", PnvPhb4PecStack, stack_no, 0), DEFINE_PROP_LINK("pec", PnvPhb4PecStack, pec, TYPE_PNV_PHB4_PEC, diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index fe7e67e73a..837146a2fb 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1960,6 +1960,8 @@ static void pnv_machine_power9_class_init(ObjectClass= *oc, void *data) pmc->compat =3D compat; pmc->compat_size =3D sizeof(compat); pmc->dt_power_mgt =3D pnv_dt_power_mgt; + + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB4); } =20 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) --=20 2.33.1 From nobody Sat May 4 02:02:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641910250487154.80654283166814; Tue, 11 Jan 2022 06:10:50 -0800 (PST) Received: from localhost ([::1]:42276 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n7HrN-0001DG-F5 for importer@patchew.org; Tue, 11 Jan 2022 09:10:49 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54334) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n7GvS-0003nl-RN; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::92d (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::92d; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x92d.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641910253402100001 Its only callers are inside pnv_phb4.c. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb4.c | 52 +++++++++++++++++----------------- include/hw/pci-host/pnv_phb4.h | 1 - 2 files changed, 26 insertions(+), 27 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index ca2f4078e5..30e609d78e 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -868,6 +868,32 @@ static uint64_t pnv_pec_stk_nest_xscom_read(void *opaq= ue, hwaddr addr, return stack->nest_regs[reg]; } =20 +static void pnv_phb4_update_regions(PnvPhb4PecStack *stack) +{ + PnvPHB4 *phb =3D stack->phb; + + /* Unmap first always */ + if (memory_region_is_mapped(&phb->mr_regs)) { + memory_region_del_subregion(&stack->phbbar, &phb->mr_regs); + } + if (memory_region_is_mapped(&phb->xsrc.esb_mmio)) { + memory_region_del_subregion(&stack->intbar, &phb->xsrc.esb_mmio); + } + + /* Map registers if enabled */ + if (memory_region_is_mapped(&stack->phbbar)) { + memory_region_add_subregion(&stack->phbbar, 0, &phb->mr_regs); + } + + /* Map ESB if enabled */ + if (memory_region_is_mapped(&stack->intbar)) { + memory_region_add_subregion(&stack->intbar, 0, &phb->xsrc.esb_mmio= ); + } + + /* Check/update m32 */ + pnv_phb4_check_all_mbt(phb); +} + static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack) { PnvPhb4PecState *pec =3D stack->pec; @@ -1796,32 +1822,6 @@ static void pnv_phb4_register_types(void) =20 type_init(pnv_phb4_register_types); =20 -void pnv_phb4_update_regions(PnvPhb4PecStack *stack) -{ - PnvPHB4 *phb =3D stack->phb; - - /* Unmap first always */ - if (memory_region_is_mapped(&phb->mr_regs)) { - memory_region_del_subregion(&stack->phbbar, &phb->mr_regs); - } - if (memory_region_is_mapped(&phb->xsrc.esb_mmio)) { - memory_region_del_subregion(&stack->intbar, &phb->xsrc.esb_mmio); - } - - /* Map registers if enabled */ - if (memory_region_is_mapped(&stack->phbbar)) { - memory_region_add_subregion(&stack->phbbar, 0, &phb->mr_regs); - } - - /* Map ESB if enabled */ - if (memory_region_is_mapped(&stack->intbar)) { - memory_region_add_subregion(&stack->intbar, 0, &phb->xsrc.esb_mmio= ); - } - - /* Check/update m32 */ - pnv_phb4_check_all_mbt(phb); -} - void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon) { uint32_t offset =3D phb->regs[PHB_INT_NOTIFY_INDEX >> 3]; diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 82f054cf21..4b7ce8a723 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -131,7 +131,6 @@ struct PnvPHB4 { }; =20 void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon); -void pnv_phb4_update_regions(PnvPhb4PecStack *stack); int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index); extern const MemoryRegionOps pnv_phb4_xscom_ops; =20 --=20 2.33.1