From nobody Thu May 2 19:04:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641863050260415.56944149596757; Mon, 10 Jan 2022 17:04:10 -0800 (PST) Received: from localhost ([::1]:53132 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n75a5-000886-4X for importer@patchew.org; Mon, 10 Jan 2022 20:04:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58230) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n75SQ-0007rn-K4; Mon, 10 Jan 2022 19:56:16 -0500 Received: from [2607:f8b0:4864:20::929] (port=42622 helo=mail-ua1-x929.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n75SN-0003pe-Aq; Mon, 10 Jan 2022 19:56:14 -0500 Received: by mail-ua1-x929.google.com with SMTP id p1so26867643uap.9; Mon, 10 Jan 2022 16:56:10 -0800 (PST) Received: from rekt.COMFAST ([152.249.109.193]) by smtp.gmail.com with ESMTPSA id x190sm4645562vkf.56.2022.01.10.16.56.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 16:56:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7iKHpUcdC7fmMFDj5oY1t0/24e0sDOIq68C6F5HZzTk=; b=qYO97sYA7ElOsHU8iJSdR71B4rPQgC3roKwJ1Wy0nyR8Ef32CKgU00x1XBLwUQJdUh Rp5Kyr4quXt0vJHQYlSbK8hqiTekfkNk2UNIRD2Uoea02BMnrmmaxmnsiqyJYLyxEgBZ nTCndferWL3SiZZdtzpoc7d6lJBQcVOhkD1sGoYK89pSPSsZsMrgG79w6JUs5dlwLtJS GLtSEQtA0TuiLslX+6WCwrlptqjwc0YyANW3Qzxgx8L/sE3kfaEHHi9nUWdRjLfkg5Qa gtwLPrghmc97WwB90tSuKtB0N+1/pyW/giN+PjTyHnH2RZ1twc4JZurjyN1HIaVC2Vn5 MaBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7iKHpUcdC7fmMFDj5oY1t0/24e0sDOIq68C6F5HZzTk=; b=acV1uQ4dauZNvRwUFKCWZZyMnL3++SSTE6DbUpP92ksbLPg35r5cZQFCWekJbTYVAE PwgrIDLj1noI2BgjnBWlNLKD8ee3oBtx6KPC1r9qX28u/9y9uu8ZHLj5lMXFMkXKqMqJ pk2pTjZIRktOkHmSPo25W3qwo7ZVtq78AXm20uX28hun6+eYLUJvozRQ0j/kZVOqGMGN OeOKkOClQ92wJDirdzRPKqTUBlKHYuY+mlk7Qa+gmyJmUaxuAJvowLGTqmbnOMBXD1QX 6QKN8xeVvjR3eWL9WyuL4TgtJNtO0Z+rwYIKt/k0J6AyDrv19Whqmavb1WLFFmy58pHs XvQQ== X-Gm-Message-State: AOAM531cmzJR8vur7E2/iLZQiP0IFGaPBITfPwDFLOhFirMoxLb5bb3U ai+ywrVvHfvmWklxa9UJxx+UlgTnh9Qgs4ju X-Google-Smtp-Source: ABdhPJxU6we1oiASy/C03qX2J+/0o6hNYJsjO4NbInW4bSWS6xvx1A7UU79VbG1zc1HGxA/t9K3rgg== X-Received: by 2002:a05:6102:3708:: with SMTP id s8mr1064488vst.56.1641862569556; Mon, 10 Jan 2022 16:56:09 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v4 1/5] ppc/pnv: set phb4 properties in stk_realize() Date: Mon, 10 Jan 2022 21:55:54 -0300 Message-Id: <20220111005558.549685-2-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220111005558.549685-1-danielhb413@gmail.com> References: <20220111005558.549685-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::929 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::929; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x929.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641863051294100001 Content-Type: text/plain; charset="utf-8" Moving all phb4 properties setup to stk_realize() keeps this logic in a single place instead of having it scattered between stk_realize() and pec_realize(). 'phb->index' can be retrieved using stack->stack_no and pnv_phb4_pec_get_phb_id(), deprecating the use of 'phb-id' alias that was being used for this purpose in pec_realize(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: C=C3=A9dric Le Goater --- hw/pci-host/pnv_phb4_pec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index d64310e7db..f8038dff17 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -392,10 +392,8 @@ static void pnv_pec_realize(DeviceState *dev, Error **= errp) for (i =3D 0; i < pec->num_stacks; i++) { PnvPhb4PecStack *stack =3D &pec->stacks[i]; Object *stk_obj =3D OBJECT(stack); - int phb_id =3D pnv_phb4_pec_get_phb_id(pec, i); =20 object_property_set_int(stk_obj, "stack-no", i, &error_abort); - object_property_set_int(stk_obj, "phb-id", phb_id, &error_abort); object_property_set_link(stk_obj, "pec", OBJECT(pec), &error_abort= ); if (!qdev_realize(DEVICE(stk_obj), NULL, errp)) { return; @@ -534,7 +532,6 @@ static void pnv_pec_stk_instance_init(Object *obj) PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(obj); =20 object_initialize_child(obj, "phb", &stack->phb, TYPE_PNV_PHB4); - object_property_add_alias(obj, "phb-id", OBJECT(&stack->phb), "index"); } =20 static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) @@ -543,6 +540,7 @@ static void pnv_pec_stk_realize(DeviceState *dev, Error= **errp) PnvPhb4PecState *pec =3D stack->pec; PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_GET_CLASS(pec); PnvChip *chip =3D pec->chip; + int phb_id =3D pnv_phb4_pec_get_phb_id(pec, stack->stack_no); uint32_t pec_nest_base; uint32_t pec_pci_base; char name[64]; @@ -570,6 +568,8 @@ static void pnv_pec_stk_realize(DeviceState *dev, Error= **errp) =20 object_property_set_int(OBJECT(&stack->phb), "chip-id", pec->chip_id, &error_fatal); + object_property_set_int(OBJECT(&stack->phb), "index", phb_id, + &error_fatal); object_property_set_int(OBJECT(&stack->phb), "version", pecc->version, &error_fatal); object_property_set_link(OBJECT(&stack->phb), "stack", OBJECT(stack), --=20 2.33.1 From nobody Thu May 2 19:04:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::936; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x936.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641862782843100003 Content-Type: text/plain; charset="utf-8" The 'stack->phb_regs_mr' PHB4 passthrough XSCOM initialization relies on 'stack->phb' being not NULL. Moving 'stack->phb_regs_mr' region_init() and add_subregion() to phb4_realize() time is a natural thing to do since it's strictly PHB related. The remaining XSCOM initialization is also related to 'stack->phb' but in a different manner. For instance, 'stack->nest_regs_mr' MemoryRegionOps, 'pnv_pec_stk_nest_xscom_ops', uses pnv_pec_stk_nest_xscom_write() as a write callback. When trying to write the PEC_NEST_STK_BAR_EN reg, pnv_pec_stk_update_map() is called. Inside this function, pnv_phb4_update_regions() is called twice. This function uses 'stack->phb' to manipulate memory regions of the phb. This is not a problem now but, when enabling user creatable phb4s, a stack that doesn't have an associated phb (i.e. stack->phb =3D NULL) it will cause a SIGINT during boot in pnv_phb4_update_regions(). All this can be avoided if all XSCOM init is moved to phb4_realize(), when we have certainty about the existence of 'stack->phb'. A lot of code was moved from pnv_phb4_pec.c to pnv_phb4.c due to static constant and variables being used but the cleaner logic is worth the trouble. Signed-off-by: Daniel Henrique Barboza Reviewed-by: C=C3=A9dric Le Goater --- hw/pci-host/pnv_phb4.c | 304 +++++++++++++++++++++++++++++++++++++ hw/pci-host/pnv_phb4_pec.c | 292 ----------------------------------- 2 files changed, 304 insertions(+), 292 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index b7b0091f93..1bd74fd932 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -29,6 +29,10 @@ qemu_log_mask(LOG_GUEST_ERROR, "phb4[%d:%d]: " fmt "\n", \ (phb)->chip_id, (phb)->phb_id, ## __VA_ARGS__) =20 +#define phb_pec_error(pec, fmt, ...) \ + qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n", \ + (pec)->chip_id, (pec)->index, ## __VA_ARGS__) + /* * QEMU version of the GETFIELD/SETFIELD macros * @@ -854,6 +858,258 @@ const MemoryRegionOps pnv_phb4_xscom_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 +static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr, + unsigned size) +{ + PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(opaque); + uint32_t reg =3D addr >> 3; + + /* TODO: add list of allowed registers and error out if not */ + return stack->nest_regs[reg]; +} + +static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack) +{ + PnvPhb4PecState *pec =3D stack->pec; + MemoryRegion *sysmem =3D get_system_memory(); + uint64_t bar_en =3D stack->nest_regs[PEC_NEST_STK_BAR_EN]; + uint64_t bar, mask, size; + char name[64]; + + /* + * NOTE: This will really not work well if those are remapped + * after the PHB has created its sub regions. We could do better + * if we had a way to resize regions but we don't really care + * that much in practice as the stuff below really only happens + * once early during boot + */ + + /* Handle unmaps */ + if (memory_region_is_mapped(&stack->mmbar0) && + !(bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) { + memory_region_del_subregion(sysmem, &stack->mmbar0); + } + if (memory_region_is_mapped(&stack->mmbar1) && + !(bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) { + memory_region_del_subregion(sysmem, &stack->mmbar1); + } + if (memory_region_is_mapped(&stack->phbbar) && + !(bar_en & PEC_NEST_STK_BAR_EN_PHB)) { + memory_region_del_subregion(sysmem, &stack->phbbar); + } + if (memory_region_is_mapped(&stack->intbar) && + !(bar_en & PEC_NEST_STK_BAR_EN_INT)) { + memory_region_del_subregion(sysmem, &stack->intbar); + } + + /* Update PHB */ + pnv_phb4_update_regions(stack); + + /* Handle maps */ + if (!memory_region_is_mapped(&stack->mmbar0) && + (bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) { + bar =3D stack->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8; + mask =3D stack->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK]; + size =3D ((~mask) >> 8) + 1; + snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio0", + pec->chip_id, pec->index, stack->stack_no); + memory_region_init(&stack->mmbar0, OBJECT(stack), name, size); + memory_region_add_subregion(sysmem, bar, &stack->mmbar0); + stack->mmio0_base =3D bar; + stack->mmio0_size =3D size; + } + if (!memory_region_is_mapped(&stack->mmbar1) && + (bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) { + bar =3D stack->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8; + mask =3D stack->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK]; + size =3D ((~mask) >> 8) + 1; + snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio1", + pec->chip_id, pec->index, stack->stack_no); + memory_region_init(&stack->mmbar1, OBJECT(stack), name, size); + memory_region_add_subregion(sysmem, bar, &stack->mmbar1); + stack->mmio1_base =3D bar; + stack->mmio1_size =3D size; + } + if (!memory_region_is_mapped(&stack->phbbar) && + (bar_en & PEC_NEST_STK_BAR_EN_PHB)) { + bar =3D stack->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8; + size =3D PNV_PHB4_NUM_REGS << 3; + snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-phb", + pec->chip_id, pec->index, stack->stack_no); + memory_region_init(&stack->phbbar, OBJECT(stack), name, size); + memory_region_add_subregion(sysmem, bar, &stack->phbbar); + } + if (!memory_region_is_mapped(&stack->intbar) && + (bar_en & PEC_NEST_STK_BAR_EN_INT)) { + bar =3D stack->nest_regs[PEC_NEST_STK_INT_BAR] >> 8; + size =3D PNV_PHB4_MAX_INTs << 16; + snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-int", + stack->pec->chip_id, stack->pec->index, stack->stack_no); + memory_region_init(&stack->intbar, OBJECT(stack), name, size); + memory_region_add_subregion(sysmem, bar, &stack->intbar); + } + + /* Update PHB */ + pnv_phb4_update_regions(stack); +} + +static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(opaque); + PnvPhb4PecState *pec =3D stack->pec; + uint32_t reg =3D addr >> 3; + + switch (reg) { + case PEC_NEST_STK_PCI_NEST_FIR: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] =3D val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_CLR: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &=3D val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_SET: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |=3D val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_MSK: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] =3D val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_MSKC: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &=3D val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_MSKS: + stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] |=3D val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_ACT0: + case PEC_NEST_STK_PCI_NEST_FIR_ACT1: + stack->nest_regs[reg] =3D val; + break; + case PEC_NEST_STK_PCI_NEST_FIR_WOF: + stack->nest_regs[reg] =3D 0; + break; + case PEC_NEST_STK_ERR_REPORT_0: + case PEC_NEST_STK_ERR_REPORT_1: + case PEC_NEST_STK_PBCQ_GNRL_STATUS: + /* Flag error ? */ + break; + case PEC_NEST_STK_PBCQ_MODE: + stack->nest_regs[reg] =3D val & 0xff00000000000000ull; + break; + case PEC_NEST_STK_MMIO_BAR0: + case PEC_NEST_STK_MMIO_BAR0_MASK: + case PEC_NEST_STK_MMIO_BAR1: + case PEC_NEST_STK_MMIO_BAR1_MASK: + if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & + (PEC_NEST_STK_BAR_EN_MMIO0 | + PEC_NEST_STK_BAR_EN_MMIO1)) { + phb_pec_error(pec, "Changing enabled BAR unsupported\n"); + } + stack->nest_regs[reg] =3D val & 0xffffffffff000000ull; + break; + case PEC_NEST_STK_PHB_REGS_BAR: + if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PH= B) { + phb_pec_error(pec, "Changing enabled BAR unsupported\n"); + } + stack->nest_regs[reg] =3D val & 0xffffffffffc00000ull; + break; + case PEC_NEST_STK_INT_BAR: + if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_IN= T) { + phb_pec_error(pec, "Changing enabled BAR unsupported\n"); + } + stack->nest_regs[reg] =3D val & 0xfffffff000000000ull; + break; + case PEC_NEST_STK_BAR_EN: + stack->nest_regs[reg] =3D val & 0xf000000000000000ull; + pnv_pec_stk_update_map(stack); + break; + case PEC_NEST_STK_DATA_FRZ_TYPE: + case PEC_NEST_STK_PBCQ_TUN_BAR: + /* Not used for now */ + stack->nest_regs[reg] =3D val; + break; + default: + qemu_log_mask(LOG_UNIMP, "phb4_pec: nest_xscom_write 0x%"HWADDR_PR= Ix + "=3D%"PRIx64"\n", addr, val); + } +} + +static const MemoryRegionOps pnv_pec_stk_nest_xscom_ops =3D { + .read =3D pnv_pec_stk_nest_xscom_read, + .write =3D pnv_pec_stk_nest_xscom_write, + .valid.min_access_size =3D 8, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, hwaddr addr, + unsigned size) +{ + PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(opaque); + uint32_t reg =3D addr >> 3; + + /* TODO: add list of allowed registers and error out if not */ + return stack->pci_regs[reg]; +} + +static void pnv_pec_stk_pci_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(opaque); + uint32_t reg =3D addr >> 3; + + switch (reg) { + case PEC_PCI_STK_PCI_FIR: + stack->nest_regs[reg] =3D val; + break; + case PEC_PCI_STK_PCI_FIR_CLR: + stack->nest_regs[PEC_PCI_STK_PCI_FIR] &=3D val; + break; + case PEC_PCI_STK_PCI_FIR_SET: + stack->nest_regs[PEC_PCI_STK_PCI_FIR] |=3D val; + break; + case PEC_PCI_STK_PCI_FIR_MSK: + stack->nest_regs[reg] =3D val; + break; + case PEC_PCI_STK_PCI_FIR_MSKC: + stack->nest_regs[PEC_PCI_STK_PCI_FIR_MSK] &=3D val; + break; + case PEC_PCI_STK_PCI_FIR_MSKS: + stack->nest_regs[PEC_PCI_STK_PCI_FIR_MSK] |=3D val; + break; + case PEC_PCI_STK_PCI_FIR_ACT0: + case PEC_PCI_STK_PCI_FIR_ACT1: + stack->nest_regs[reg] =3D val; + break; + case PEC_PCI_STK_PCI_FIR_WOF: + stack->nest_regs[reg] =3D 0; + break; + case PEC_PCI_STK_ETU_RESET: + stack->nest_regs[reg] =3D val & 0x8000000000000000ull; + /* TODO: Implement reset */ + break; + case PEC_PCI_STK_PBAIB_ERR_REPORT: + break; + case PEC_PCI_STK_PBAIB_TX_CMD_CRED: + case PEC_PCI_STK_PBAIB_TX_DAT_CRED: + stack->nest_regs[reg] =3D val; + break; + default: + qemu_log_mask(LOG_UNIMP, "phb4_pec_stk: pci_xscom_write 0x%"HWADDR= _PRIx + "=3D%"PRIx64"\n", addr, val); + } +} + +static const MemoryRegionOps pnv_pec_stk_pci_xscom_ops =3D { + .read =3D pnv_pec_stk_pci_xscom_read, + .write =3D pnv_pec_stk_pci_xscom_write, + .valid.min_access_size =3D 8, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + static int pnv_phb4_map_irq(PCIDevice *pci_dev, int irq_num) { /* Check that out properly ... */ @@ -1175,6 +1431,52 @@ int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, in= t stack_index) return offset + stack_index; } =20 +static void pnv_phb4_XSCOM_init(PnvPHB4 *phb) +{ + PnvPhb4PecStack *stack =3D phb->stack; + PnvPhb4PecState *pec =3D stack->pec; + PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_GET_CLASS(pec); + uint32_t pec_nest_base; + uint32_t pec_pci_base; + char name[64]; + + assert(pec); + + /* Initialize the XSCOM regions for the stack registers */ + snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest-stack-%d", + pec->chip_id, pec->index, stack->stack_no); + pnv_xscom_region_init(&stack->nest_regs_mr, OBJECT(stack), + &pnv_pec_stk_nest_xscom_ops, stack, name, + PHB4_PEC_NEST_STK_REGS_COUNT); + + snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d", + pec->chip_id, pec->index, stack->stack_no); + pnv_xscom_region_init(&stack->pci_regs_mr, OBJECT(stack), + &pnv_pec_stk_pci_xscom_ops, stack, name, + PHB4_PEC_PCI_STK_REGS_COUNT); + + /* PHB pass-through */ + snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d-phb", + pec->chip_id, pec->index, stack->stack_no); + pnv_xscom_region_init(&stack->phb_regs_mr, OBJECT(phb), + &pnv_phb4_xscom_ops, phb, name, 0x40); + + pec_nest_base =3D pecc->xscom_nest_base(pec); + pec_pci_base =3D pecc->xscom_pci_base(pec); + + /* Populate the XSCOM address space. */ + pnv_xscom_add_subregion(pec->chip, + pec_nest_base + 0x40 * (stack->stack_no + 1), + &stack->nest_regs_mr); + pnv_xscom_add_subregion(pec->chip, + pec_pci_base + 0x40 * (stack->stack_no + 1), + &stack->pci_regs_mr); + pnv_xscom_add_subregion(pec->chip, + pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + + 0x40 * stack->stack_no, + &stack->phb_regs_mr); +} + static void pnv_phb4_instance_init(Object *obj) { PnvPHB4 *phb =3D PNV_PHB4(obj); @@ -1195,6 +1497,8 @@ static void pnv_phb4_realize(DeviceState *dev, Error = **errp) =20 assert(phb->stack); =20 + pnv_phb4_XSCOM_init(phb); + /* Set the "big_phb" flag */ phb->big_phb =3D phb->phb_id =3D=3D 0 || phb->phb_id =3D=3D 3; =20 diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index f8038dff17..bf0fdf33fd 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -111,258 +111,6 @@ static const MemoryRegionOps pnv_pec_pci_xscom_ops = =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr, - unsigned size) -{ - PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(opaque); - uint32_t reg =3D addr >> 3; - - /* TODO: add list of allowed registers and error out if not */ - return stack->nest_regs[reg]; -} - -static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack) -{ - PnvPhb4PecState *pec =3D stack->pec; - MemoryRegion *sysmem =3D get_system_memory(); - uint64_t bar_en =3D stack->nest_regs[PEC_NEST_STK_BAR_EN]; - uint64_t bar, mask, size; - char name[64]; - - /* - * NOTE: This will really not work well if those are remapped - * after the PHB has created its sub regions. We could do better - * if we had a way to resize regions but we don't really care - * that much in practice as the stuff below really only happens - * once early during boot - */ - - /* Handle unmaps */ - if (memory_region_is_mapped(&stack->mmbar0) && - !(bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) { - memory_region_del_subregion(sysmem, &stack->mmbar0); - } - if (memory_region_is_mapped(&stack->mmbar1) && - !(bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) { - memory_region_del_subregion(sysmem, &stack->mmbar1); - } - if (memory_region_is_mapped(&stack->phbbar) && - !(bar_en & PEC_NEST_STK_BAR_EN_PHB)) { - memory_region_del_subregion(sysmem, &stack->phbbar); - } - if (memory_region_is_mapped(&stack->intbar) && - !(bar_en & PEC_NEST_STK_BAR_EN_INT)) { - memory_region_del_subregion(sysmem, &stack->intbar); - } - - /* Update PHB */ - pnv_phb4_update_regions(stack); - - /* Handle maps */ - if (!memory_region_is_mapped(&stack->mmbar0) && - (bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) { - bar =3D stack->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8; - mask =3D stack->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK]; - size =3D ((~mask) >> 8) + 1; - snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio0", - pec->chip_id, pec->index, stack->stack_no); - memory_region_init(&stack->mmbar0, OBJECT(stack), name, size); - memory_region_add_subregion(sysmem, bar, &stack->mmbar0); - stack->mmio0_base =3D bar; - stack->mmio0_size =3D size; - } - if (!memory_region_is_mapped(&stack->mmbar1) && - (bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) { - bar =3D stack->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8; - mask =3D stack->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK]; - size =3D ((~mask) >> 8) + 1; - snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio1", - pec->chip_id, pec->index, stack->stack_no); - memory_region_init(&stack->mmbar1, OBJECT(stack), name, size); - memory_region_add_subregion(sysmem, bar, &stack->mmbar1); - stack->mmio1_base =3D bar; - stack->mmio1_size =3D size; - } - if (!memory_region_is_mapped(&stack->phbbar) && - (bar_en & PEC_NEST_STK_BAR_EN_PHB)) { - bar =3D stack->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8; - size =3D PNV_PHB4_NUM_REGS << 3; - snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-phb", - pec->chip_id, pec->index, stack->stack_no); - memory_region_init(&stack->phbbar, OBJECT(stack), name, size); - memory_region_add_subregion(sysmem, bar, &stack->phbbar); - } - if (!memory_region_is_mapped(&stack->intbar) && - (bar_en & PEC_NEST_STK_BAR_EN_INT)) { - bar =3D stack->nest_regs[PEC_NEST_STK_INT_BAR] >> 8; - size =3D PNV_PHB4_MAX_INTs << 16; - snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-int", - stack->pec->chip_id, stack->pec->index, stack->stack_no); - memory_region_init(&stack->intbar, OBJECT(stack), name, size); - memory_region_add_subregion(sysmem, bar, &stack->intbar); - } - - /* Update PHB */ - pnv_phb4_update_regions(stack); -} - -static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(opaque); - PnvPhb4PecState *pec =3D stack->pec; - uint32_t reg =3D addr >> 3; - - switch (reg) { - case PEC_NEST_STK_PCI_NEST_FIR: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] =3D val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_CLR: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &=3D val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_SET: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |=3D val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_MSK: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] =3D val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_MSKC: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &=3D val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_MSKS: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] |=3D val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_ACT0: - case PEC_NEST_STK_PCI_NEST_FIR_ACT1: - stack->nest_regs[reg] =3D val; - break; - case PEC_NEST_STK_PCI_NEST_FIR_WOF: - stack->nest_regs[reg] =3D 0; - break; - case PEC_NEST_STK_ERR_REPORT_0: - case PEC_NEST_STK_ERR_REPORT_1: - case PEC_NEST_STK_PBCQ_GNRL_STATUS: - /* Flag error ? */ - break; - case PEC_NEST_STK_PBCQ_MODE: - stack->nest_regs[reg] =3D val & 0xff00000000000000ull; - break; - case PEC_NEST_STK_MMIO_BAR0: - case PEC_NEST_STK_MMIO_BAR0_MASK: - case PEC_NEST_STK_MMIO_BAR1: - case PEC_NEST_STK_MMIO_BAR1_MASK: - if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & - (PEC_NEST_STK_BAR_EN_MMIO0 | - PEC_NEST_STK_BAR_EN_MMIO1)) { - phb_pec_error(pec, "Changing enabled BAR unsupported\n"); - } - stack->nest_regs[reg] =3D val & 0xffffffffff000000ull; - break; - case PEC_NEST_STK_PHB_REGS_BAR: - if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PH= B) { - phb_pec_error(pec, "Changing enabled BAR unsupported\n"); - } - stack->nest_regs[reg] =3D val & 0xffffffffffc00000ull; - break; - case PEC_NEST_STK_INT_BAR: - if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_IN= T) { - phb_pec_error(pec, "Changing enabled BAR unsupported\n"); - } - stack->nest_regs[reg] =3D val & 0xfffffff000000000ull; - break; - case PEC_NEST_STK_BAR_EN: - stack->nest_regs[reg] =3D val & 0xf000000000000000ull; - pnv_pec_stk_update_map(stack); - break; - case PEC_NEST_STK_DATA_FRZ_TYPE: - case PEC_NEST_STK_PBCQ_TUN_BAR: - /* Not used for now */ - stack->nest_regs[reg] =3D val; - break; - default: - qemu_log_mask(LOG_UNIMP, "phb4_pec: nest_xscom_write 0x%"HWADDR_PR= Ix - "=3D%"PRIx64"\n", addr, val); - } -} - -static const MemoryRegionOps pnv_pec_stk_nest_xscom_ops =3D { - .read =3D pnv_pec_stk_nest_xscom_read, - .write =3D pnv_pec_stk_nest_xscom_write, - .valid.min_access_size =3D 8, - .valid.max_access_size =3D 8, - .impl.min_access_size =3D 8, - .impl.max_access_size =3D 8, - .endianness =3D DEVICE_BIG_ENDIAN, -}; - -static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, hwaddr addr, - unsigned size) -{ - PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(opaque); - uint32_t reg =3D addr >> 3; - - /* TODO: add list of allowed registers and error out if not */ - return stack->pci_regs[reg]; -} - -static void pnv_pec_stk_pci_xscom_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(opaque); - uint32_t reg =3D addr >> 3; - - switch (reg) { - case PEC_PCI_STK_PCI_FIR: - stack->nest_regs[reg] =3D val; - break; - case PEC_PCI_STK_PCI_FIR_CLR: - stack->nest_regs[PEC_PCI_STK_PCI_FIR] &=3D val; - break; - case PEC_PCI_STK_PCI_FIR_SET: - stack->nest_regs[PEC_PCI_STK_PCI_FIR] |=3D val; - break; - case PEC_PCI_STK_PCI_FIR_MSK: - stack->nest_regs[reg] =3D val; - break; - case PEC_PCI_STK_PCI_FIR_MSKC: - stack->nest_regs[PEC_PCI_STK_PCI_FIR_MSK] &=3D val; - break; - case PEC_PCI_STK_PCI_FIR_MSKS: - stack->nest_regs[PEC_PCI_STK_PCI_FIR_MSK] |=3D val; - break; - case PEC_PCI_STK_PCI_FIR_ACT0: - case PEC_PCI_STK_PCI_FIR_ACT1: - stack->nest_regs[reg] =3D val; - break; - case PEC_PCI_STK_PCI_FIR_WOF: - stack->nest_regs[reg] =3D 0; - break; - case PEC_PCI_STK_ETU_RESET: - stack->nest_regs[reg] =3D val & 0x8000000000000000ull; - /* TODO: Implement reset */ - break; - case PEC_PCI_STK_PBAIB_ERR_REPORT: - break; - case PEC_PCI_STK_PBAIB_TX_CMD_CRED: - case PEC_PCI_STK_PBAIB_TX_DAT_CRED: - stack->nest_regs[reg] =3D val; - break; - default: - qemu_log_mask(LOG_UNIMP, "phb4_pec_stk: pci_xscom_write 0x%"HWADDR= _PRIx - "=3D%"PRIx64"\n", addr, val); - } -} - -static const MemoryRegionOps pnv_pec_stk_pci_xscom_ops =3D { - .read =3D pnv_pec_stk_pci_xscom_read, - .write =3D pnv_pec_stk_pci_xscom_write, - .valid.min_access_size =3D 8, - .valid.max_access_size =3D 8, - .impl.min_access_size =3D 8, - .impl.max_access_size =3D 8, - .endianness =3D DEVICE_BIG_ENDIAN, -}; - static void pnv_pec_instance_init(Object *obj) { PnvPhb4PecState *pec =3D PNV_PHB4_PEC(obj); @@ -539,32 +287,7 @@ static void pnv_pec_stk_realize(DeviceState *dev, Erro= r **errp) PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(dev); PnvPhb4PecState *pec =3D stack->pec; PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_GET_CLASS(pec); - PnvChip *chip =3D pec->chip; int phb_id =3D pnv_phb4_pec_get_phb_id(pec, stack->stack_no); - uint32_t pec_nest_base; - uint32_t pec_pci_base; - char name[64]; - - assert(pec); - - /* Initialize the XSCOM regions for the stack registers */ - snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest-stack-%d", - pec->chip_id, pec->index, stack->stack_no); - pnv_xscom_region_init(&stack->nest_regs_mr, OBJECT(stack), - &pnv_pec_stk_nest_xscom_ops, stack, name, - PHB4_PEC_NEST_STK_REGS_COUNT); - - snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d", - pec->chip_id, pec->index, stack->stack_no); - pnv_xscom_region_init(&stack->pci_regs_mr, OBJECT(stack), - &pnv_pec_stk_pci_xscom_ops, stack, name, - PHB4_PEC_PCI_STK_REGS_COUNT); - - /* PHB pass-through */ - snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d-phb", - pec->chip_id, pec->index, stack->stack_no); - pnv_xscom_region_init(&stack->phb_regs_mr, OBJECT(&stack->phb), - &pnv_phb4_xscom_ops, &stack->phb, name, 0x40); =20 object_property_set_int(OBJECT(&stack->phb), "chip-id", pec->chip_id, &error_fatal); @@ -577,21 +300,6 @@ static void pnv_pec_stk_realize(DeviceState *dev, Erro= r **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&stack->phb), errp)) { return; } - - pec_nest_base =3D pecc->xscom_nest_base(pec); - pec_pci_base =3D pecc->xscom_pci_base(pec); - - /* Populate the XSCOM address space. */ - pnv_xscom_add_subregion(chip, - pec_nest_base + 0x40 * (stack->stack_no + 1), - &stack->nest_regs_mr); - pnv_xscom_add_subregion(chip, - pec_pci_base + 0x40 * (stack->stack_no + 1), - &stack->pci_regs_mr); - pnv_xscom_add_subregion(chip, - pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + - 0x40 * stack->stack_no, - &stack->phb_regs_mr); } =20 static Property pnv_pec_stk_properties[] =3D { --=20 2.33.1 From nobody Thu May 2 19:04:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" At this moment, stack->phb is the plain PnvPHB4 device itself instead of a pointer to the device. This will present a problem when adding user creatable devices because we can't deal with this struct and the realize() callback from the user creatable device. We can't get rid of this attribute, similar to what we did when enabling pnv-phb3 user creatable devices, because pnv_phb4_update_regions() needs to access stack->phb to do its job. This function is called twice in pnv_pec_stk_update_map(), which is one of the nested xscom write callbacks (via pnv_pec_stk_nest_xscom_write()). In fact, pnv_pec_stk_update_map() code comment is explicit about how the order of the unmap/map operations relates with the PHB subregions. All of this indicates that this code is tied together in a way that we either go on a crusade, featuring lots of refactories and redesign and considerable pain, to decouple stack and phb mapping, or we allow stack update_map operations to access the associated PHB as it is today even after introducing pnv-phb4 user devices. This patch chooses the latter. Instead of getting rid of stack->phb, turn it into a PHB pointer. This will allow us to assign an user created PHB to an existing stack later. In this process, pnv_pec_stk_instance_init() is removed because stack->phb is being initialized in stk_realize() instead. Signed-off-by: Daniel Henrique Barboza Reviewed-by: C=C3=A9dric Le Goater --- hw/pci-host/pnv_phb4.c | 2 +- hw/pci-host/pnv_phb4_pec.c | 20 +++++++------------- include/hw/pci-host/pnv_phb4.h | 7 +++++-- 3 files changed, 13 insertions(+), 16 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 1bd74fd932..3ffa8f51e9 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1728,7 +1728,7 @@ type_init(pnv_phb4_register_types); =20 void pnv_phb4_update_regions(PnvPhb4PecStack *stack) { - PnvPHB4 *phb =3D &stack->phb; + PnvPHB4 *phb =3D stack->phb; =20 /* Unmap first always */ if (memory_region_is_mapped(&phb->mr_regs)) { diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index bf0fdf33fd..d4c52a5d28 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -275,13 +275,6 @@ static const TypeInfo pnv_pec_type_info =3D { } }; =20 -static void pnv_pec_stk_instance_init(Object *obj) -{ - PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(obj); - - object_initialize_child(obj, "phb", &stack->phb, TYPE_PNV_PHB4); -} - static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) { PnvPhb4PecStack *stack =3D PNV_PHB4_PEC_STACK(dev); @@ -289,15 +282,17 @@ static void pnv_pec_stk_realize(DeviceState *dev, Err= or **errp) PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_GET_CLASS(pec); int phb_id =3D pnv_phb4_pec_get_phb_id(pec, stack->stack_no); =20 - object_property_set_int(OBJECT(&stack->phb), "chip-id", pec->chip_id, + stack->phb =3D PNV_PHB4(qdev_new(TYPE_PNV_PHB4)); + + object_property_set_int(OBJECT(stack->phb), "chip-id", pec->chip_id, &error_fatal); - object_property_set_int(OBJECT(&stack->phb), "index", phb_id, + object_property_set_int(OBJECT(stack->phb), "index", phb_id, &error_fatal); - object_property_set_int(OBJECT(&stack->phb), "version", pecc->version, + object_property_set_int(OBJECT(stack->phb), "version", pecc->version, &error_fatal); - object_property_set_link(OBJECT(&stack->phb), "stack", OBJECT(stack), + object_property_set_link(OBJECT(stack->phb), "stack", OBJECT(stack), &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(&stack->phb), errp)) { + if (!sysbus_realize(SYS_BUS_DEVICE(stack->phb), errp)) { return; } } @@ -324,7 +319,6 @@ static const TypeInfo pnv_pec_stk_type_info =3D { .name =3D TYPE_PNV_PHB4_PEC_STACK, .parent =3D TYPE_DEVICE, .instance_size =3D sizeof(PnvPhb4PecStack), - .instance_init =3D pnv_pec_stk_instance_init, .class_init =3D pnv_pec_stk_class_init, .interfaces =3D (InterfaceInfo[]) { { TYPE_PNV_XSCOM_INTERFACE }, diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 5ee996ebc6..82f054cf21 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -177,8 +177,11 @@ struct PnvPhb4PecStack { /* The owner PEC */ PnvPhb4PecState *pec; =20 - /* The actual PHB */ - PnvPHB4 phb; + /* + * PHB4 pointer. pnv_phb4_update_regions() needs to access + * the PHB4 via a PnvPhb4PecStack pointer. + */ + PnvPHB4 *phb; }; =20 struct PnvPhb4PecState { --=20 2.33.1 From nobody Thu May 2 19:04:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" This patch introduces pnv-phb4 user creatable devices that are created in a similar manner as pnv-phb3 devices, allowing the user to interact with the PHBs directly instead of creating PCI Express Controllers that will create a certain amount of PHBs per controller index. We accomplish this by doing the following: - add a pnv_phb4_get_stack() helper to retrieve which stack an user created phb4 would occupy; - when dealing with an user created pnv-phb4 (detected by checking if phb->stack is NULL at the start of phb4_realize()), retrieve its stack and initialize its properties as done in stk_realize(); - use 'defaults_enabled()' in stk_realize() to avoid creating and initializing a 'stack->phb' qdev that might be overwritten by an user created pnv-phb4 device. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb4.c | 75 +++++++++++++++++++++++++++++++++++++- hw/pci-host/pnv_phb4_pec.c | 5 +++ hw/ppc/pnv.c | 2 + 3 files changed, 80 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 3ffa8f51e9..10f8d6a919 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1487,15 +1487,86 @@ static void pnv_phb4_instance_init(Object *obj) object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE); } =20 +static PnvPhb4PecStack *pnv_phb4_get_stack(int chip_id, int index, + Error **errp) +{ + PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); + PnvChip *chip =3D pnv_get_chip(pnv, chip_id); + Pnv9Chip *chip9 =3D PNV9_CHIP(chip); + int i, j; + + for (i =3D 0; i < chip->num_pecs; i++) { + /* + * For each PEC, check the amount of stacks it supports + * and see if the given phb4 index matches a stack. + */ + PnvPhb4PecState *pec =3D &chip9->pecs[i]; + + for (j =3D 0; j < pec->num_stacks; j++) { + if (index =3D=3D pnv_phb4_pec_get_phb_id(pec, j)) { + return &pec->stacks[j]; + } + } + } + + error_setg(errp, + "pnv-phb4 chip-id %d index %d didn't match any existing PEC= ", + chip_id, index); + + return NULL; +} + static void pnv_phb4_realize(DeviceState *dev, Error **errp) { PnvPHB4 *phb =3D PNV_PHB4(dev); PCIHostState *pci =3D PCI_HOST_BRIDGE(dev); XiveSource *xsrc =3D &phb->xsrc; + Error *local_err =3D NULL; int nr_irqs; char name[32]; =20 - assert(phb->stack); + /* User created PHB */ + if (!phb->stack) { + PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); + PnvChip *chip =3D pnv_get_chip(pnv, phb->chip_id); + PnvPhb4PecClass *pecc; + BusState *s; + + if (!chip) { + error_setg(errp, "invalid chip id: %d", phb->chip_id); + return; + } + + phb->stack =3D pnv_phb4_get_stack(phb->chip_id, phb->phb_id, + &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + /* All other phb properties but 'version' are already set */ + pecc =3D PNV_PHB4_PEC_GET_CLASS(phb->stack->pec); + object_property_set_int(OBJECT(phb), "version", pecc->version, + &error_fatal); + + /* + * Assign stack->phb since pnv_phb4_update_regions() uses it + * to access the phb. + */ + phb->stack->phb =3D phb; + + /* + * Reparent user created devices to the chip to build + * correctly the device tree. + */ + pnv_chip_parent_fixup(chip, OBJECT(phb), phb->phb_id); + + s =3D qdev_get_parent_bus(DEVICE(chip)); + if (!qdev_set_parent_bus(DEVICE(phb), s, &local_err)) { + error_propagate(errp, local_err); + return; + } + } =20 pnv_phb4_XSCOM_init(phb); =20 @@ -1600,7 +1671,7 @@ static void pnv_phb4_class_init(ObjectClass *klass, v= oid *data) dc->realize =3D pnv_phb4_realize; device_class_set_props(dc, pnv_phb4_properties); set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->user_creatable =3D false; + dc->user_creatable =3D true; =20 xfc->notify =3D pnv_phb4_xive_notify; } diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index d4c52a5d28..dfd25831d5 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -19,6 +19,7 @@ #include "hw/pci/pci_bus.h" #include "hw/ppc/pnv.h" #include "hw/qdev-properties.h" +#include "sysemu/sysemu.h" =20 #include =20 @@ -282,6 +283,10 @@ static void pnv_pec_stk_realize(DeviceState *dev, Erro= r **errp) PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_GET_CLASS(pec); int phb_id =3D pnv_phb4_pec_get_phb_id(pec, stack->stack_no); =20 + if (!defaults_enabled()) { + return; + } + stack->phb =3D PNV_PHB4(qdev_new(TYPE_PNV_PHB4)); =20 object_property_set_int(OBJECT(stack->phb), "chip-id", pec->chip_id, diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index fe7e67e73a..837146a2fb 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1960,6 +1960,8 @@ static void pnv_machine_power9_class_init(ObjectClass= *oc, void *data) pmc->compat =3D compat; pmc->compat_size =3D sizeof(compat); pmc->dt_power_mgt =3D pnv_dt_power_mgt; + + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB4); } =20 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) --=20 2.33.1 From nobody Thu May 2 19:04:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641863275158903.9293344016446; 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Mon, 10 Jan 2022 16:56:17 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v4 5/5] ppc/pnv: turn pnv_phb4_update_regions() into static Date: Mon, 10 Jan 2022 21:55:58 -0300 Message-Id: <20220111005558.549685-6-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220111005558.549685-1-danielhb413@gmail.com> References: <20220111005558.549685-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::92c (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::92c; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x92c.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641863276286100001 Content-Type: text/plain; charset="utf-8" Its only callers are inside pnv_phb4.c. Signed-off-by: Daniel Henrique Barboza Reviewed-by: C=C3=A9dric Le Goater --- hw/pci-host/pnv_phb4.c | 52 +++++++++++++++++----------------- include/hw/pci-host/pnv_phb4.h | 1 - 2 files changed, 26 insertions(+), 27 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 10f8d6a919..34c43bd0f5 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -868,6 +868,32 @@ static uint64_t pnv_pec_stk_nest_xscom_read(void *opaq= ue, hwaddr addr, return stack->nest_regs[reg]; } =20 +static void pnv_phb4_update_regions(PnvPhb4PecStack *stack) +{ + PnvPHB4 *phb =3D stack->phb; + + /* Unmap first always */ + if (memory_region_is_mapped(&phb->mr_regs)) { + memory_region_del_subregion(&stack->phbbar, &phb->mr_regs); + } + if (memory_region_is_mapped(&phb->xsrc.esb_mmio)) { + memory_region_del_subregion(&stack->intbar, &phb->xsrc.esb_mmio); + } + + /* Map registers if enabled */ + if (memory_region_is_mapped(&stack->phbbar)) { + memory_region_add_subregion(&stack->phbbar, 0, &phb->mr_regs); + } + + /* Map ESB if enabled */ + if (memory_region_is_mapped(&stack->intbar)) { + memory_region_add_subregion(&stack->intbar, 0, &phb->xsrc.esb_mmio= ); + } + + /* Check/update m32 */ + pnv_phb4_check_all_mbt(phb); +} + static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack) { PnvPhb4PecState *pec =3D stack->pec; @@ -1797,32 +1823,6 @@ static void pnv_phb4_register_types(void) =20 type_init(pnv_phb4_register_types); =20 -void pnv_phb4_update_regions(PnvPhb4PecStack *stack) -{ - PnvPHB4 *phb =3D stack->phb; - - /* Unmap first always */ - if (memory_region_is_mapped(&phb->mr_regs)) { - memory_region_del_subregion(&stack->phbbar, &phb->mr_regs); - } - if (memory_region_is_mapped(&phb->xsrc.esb_mmio)) { - memory_region_del_subregion(&stack->intbar, &phb->xsrc.esb_mmio); - } - - /* Map registers if enabled */ - if (memory_region_is_mapped(&stack->phbbar)) { - memory_region_add_subregion(&stack->phbbar, 0, &phb->mr_regs); - } - - /* Map ESB if enabled */ - if (memory_region_is_mapped(&stack->intbar)) { - memory_region_add_subregion(&stack->intbar, 0, &phb->xsrc.esb_mmio= ); - } - - /* Check/update m32 */ - pnv_phb4_check_all_mbt(phb); -} - void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon) { uint32_t offset =3D phb->regs[PHB_INT_NOTIFY_INDEX >> 3]; diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 82f054cf21..4b7ce8a723 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -131,7 +131,6 @@ struct PnvPHB4 { }; =20 void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon); -void pnv_phb4_update_regions(PnvPhb4PecStack *stack); int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index); extern const MemoryRegionOps pnv_phb4_xscom_ops; =20 --=20 2.33.1