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Date: Mon, 10 Jan 2022 15:40:29 +0100 Message-Id: <20220110144034.67410-14-pbonzini@redhat.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220110144034.67410-1-pbonzini@redhat.com> References: <20220110144034.67410-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::52a (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=paolo.bonzini@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Levitsky Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641827814699100001 Content-Type: text/plain; charset="utf-8" From: Maxim Levitsky This allows to make PDPTRs part of the migration stream and thus not reload them after migration which is against X86 spec. Signed-off-by: Maxim Levitsky Message-Id: <20211101132300.192584-2-mlevitsk@redhat.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 3 ++ target/i386/kvm/kvm.c | 108 +++++++++++++++++++++++++++++++++++++++++- target/i386/machine.c | 29 ++++++++++++ 3 files changed, 138 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 04f2b790c9..9911d7c871 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1455,6 +1455,9 @@ typedef struct CPUX86State { SegmentCache idt; /* only base and limit are used */ =20 target_ulong cr[5]; /* NOTE: cr1 is unused */ + + bool pdptrs_valid; + uint64_t pdptrs[4]; int32_t a20_mask; =20 BNDReg bnd_regs[4]; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 13f8e30c2a..d81745620b 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -124,6 +124,7 @@ static uint32_t num_architectural_pmu_fixed_counters; static int has_xsave; static int has_xcrs; static int has_pit_state2; +static int has_sregs2; static int has_exception_payload; =20 static bool has_msr_mcg_ext_ctl; @@ -2324,6 +2325,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s) has_xsave =3D kvm_check_extension(s, KVM_CAP_XSAVE); has_xcrs =3D kvm_check_extension(s, KVM_CAP_XCRS); has_pit_state2 =3D kvm_check_extension(s, KVM_CAP_PIT_STATE2); + has_sregs2 =3D kvm_check_extension(s, KVM_CAP_SREGS2) > 0; =20 hv_vpindex_settable =3D kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX= ); =20 @@ -2650,6 +2652,61 @@ static int kvm_put_sregs(X86CPU *cpu) return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); } =20 +static int kvm_put_sregs2(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + struct kvm_sregs2 sregs; + int i; + + sregs.flags =3D 0; + + if ((env->eflags & VM_MASK)) { + set_v8086_seg(&sregs.cs, &env->segs[R_CS]); + set_v8086_seg(&sregs.ds, &env->segs[R_DS]); + set_v8086_seg(&sregs.es, &env->segs[R_ES]); + set_v8086_seg(&sregs.fs, &env->segs[R_FS]); + set_v8086_seg(&sregs.gs, &env->segs[R_GS]); + set_v8086_seg(&sregs.ss, &env->segs[R_SS]); + } else { + set_seg(&sregs.cs, &env->segs[R_CS]); + set_seg(&sregs.ds, &env->segs[R_DS]); + set_seg(&sregs.es, &env->segs[R_ES]); + set_seg(&sregs.fs, &env->segs[R_FS]); + set_seg(&sregs.gs, &env->segs[R_GS]); + set_seg(&sregs.ss, &env->segs[R_SS]); + } + + set_seg(&sregs.tr, &env->tr); + set_seg(&sregs.ldt, &env->ldt); + + sregs.idt.limit =3D env->idt.limit; + sregs.idt.base =3D env->idt.base; + memset(sregs.idt.padding, 0, sizeof sregs.idt.padding); + sregs.gdt.limit =3D env->gdt.limit; + sregs.gdt.base =3D env->gdt.base; + memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding); + + sregs.cr0 =3D env->cr[0]; + sregs.cr2 =3D env->cr[2]; + sregs.cr3 =3D env->cr[3]; + sregs.cr4 =3D env->cr[4]; + + sregs.cr8 =3D cpu_get_apic_tpr(cpu->apic_state); + sregs.apic_base =3D cpu_get_apic_base(cpu->apic_state); + + sregs.efer =3D env->efer; + + if (env->pdptrs_valid) { + for (i =3D 0; i < 4; i++) { + sregs.pdptrs[i] =3D env->pdptrs[i]; + } + sregs.flags |=3D KVM_SREGS2_FLAGS_PDPTRS_VALID; + } + + return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS2, &sregs); +} + + static void kvm_msr_buf_reset(X86CPU *cpu) { memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE); @@ -3330,6 +3387,53 @@ static int kvm_get_sregs(X86CPU *cpu) return 0; } =20 +static int kvm_get_sregs2(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + struct kvm_sregs2 sregs; + int i, ret; + + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS2, &sregs); + if (ret < 0) { + return ret; + } + + get_seg(&env->segs[R_CS], &sregs.cs); + get_seg(&env->segs[R_DS], &sregs.ds); + get_seg(&env->segs[R_ES], &sregs.es); + get_seg(&env->segs[R_FS], &sregs.fs); + get_seg(&env->segs[R_GS], &sregs.gs); + get_seg(&env->segs[R_SS], &sregs.ss); + + get_seg(&env->tr, &sregs.tr); + get_seg(&env->ldt, &sregs.ldt); + + env->idt.limit =3D sregs.idt.limit; + env->idt.base =3D sregs.idt.base; + env->gdt.limit =3D sregs.gdt.limit; + env->gdt.base =3D sregs.gdt.base; + + env->cr[0] =3D sregs.cr0; + env->cr[2] =3D sregs.cr2; + env->cr[3] =3D sregs.cr3; + env->cr[4] =3D sregs.cr4; + + env->efer =3D sregs.efer; + + env->pdptrs_valid =3D sregs.flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; + + if (env->pdptrs_valid) { + for (i =3D 0; i < 4; i++) { + env->pdptrs[i] =3D sregs.pdptrs[i]; + } + } + + /* changes to apic base and cr8/tpr are read back via kvm_arch_post_ru= n */ + x86_update_hflags(env); + + return 0; +} + static int kvm_get_msrs(X86CPU *cpu) { CPUX86State *env =3D &cpu->env; @@ -4173,7 +4277,7 @@ int kvm_arch_put_registers(CPUState *cpu, int level) assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); =20 /* must be before kvm_put_nested_state so that EFER.SVME is set */ - ret =3D kvm_put_sregs(x86_cpu); + ret =3D has_sregs2 ? kvm_put_sregs2(x86_cpu) : kvm_put_sregs(x86_cpu); if (ret < 0) { return ret; } @@ -4278,7 +4382,7 @@ int kvm_arch_get_registers(CPUState *cs) if (ret < 0) { goto out; } - ret =3D kvm_get_sregs(cpu); + ret =3D has_sregs2 ? kvm_get_sregs2(cpu) : kvm_get_sregs(cpu); if (ret < 0) { goto out; } diff --git a/target/i386/machine.c b/target/i386/machine.c index 83c2b91529..6202f47793 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1451,6 +1451,34 @@ static const VMStateDescription vmstate_msr_intel_sg= x =3D { .needed =3D intel_sgx_msrs_needed, .fields =3D (VMStateField[]) { VMSTATE_UINT64_ARRAY(env.msr_ia32_sgxlepubkeyhash, X86CPU, 4), + VMSTATE_END_OF_LIST() + } + }; + +static bool pdptrs_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + return env->pdptrs_valid; +} + +static int pdptrs_post_load(void *opaque, int version_id) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + env->pdptrs_valid =3D true; + return 0; +} + + +static const VMStateDescription vmstate_pdptrs =3D { + .name =3D "cpu/pdptrs", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pdptrs_needed, + .post_load =3D pdptrs_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_ARRAY(env.pdptrs, X86CPU, 4), VMSTATE_END_OF_LIST() } }; @@ -1593,6 +1621,7 @@ const VMStateDescription vmstate_x86_cpu =3D { #endif &vmstate_msr_tsx_ctrl, &vmstate_msr_intel_sgx, + &vmstate_pdptrs, NULL } }; --=20 2.33.1