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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=002fe4623=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1641791879264100001 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa This change fixes a bug where a write only register is read. As per https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table the 'INTR_TEST0' register is write only. Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/timer/ibex_timer.c | 14 +++++--------- include/hw/timer/ibex_timer.h | 1 - 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c index 66e1f8e48c..826c38b653 100644 --- a/hw/timer/ibex_timer.c +++ b/hw/timer/ibex_timer.c @@ -130,7 +130,6 @@ static void ibex_timer_reset(DeviceState *dev) s->timer_compare_upper0 =3D 0xFFFFFFFF; s->timer_intr_enable =3D 0x00000000; s->timer_intr_state =3D 0x00000000; - s->timer_intr_test =3D 0x00000000; =20 ibex_timer_update_irqs(s); } @@ -168,7 +167,8 @@ static uint64_t ibex_timer_read(void *opaque, hwaddr ad= dr, retvalue =3D s->timer_intr_state; break; case R_INTR_TEST: - retvalue =3D s->timer_intr_test; + qemu_log_mask(LOG_GUEST_ERROR, + "Attempted to read INTR_TEST, a write only register"= ); break; default: qemu_log_mask(LOG_GUEST_ERROR, @@ -215,10 +215,7 @@ static void ibex_timer_write(void *opaque, hwaddr addr, s->timer_intr_state &=3D ~val; break; case R_INTR_TEST: - s->timer_intr_test =3D val; - if (s->timer_intr_enable & - s->timer_intr_test & - R_INTR_ENABLE_IE_0_MASK) { + if (s->timer_intr_enable & val & R_INTR_ENABLE_IE_0_MASK) { s->timer_intr_state |=3D R_INTR_STATE_IS_0_MASK; qemu_set_irq(s->irq, true); } @@ -247,8 +244,8 @@ static int ibex_timer_post_load(void *opaque, int versi= on_id) =20 static const VMStateDescription vmstate_ibex_timer =3D { .name =3D TYPE_IBEX_TIMER, - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .post_load =3D ibex_timer_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINT32(timer_ctrl, IbexTimerState), @@ -257,7 +254,6 @@ static const VMStateDescription vmstate_ibex_timer =3D { VMSTATE_UINT32(timer_compare_upper0, IbexTimerState), VMSTATE_UINT32(timer_intr_enable, IbexTimerState), VMSTATE_UINT32(timer_intr_state, IbexTimerState), - VMSTATE_UINT32(timer_intr_test, IbexTimerState), VMSTATE_END_OF_LIST() } }; diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h index b6f69b38ee..1a0a28d5fa 100644 --- a/include/hw/timer/ibex_timer.h +++ b/include/hw/timer/ibex_timer.h @@ -43,7 +43,6 @@ struct IbexTimerState { uint32_t timer_compare_upper0; uint32_t timer_intr_enable; uint32_t timer_intr_state; - uint32_t timer_intr_test; =20 uint32_t timebase_freq; =20 --=20 2.34.1