From nobody Mon May 6 17:08:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641625350040810.8457285411267; Fri, 7 Jan 2022 23:02:30 -0800 (PST) Received: from localhost ([::1]:50740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n65kC-0003oR-U0 for importer@patchew.org; Sat, 08 Jan 2022 02:02:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65LR-0005cU-EY for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:36:54 -0500 Received: from [2607:f8b0:4864:20::102a] (port=51756 helo=mail-pj1-x102a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65LO-00046j-Uv for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:36:53 -0500 Received: by mail-pj1-x102a.google.com with SMTP id ie13so7092404pjb.1 for ; Fri, 07 Jan 2022 22:36:50 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id z4sm840954pfh.215.2022.01.07.22.36.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:36:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CeWgoUY+FsDQQpDS8Npex8+n2m1iX//bpDjlxIIaI/o=; b=xDDvOvBButcncy5rLezFRSOnjB1adkF+JhrxwX4J5pNpHUESjCU111Lny19eKQ3NxK twjr92sZMa5kk0Jn7NFOXF29vBoCdlrA86ypmNR+2rpcOq39jVqa8p/MrjP5U0/6ikXM DZxayulTeR3AeI/IB6C3ezs/Xw5+75/39t9ehMHfge1f2s3g/EFwaw7WxzEtv+q1ANs+ bmvA9nM2dq/+4G3VAUjEtBB4E+i/p2cDUE7BWlSqMjAbOtZdce87qpG0/1c122uxwUMA DlYyUMSFHYWo4wVnBII546EQ/42dWNnsvcRtV1cscjLFRceqeyzqbc/wVlR/fDcPC4Nj sWGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CeWgoUY+FsDQQpDS8Npex8+n2m1iX//bpDjlxIIaI/o=; b=IApDBNHaB10dRAoskY7H+M90AeD+d0ctjSBRYzuA0RgEHdkfeNB7CH70Pf+gwGefKJ UKkSqlEf4FneTkZyr/m2Dx0ZQNm67ik6WOLUjm+1wHo5pvnENQuMwj5kpXpxiV6p6QFI cbDeTarxkT8Dq2fXvQZ2mpEg7zEMUFl51bKs1Pp6zj32X904WkS752FqtaEIWnf3r4MO U0kFk3xQWjxLtPNNJ6AQLxSwq/FzmmXOnoeuV3Y3azTe6ntDvIlTNmth3K1W7ANZVdNS jRD4HQJ9i9Xi+4I9n95vpPH70ZTPOMHKDm08QjIw1esniHnmZ5LOjgwSwdPsvLd39k4e xaHw== X-Gm-Message-State: AOAM532/abwGymnLW1nAJzaHNqpoy1Iy+Y850Gkm5iYTEXlSR9UiXWdw cuTKW4++D2iLbFMHB9+QtYvyv2o0L5VgGQ== X-Google-Smtp-Source: ABdhPJwPvLc3r6R2//SaJFdKssQ3gQXz1SirisuSZEOtP1q+CNgJ17Ogo20sKTNLlK6IWrxmWL83Dw== X-Received: by 2002:a17:90a:7023:: with SMTP id f32mr19410244pjk.226.1641623809409; Fri, 07 Jan 2022 22:36:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/12] tcg/mips: Support unaligned access for user-only Date: Fri, 7 Jan 2022 22:36:33 -0800 Message-Id: <20220108063644.478043-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063644.478043-1-richard.henderson@linaro.org> References: <20220108063644.478043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102a (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641625352623100001 Content-Type: text/plain; charset="utf-8" This is kinda sorta the opposite of the other tcg hosts, where we get (normal) alignment checks for free with host SIGBUS and need to add code to support unaligned accesses. Fortunately, the ISA contains pairs of instructions that are used to implement unaligned memory accesses. Use them. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 2 - tcg/mips/tcg-target.c.inc | 334 +++++++++++++++++++++++++++++++++++++- 2 files changed, 328 insertions(+), 8 deletions(-) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c366fdf74b..7669213175 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -207,8 +207,6 @@ extern bool use_mips32r2_instructions; void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t) QEMU_ERROR("code path is reachable"); =20 -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif =20 #endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index d8f6914f03..5737d8a269 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -24,6 +24,8 @@ * THE SOFTWARE. */ =20 +#include "../tcg-ldst.c.inc" + #ifdef HOST_WORDS_BIGENDIAN # define MIPS_BE 1 #else @@ -230,16 +232,26 @@ typedef enum { OPC_ORI =3D 015 << 26, OPC_XORI =3D 016 << 26, OPC_LUI =3D 017 << 26, + OPC_BNEL =3D 025 << 26, + OPC_BNEZALC_R6 =3D 030 << 26, OPC_DADDIU =3D 031 << 26, + OPC_LDL =3D 032 << 26, + OPC_LDR =3D 033 << 26, OPC_LB =3D 040 << 26, OPC_LH =3D 041 << 26, + OPC_LWL =3D 042 << 26, OPC_LW =3D 043 << 26, OPC_LBU =3D 044 << 26, OPC_LHU =3D 045 << 26, + OPC_LWR =3D 046 << 26, OPC_LWU =3D 047 << 26, OPC_SB =3D 050 << 26, OPC_SH =3D 051 << 26, + OPC_SWL =3D 052 << 26, OPC_SW =3D 053 << 26, + OPC_SDL =3D 054 << 26, + OPC_SDR =3D 055 << 26, + OPC_SWR =3D 056 << 26, OPC_LD =3D 067 << 26, OPC_SD =3D 077 << 26, =20 @@ -1015,8 +1027,6 @@ static void tcg_out_call(TCGContext *s, const tcg_ins= n_unit *arg) } =20 #if defined(CONFIG_SOFTMMU) -#include "../tcg-ldst.c.inc" - static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] =3D { [MO_UB] =3D helper_ret_ldub_mmu, [MO_SB] =3D helper_ret_ldsb_mmu, @@ -1324,7 +1334,82 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); return true; } -#endif + +#else + +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, + TCGReg addrhi, unsigned a_bits) +{ + unsigned a_mask =3D (1 << a_bits) - 1; + TCGLabelQemuLdst *l =3D new_ldst_label(s); + + l->is_ld =3D is_ld; + l->addrlo_reg =3D addrlo; + l->addrhi_reg =3D addrhi; + + /* We are expecting a_bits to max out at 7, much lower than ANDI. */ + tcg_debug_assert(a_bits < 16); + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); + + l->label_ptr[0] =3D s->code_ptr; + if (use_mips32r6_instructions) { + tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); + } else { + tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); + tcg_out_nop(s); + } + + l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + void *target; + + if (!reloc_pc16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { + return false; + } + + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + /* A0 is env, A1 is skipped, A2:A3 is the uint64_t address. */ + TCGReg a2 =3D MIPS_BE ? l->addrhi_reg : l->addrlo_reg; + TCGReg a3 =3D MIPS_BE ? l->addrlo_reg : l->addrhi_reg; + + if (a3 !=3D TCG_REG_A2) { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2); + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3); + } else if (a2 !=3D TCG_REG_A3) { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3); + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2); + } else { + tcg_out_mov(s, TCG_TYPE_I32, TCG_TMP0, TCG_REG_A2); + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, TCG_REG_A3); + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, TCG_TMP0); + } + } else { + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg); + } + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); + + /* + * Tail call to the helper, with the return address back inline. + * We have arrived here via BNEL, so $31 is already set. + */ + target =3D (l->is_ld ? helper_unaligned_ld : helper_unaligned_st); + tcg_out_call_int(s, target, true); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} +#endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, TCGReg base, MemOp opc, bool is_64) @@ -1430,6 +1515,127 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg lo, TCGReg hi, } } =20 +static void __attribute__((unused)) +tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, + TCGReg base, MemOp opc, bool is_64) +{ + const MIPSInsn lw1 =3D MIPS_BE ? OPC_LWL : OPC_LWR; + const MIPSInsn lw2 =3D MIPS_BE ? OPC_LWR : OPC_LWL; + const MIPSInsn ld1 =3D MIPS_BE ? OPC_LDL : OPC_LDR; + const MIPSInsn ld2 =3D MIPS_BE ? OPC_LDR : OPC_LDL; + + bool sgn =3D (opc & MO_SIGN); + + switch (opc & (MO_SSIZE | MO_BSWAP)) { + case MO_SW | MO_BE: + case MO_UW | MO_BE: + tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); + tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); + if (use_mips32r2_instructions) { + tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); + } else { + tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); + tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); + } + break; + + case MO_SW | MO_LE: + case MO_UW | MO_LE: + if (use_mips32r2_instructions && lo !=3D base) { + tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); + tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); + tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); + } else { + tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); + tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); + tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); + tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); + } + break; + + case MO_SL: + case MO_UL: + tcg_out_opc_imm(s, lw1, lo, base, 0); + tcg_out_opc_imm(s, lw2, lo, base, 3); + if (TCG_TARGET_REG_BITS =3D=3D 64 && is_64 && !sgn) { + tcg_out_ext32u(s, lo, lo); + } + break; + + case MO_UL | MO_BSWAP: + case MO_SL | MO_BSWAP: + if (use_mips32r2_instructions) { + tcg_out_opc_imm(s, lw1, lo, base, 0); + tcg_out_opc_imm(s, lw2, lo, base, 3); + tcg_out_bswap32(s, lo, lo, + TCG_TARGET_REG_BITS =3D=3D 64 && is_64 + ? (sgn ? TCG_BSWAP_OS : TCG_BSWAP_OZ) : 0); + } else { + const tcg_insn_unit *subr =3D + (TCG_TARGET_REG_BITS =3D=3D 64 && is_64 && !sgn + ? bswap32u_addr : bswap32_addr); + + tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0); + tcg_out_bswap_subr(s, subr); + /* delay slot */ + tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 3); + tcg_out_mov(s, is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, lo, TCG_TM= P3); + } + break; + + case MO_Q: + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_opc_imm(s, ld1, lo, base, 0); + tcg_out_opc_imm(s, ld2, lo, base, 7); + } else { + tcg_out_opc_imm(s, lw1, MIPS_BE ? hi : lo, base, 0 + 0); + tcg_out_opc_imm(s, lw2, MIPS_BE ? hi : lo, base, 0 + 3); + tcg_out_opc_imm(s, lw1, MIPS_BE ? lo : hi, base, 4 + 0); + tcg_out_opc_imm(s, lw2, MIPS_BE ? lo : hi, base, 4 + 3); + } + break; + + case MO_Q | MO_BSWAP: + if (TCG_TARGET_REG_BITS =3D=3D 64) { + if (use_mips32r2_instructions) { + tcg_out_opc_imm(s, ld1, lo, base, 0); + tcg_out_opc_imm(s, ld2, lo, base, 7); + tcg_out_bswap64(s, lo, lo); + } else { + tcg_out_opc_imm(s, ld1, TCG_TMP0, base, 0); + tcg_out_bswap_subr(s, bswap64_addr); + /* delay slot */ + tcg_out_opc_imm(s, ld2, TCG_TMP0, base, 7); + tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); + } + } else if (use_mips32r2_instructions) { + tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0); + tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3); + tcg_out_opc_imm(s, lw1, TCG_TMP1, base, 4 + 0); + tcg_out_opc_imm(s, lw2, TCG_TMP1, base, 4 + 3); + tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); + tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); + tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); + tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); + } else { + tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0); + tcg_out_bswap_subr(s, bswap32_addr); + /* delay slot */ + tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3); + tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 4 + 0); + tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); + tcg_out_bswap_subr(s, bswap32_addr); + /* delay slot */ + tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 4 + 3); + tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); + } + break; + + default: + g_assert_not_reached(); + } +} + static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) { TCGReg addr_regl, addr_regh __attribute__((unused)); @@ -1438,6 +1644,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; +#else + unsigned a_bits, s_bits; #endif TCGReg base =3D TCG_REG_A0; =20 @@ -1467,7 +1675,27 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is_64) } else { tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl= ); } - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + a_bits =3D get_alignment_bits(opc); + s_bits =3D opc & MO_SIZE; + /* + * R6 removes the left/right instructions but requires the + * system to support misaligned memory accesses. + */ + if (use_mips32r6_instructions) { + if (a_bits) { + tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); + } + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + } else { + if (a_bits && a_bits !=3D s_bits) { + tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); + } + if (a_bits >=3D s_bits) { + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_= 64); + } else { + tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is= _64); + } + } #endif } =20 @@ -1532,6 +1760,79 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TC= GReg lo, TCGReg hi, } } =20 +static void __attribute__((unused)) +tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, + TCGReg base, MemOp opc) +{ + const MIPSInsn sw1 =3D MIPS_BE ? OPC_SWL : OPC_SWR; + const MIPSInsn sw2 =3D MIPS_BE ? OPC_SWR : OPC_SWL; + const MIPSInsn sd1 =3D MIPS_BE ? OPC_SDL : OPC_SDR; + const MIPSInsn sd2 =3D MIPS_BE ? OPC_SDR : OPC_SDL; + + /* Don't clutter the code below with checks to avoid bswapping ZERO. = */ + if ((lo | hi) =3D=3D 0) { + opc &=3D ~MO_BSWAP; + } + + switch (opc & (MO_SIZE | MO_BSWAP)) { + case MO_16 | MO_BE: + tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); + tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 0); + tcg_out_opc_imm(s, OPC_SB, lo, base, 1); + break; + + case MO_16 | MO_LE: + tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); + tcg_out_opc_imm(s, OPC_SB, lo, base, 0); + tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 1); + break; + + case MO_32 | MO_BSWAP: + tcg_out_bswap32(s, TCG_TMP3, lo, 0); + lo =3D TCG_TMP3; + /* fall through */ + case MO_32: + tcg_out_opc_imm(s, sw1, lo, base, 0); + tcg_out_opc_imm(s, sw2, lo, base, 3); + break; + + case MO_64 | MO_BSWAP: + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_bswap64(s, TCG_TMP3, lo); + lo =3D TCG_TMP3; + } else if (use_mips32r2_instructions) { + tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? hi : lo); + tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? lo : hi); + tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); + tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); + hi =3D MIPS_BE ? TCG_TMP0 : TCG_TMP1; + lo =3D MIPS_BE ? TCG_TMP1 : TCG_TMP0; + } else { + tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0); + tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 0); + tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 3); + tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0); + tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 4); + tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 7); + break; + } + /* fall through */ + case MO_64: + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_opc_imm(s, sd1, lo, base, 0); + tcg_out_opc_imm(s, sd2, lo, base, 7); + } else { + tcg_out_opc_imm(s, sw1, MIPS_BE ? hi : lo, base, 0); + tcg_out_opc_imm(s, sw2, MIPS_BE ? hi : lo, base, 3); + tcg_out_opc_imm(s, sw1, MIPS_BE ? lo : hi, base, 4); + tcg_out_opc_imm(s, sw2, MIPS_BE ? lo : hi, base, 7); + } + break; + + default: + tcg_abort(); + } +} static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) { TCGReg addr_regl, addr_regh __attribute__((unused)); @@ -1540,6 +1841,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; +#else + unsigned a_bits, s_bits; #endif TCGReg base =3D TCG_REG_A0; =20 @@ -1558,7 +1861,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - base =3D TCG_REG_A0; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, base, addr_regl); addr_regl =3D base; @@ -1570,7 +1872,27 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is_64) } else { tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl= ); } - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + a_bits =3D get_alignment_bits(opc); + s_bits =3D opc & MO_SIZE; + /* + * R6 removes the left/right instructions but requires the + * system to support misaligned memory accesses. + */ + if (use_mips32r6_instructions) { + if (a_bits) { + tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); + } + tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + } else { + if (a_bits && a_bits !=3D s_bits) { + tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); + } + if (a_bits >=3D s_bits) { + tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + } else { + tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc); + } + } #endif } =20 --=20 2.25.1 From nobody Mon May 6 17:08:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641628472292710.5522200452806; Fri, 7 Jan 2022 23:54:32 -0800 (PST) Received: from localhost ([::1]:52790 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n66YY-0006iC-SS for importer@patchew.org; Sat, 08 Jan 2022 02:54:30 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58056) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65LS-0005ca-5t for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:36:54 -0500 Received: from [2607:f8b0:4864:20::62a] (port=39863 helo=mail-pl1-x62a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65LQ-00046x-84 for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:36:53 -0500 Received: by mail-pl1-x62a.google.com with SMTP id l8so4492532plt.6 for ; Fri, 07 Jan 2022 22:36:51 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id z4sm840954pfh.215.2022.01.07.22.36.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:36:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/BN9VpY7lULAa+aWFofLmKrrADNV3cDS0i892w5Blog=; b=U3Px7P5O+6qNXlPnv3BS0I5sjGIussUBxC9m42H0r567vvoZbqV7fzifWVliJSu32W eMKGSQUCz5WlhosUUCMvblLAf445O6P6ZhELe8OHRyLfCx94G92arIGnBaByRj+Eu0We 5Cw1KGw8A6sHuxOKIZzD132GaNKGTeTge1NDxxaY6/VgSGmvi3/xJ92n8gTgNzIyBLVA vs4Ctw0KH6Cp7+dAsPIdvA1VCCjX6r3+ip5JE+6A5Tv+GVMbnkQG2DE+CRKg4aCTD2u3 HgS1BqMcQh/4z8S4Bb4kKQokq2wmx8DBvGTlm6l+Wcfcw9Axilgc/L0gaePGK3VrqM6h MYhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/BN9VpY7lULAa+aWFofLmKrrADNV3cDS0i892w5Blog=; b=v4xhu+cwMmev9CGSBNOL6zu8gWE1vhXhMbXzPFX7JduM1Y4w44isM8aIaRkKHHyeeo yTe0I9KglbRaXQdnkAX2sdSyNe61TSMtRRhAKZw77i5M1NoV9SYUGll8OFdwrhZYOH++ DyKAZquapr5RMnaj8g9eRyfNhBKtlGcrr83e2OLUkpXh4wDASD7Sn1zMiZzp1frjTVrg Ec9G35lZJUgxbLyTHRfjUGYN3IZMY4e/hsPbFKLH3TophoREIGxxlVkBl/whvV6kLsRJ Yz1sMEZYJbxPAijZ6v6LNDbyA+K3ENZWcPGaBnOVGt7POCbJcyOMVxYgld13LxyPqQR/ nxRA== X-Gm-Message-State: AOAM530g653XANOXnghGveQDcpLvQTTIKWOkU+3z7xhf4XiklTg/NwNd fYvG+atASgGDSeglXNBUd9jHSfs4SXlL+g== X-Google-Smtp-Source: ABdhPJxjlqBdYYqC2tcBkAbniZEvqmoZK41QcnIsCZl3a0LdeYnT9a/0cg+eTlxxmDVrES+RdP9e4Q== X-Received: by 2002:a17:90b:1043:: with SMTP id gq3mr18929552pjb.24.1641623810844; Fri, 07 Jan 2022 22:36:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 02/12] tcg/mips: Support unaligned access for softmmu Date: Fri, 7 Jan 2022 22:36:34 -0800 Message-Id: <20220108063644.478043-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063644.478043-1-richard.henderson@linaro.org> References: <20220108063644.478043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62a (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641628474632100002 Content-Type: text/plain; charset="utf-8" We can use the routines just added for user-only to emit unaligned accesses in softmmu mode too. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 91 ++++++++++++++++++++++----------------- 1 file changed, 51 insertions(+), 40 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 5737d8a269..7682059d92 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1134,8 +1134,10 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg b= ase, TCGReg addrl, tcg_insn_unit *label_ptr[2], bool is_load) { MemOp opc =3D get_memop(oi); - unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); + unsigned s_bits =3D opc & MO_SIZE; + unsigned a_mask =3D (1 << a_bits) - 1; + unsigned s_mask =3D (1 << s_bits) - 1; int mem_index =3D get_mmuidx(oi); int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); @@ -1143,7 +1145,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg ba= se, TCGReg addrl, int add_off =3D offsetof(CPUTLBEntry, addend); int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - target_ulong mask; + target_ulong tlb_mask; =20 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); @@ -1157,27 +1159,13 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg = base, TCGReg addrl, /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3= . */ tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); =20 - /* We don't currently support unaligned accesses. - We could do so with mips32r6. */ - if (a_bits < s_bits) { - a_bits =3D s_bits; - } - - /* Mask the page bits, keeping the alignment bits to compare against. = */ - mask =3D (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1); - /* Load the (low-half) tlb comparator. */ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); - tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask); + tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); } else { tcg_out_ldst(s, (TARGET_LONG_BITS =3D=3D 64 ? OPC_LD : TCG_TARGET_REG_BITS =3D=3D 64 ? OPC_LWU : OPC_L= W), TCG_TMP0, TCG_TMP3, cmp_off); - tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask); - /* No second compare is required here; - load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); } =20 /* Zero extend a 32-bit guest address for a 64-bit host. */ @@ -1185,7 +1173,25 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg b= ase, TCGReg addrl, tcg_out_ext32u(s, base, addrl); addrl =3D base; } - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); + + /* + * Mask the page bits, keeping the alignment bits to compare against. + * For unaligned accesses, compare against the end of the access to + * verify that it does not cross a page boundary. + */ + tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; + tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask); + if (a_mask >=3D s_mask) { + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); + } else { + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrl, s_mask - a_mask); + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); + } + + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + /* Load the tlb addend for the fast path. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + } =20 label_ptr[0] =3D s->code_ptr; tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); @@ -1193,7 +1199,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg ba= se, TCGReg addrl, /* Load and test the high half tlb comparator. */ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { /* delay slot */ - tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); + tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); =20 /* Load the tlb addend for the fast path. */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); @@ -1515,8 +1521,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, } } =20 -static void __attribute__((unused)) -tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, +static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, TCGReg base, MemOp opc, bool is_64) { const MIPSInsn lw1 =3D MIPS_BE ? OPC_LWL : OPC_LWR; @@ -1645,8 +1650,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; #else - unsigned a_bits, s_bits; #endif + unsigned a_bits, s_bits; TCGReg base =3D TCG_REG_A0; =20 data_regl =3D *args++; @@ -1655,10 +1660,20 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) addr_regh =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); oi =3D *args++; opc =3D get_memop(oi); + a_bits =3D get_alignment_bits(opc); + s_bits =3D opc & MO_SIZE; =20 + /* + * R6 removes the left/right instructions but requires the + * system to support misaligned memory accesses. + */ #if defined(CONFIG_SOFTMMU) tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + if (use_mips32r6_instructions || a_bits >=3D s_bits) { + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + } else { + tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64); + } add_qemu_ldst_label(s, 1, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), data_regl, data_regh, addr_regl, addr_regh, @@ -1675,12 +1690,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is_64) } else { tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl= ); } - a_bits =3D get_alignment_bits(opc); - s_bits =3D opc & MO_SIZE; - /* - * R6 removes the left/right instructions but requires the - * system to support misaligned memory accesses. - */ if (use_mips32r6_instructions) { if (a_bits) { tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); @@ -1760,8 +1769,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, } } =20 -static void __attribute__((unused)) -tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, +static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, TCGReg base, MemOp opc) { const MIPSInsn sw1 =3D MIPS_BE ? OPC_SWL : OPC_SWR; @@ -1841,9 +1849,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; -#else - unsigned a_bits, s_bits; #endif + unsigned a_bits, s_bits; TCGReg base =3D TCG_REG_A0; =20 data_regl =3D *args++; @@ -1852,10 +1859,20 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is_64) addr_regh =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); oi =3D *args++; opc =3D get_memop(oi); + a_bits =3D get_alignment_bits(opc); + s_bits =3D opc & MO_SIZE; =20 + /* + * R6 removes the left/right instructions but requires the + * system to support misaligned memory accesses. + */ #if defined(CONFIG_SOFTMMU) tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + if (use_mips32r6_instructions || a_bits >=3D s_bits) { + tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + } else { + tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc); + } add_qemu_ldst_label(s, 0, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), data_regl, data_regh, addr_regl, addr_regh, @@ -1872,12 +1889,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is_64) } else { tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl= ); } - a_bits =3D get_alignment_bits(opc); - s_bits =3D opc & MO_SIZE; - /* - * R6 removes the left/right instructions but requires the - * system to support misaligned memory accesses. - */ if (use_mips32r6_instructions) { if (a_bits) { tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); --=20 2.25.1 From nobody Mon May 6 17:08:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641625870767451.1432179747211; Fri, 7 Jan 2022 23:11:10 -0800 (PST) Received: from localhost ([::1]:59280 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n65sb-0001KS-N9 for importer@patchew.org; Sat, 08 Jan 2022 02:11:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58068) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65LS-0005dX-P9 for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:36:54 -0500 Received: from [2607:f8b0:4864:20::432] (port=35529 helo=mail-pf1-x432.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65LR-000475-9u for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:36:54 -0500 Received: by mail-pf1-x432.google.com with SMTP id v11so7102997pfu.2 for ; Fri, 07 Jan 2022 22:36:52 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id z4sm840954pfh.215.2022.01.07.22.36.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:36:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fm/3m5hyAUdcKM+wbinoSBlpdmK7ofC9QaoVC3ISJrg=; b=u/mv3dUB3a7pbw82qL10Fs39mZinB29WdW1u+VaBalJzfKPEAUmPwntiwCAYA9bDXy D47yTH/SasLl+j9RLiqjbprHWxZQN0eqwFEfesiKORkvxg7o/C2yrwxIodV75J68qbO9 byQIXGffLkE6QNhhQJfAX7G0FMSNlmcY/wE1xI000yKr8WadXW67HpF3Ui95ZMcjvZAh 9qMkZko5/teB+V8A5WqQMf/CnATn+SU4Bg+Z9TnqElROAfr/pE3a7zsHtIVfoQYg+kAq l8qY/uEeeadq3v79mGr598z6b1olZDCS1TPiBoeEo2gwwnOUE14rO3W7rB1YQwItlRPd ch3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fm/3m5hyAUdcKM+wbinoSBlpdmK7ofC9QaoVC3ISJrg=; b=qOqiEMiZfehJIwEwq2LcvDbNebo7UNWfBEBSa2XTFnpupu5OHJwbA3jbjeFD6pU9IQ 3CSi9LslxHT1GT73E6+vD9g5qNwbIie/0QbTzhXAEAco59i/hFNMvbTDbsxSAA2WY8RK TcqVZnPBuuRK8dGJt+D0NhxGpWGj34ZqBvGHwN8fVg52eTTLqc0/zzIVD9/zU213O4T7 vrRU34dbsyGxySZzviBKihRXbH+PObKUzkl6FEkdn6fI8jdPT0OvzlwKOF8PeAewPcdU uYWSP+3rDw1Tzq8da6pLWzuCRUMhGctZf6dyA4hXpSKDVimZS6rs8Tc/JDyh0KUr91Qn QNDA== X-Gm-Message-State: AOAM532yrSi67tc2s5mXDq7jLB1scyeBLwySNyTvKjg6u0kZoRA78yu5 YVfKqX+TP8Agu7Xf6mzqB/KUxbp1BHsbhA== X-Google-Smtp-Source: ABdhPJxh4y38xNIPkfYVa82ScKutBfd5CgRcxlKymO5QqtGwCjHBouSoVWJAl2AnpQUxph8jc6AcnQ== X-Received: by 2002:a63:3606:: with SMTP id d6mr18472282pga.486.1641623812017; Fri, 07 Jan 2022 22:36:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 03/12] tcg/mips: Move TCG_AREG0 to S8 Date: Fri, 7 Jan 2022 22:36:35 -0800 Message-Id: <20220108063644.478043-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063644.478043-1-richard.henderson@linaro.org> References: <20220108063644.478043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::432 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641625872383100001 No functional change; just moving the saved reserved regs to the end. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 2 +- tcg/mips/tcg-target.c.inc | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 7669213175..28c42e23e1 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -76,7 +76,7 @@ typedef enum { TCG_REG_RA, =20 TCG_REG_CALL_STACK =3D TCG_REG_SP, - TCG_AREG0 =3D TCG_REG_S0, + TCG_AREG0 =3D TCG_REG_S8, } TCGReg; =20 /* used for function call generation */ diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 7682059d92..5702a6ad92 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2548,7 +2548,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) } =20 static const int tcg_target_callee_save_regs[] =3D { - TCG_REG_S0, /* used for the global env (TCG_AREG0) */ + TCG_REG_S0, TCG_REG_S1, TCG_REG_S2, TCG_REG_S3, @@ -2556,7 +2556,7 @@ static const int tcg_target_callee_save_regs[] =3D { TCG_REG_S5, TCG_REG_S6, TCG_REG_S7, - TCG_REG_S8, + TCG_REG_S8, /* used for the global env (TCG_AREG0) */ TCG_REG_RA, /* should be last for ABI compliance */ }; =20 --=20 2.25.1 From nobody Mon May 6 17:08:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641628841168759.4740285424441; Sat, 8 Jan 2022 00:00:41 -0800 (PST) Received: from localhost ([::1]:33072 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n66eV-0004RR-CT for importer@patchew.org; Sat, 08 Jan 2022 03:00:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58086) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65LT-0005eq-Nf for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:36:55 -0500 Received: from [2607:f8b0:4864:20::1030] (port=53022 helo=mail-pj1-x1030.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65LS-00047D-4I for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:36:55 -0500 Received: by mail-pj1-x1030.google.com with SMTP id pj2so5883021pjb.2 for ; Fri, 07 Jan 2022 22:36:53 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id z4sm840954pfh.215.2022.01.07.22.36.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:36:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zVgPy1si4yjxxz6mZk4TkdamYUEEeS8CxpBgD8+viKw=; b=QhjJqBqyHaj8QOIEYINho78lXXWmEOfCvSjca27mxgIsuJq/GjWBUdD1G7EJtWk2Xg FKTAvRWK+eXiGEpfLIIyNe99i31JaIsf+S2rcs972jV6g2jUQR8YAHCcQfM8KSjn2IyR S4qwzPJY4ptqE4ZAfJ8r/AQotW4ahBiqHhU2Qte56eYzMFdMMxg5VWO9GZvRpnJbVyc2 mhaMdmEwNwaceYBXqSfocgh16+B63uuKRKYKCgIjRWbldtU7GlWG4B4dGsm9pQrypjPC mXM73DlYr9qabguBzEm1lV8/CXkISNe17J8Rkwb3YzV1tI2ZIoyiszbBVlrByuMdsBYI lB5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zVgPy1si4yjxxz6mZk4TkdamYUEEeS8CxpBgD8+viKw=; b=qBGjTsdO2tOI0lvlD3zfAHW0qfZg8EjafMWRgvjaKRhuSs41FcdG/R/CUPRG5/V7a9 zHQwxbFPU4xzCrUEfqYZfvZLxIwX/y/oMfwkSnxMkBigPzM95vp5wpFQyzNLr8WlKNt9 8nHbdMW5+4yh+CIG647lERxnJ4GclCDMRAcaCeCrdZmyYxZ8tktDJ9BR7oqqHmWVGPTd v8C2EwYi1WxpRuB6gSYuNHGc0owSd6zr/2GJhlogOB8Kl4Rfwi8PbfspY/4dPEPcASz/ 9Aoa7d5y+syO8C9iw5EIDiPLxYpkLrX/G7sV4iX1wn5Dcs9ZXeZ+4J4MCdCdPESbmTxr VPbA== X-Gm-Message-State: AOAM53374cWmNh6RkML4cQMjt8NeHeZZMUoseS33VIxCDAi3+l38EWRz AVemwuqsvLpRRTllGWLicX+LqjLuLsqhiQ== X-Google-Smtp-Source: ABdhPJwDrorNwSArxmtJeob9FL+c88qag/UuKBLXL9NCKIQYfGfkvlMORXOEEHVD1/sODRBgH7JW3g== X-Received: by 2002:a17:90b:1c05:: with SMTP id oc5mr19091105pjb.31.1641623812876; Fri, 07 Jan 2022 22:36:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 04/12] tcg/mips: Move TCG_GUEST_BASE_REG to S7 Date: Fri, 7 Jan 2022 22:36:36 -0800 Message-Id: <20220108063644.478043-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063644.478043-1-richard.henderson@linaro.org> References: <20220108063644.478043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1030 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641628843986100001 No functional change; just moving the saved reserved regs to the end. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 5702a6ad92..1bfe6aea0e 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -86,7 +86,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET= _NB_REGS] =3D { #define TCG_TMP3 TCG_REG_T7 =20 #ifndef CONFIG_SOFTMMU -#define TCG_GUEST_BASE_REG TCG_REG_S1 +#define TCG_GUEST_BASE_REG TCG_REG_S7 #endif =20 /* check if we really need so many registers :P */ @@ -2555,7 +2555,7 @@ static const int tcg_target_callee_save_regs[] =3D { TCG_REG_S4, TCG_REG_S5, TCG_REG_S6, - TCG_REG_S7, + TCG_REG_S7, /* used for guest_base */ TCG_REG_S8, /* used for the global env (TCG_AREG0) */ TCG_REG_RA, /* should be last for ABI compliance */ }; --=20 2.25.1 From nobody Mon May 6 17:08:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641629024553234.66730053356264; Sat, 8 Jan 2022 00:03:44 -0800 (PST) Received: from localhost ([::1]:41480 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n66hT-0001wZ-ET for importer@patchew.org; Sat, 08 Jan 2022 03:03:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58096) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65Lc-0005hH-AO for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:37:05 -0500 Received: from [2607:f8b0:4864:20::102c] (port=41628 helo=mail-pj1-x102c.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65LS-00047P-Tv for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:36:56 -0500 Received: by mail-pj1-x102c.google.com with SMTP id b1-20020a17090a990100b001b14bd47532so8976310pjp.0 for ; Fri, 07 Jan 2022 22:36:54 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id z4sm840954pfh.215.2022.01.07.22.36.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:36:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y8sDBwJK1V/FhZ8YD28+6vGDo+RSEHHSakaI/hkSLk4=; b=Xwa2EcwPFc9kSL5RT4ODi22Ne/isCDG/9zDT2bXsJsj2zTAmn24FCik8D+JnrsJyNC +4OLykoDqzIHEpvuQGAO+fqGHEv+xYH84lGQ39B8D6QCc6UFJSoW72tXHLWy1HOZcl2u UPKHn8Tt/ymtPLdnY8L33BuxPJIBHJYL66JpSSk2WBJeglXMlEUFcr9I1enkSVJjaYoS Q/8JaNYfyhryWbaOnICf6iKnGI3CqrCZ4HMsB47nsHIq0RCRYh0sA6TKc+zOT9pEwuy9 j9qIMIuCm8fNhM8pBZRqfN1h7gEpsYzwRKzzK8qqhh8/TuVHGFdMdkDp3b3X9YA+z4FW +mZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y8sDBwJK1V/FhZ8YD28+6vGDo+RSEHHSakaI/hkSLk4=; b=J9UXyOo4MdzzbUmAETv34SwEXm6dnbL0If86ISkW4FF+VyM9EW0QmQXCu68hNRHcVz oNoVvmsoK64dYGzMiMolsqD0H7BiJiNletAg5vtCbFxmACABAUQ2QATXPNp8Sxh+EZt7 o1oOH1vIH6UemfIUfgCV5JCVu5ehUQh6g4AaGWGUyjwn/q8zFxa31gYN+tPjLMcfQPUS W5e1Rt3vWfO5BXrCyWKEhvSkRNKPWpJsFiMey5w4hlKDhYwKZrR63ooLWwsXhQCYWWB/ VEztV2WBoy/GqUk8vvoNAGIPCku0BUhkOCt0HajKSUlBcmXFCllqqVQ1FM98U4v2Tmvq hr+w== X-Gm-Message-State: AOAM531mlGoJT+jKmAzcyoHwOW2lo9nL3njcm4+pli0KnkFkJEeyfYOM phL/IUU7opmXa7VRvtwn4MPdndKZxxKJ2g== X-Google-Smtp-Source: ABdhPJyDrNafMSd0FSB13kIRGeBBd/7uvMcgOuYh0yTMxkf9fvbz4/iQP6TU/VJjJXfBb6aRAdmYFg== X-Received: by 2002:a17:90b:1651:: with SMTP id il17mr19575999pjb.190.1641623813755; Fri, 07 Jan 2022 22:36:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/12] tcg/mips: Unify TCG_GUEST_BASE_REG tests Date: Fri, 7 Jan 2022 22:36:37 -0800 Message-Id: <20220108063644.478043-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063644.478043-1-richard.henderson@linaro.org> References: <20220108063644.478043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102c (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641629026187100001 Content-Type: text/plain; charset="utf-8" In tcg_out_qemu_ld/st, we already check for guest_base matching int16_t. Mirror that when setting up TCG_GUEST_BASE_REG in the prologue. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/mips/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 1bfe6aea0e..46616784f8 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2677,7 +2677,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) } =20 #ifndef CONFIG_SOFTMMU - if (guest_base) { + if (guest_base !=3D (int16_t)guest_base) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } --=20 2.25.1 From nobody Mon May 6 17:08:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641626403234172.7885364053177; Fri, 7 Jan 2022 23:20:03 -0800 (PST) Received: from localhost ([::1]:41066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n661C-0002TU-1a for importer@patchew.org; Sat, 08 Jan 2022 02:20:02 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58144) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65Ld-0005hU-OV for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:37:07 -0500 Received: from [2607:f8b0:4864:20::535] (port=40747 helo=mail-pg1-x535.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65Lc-00047d-2X for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:37:05 -0500 Received: by mail-pg1-x535.google.com with SMTP id t32so7682052pgm.7 for ; Fri, 07 Jan 2022 22:36:55 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id z4sm840954pfh.215.2022.01.07.22.36.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:36:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=04Ui5ZVOanN6S96ULx7r59C8kMoqyjA71CaJbEASneY=; b=zi5xpJWneCBVR2piniN/oSOopsTdgRz3EJeXIJd/qCNUPIZFDpR24G6ui8F/wb8tGX oYfyazZePa4hnuCfE2BVjq/PLfj4bhuM+9qJXy/3eraK9Am3RWDK06T3KwBwU+a5iAMX bPs0yN2OsJQWJfPeJoBoJTDthVjwSVd0192iYiePclVrPxAR5kqoIagJ6/tmJJUwN+ak xAQXwKote8mYpH72pMedZ4lxhuZEocjD9tBlHs8u2/ScjL4JxJ92oPcu9A03ErXqk4Em 46YCvBp/f0fR9SSVpAJmdRb4NPsBwzJVys6V+vXKTN2iLYxkqoW1H9PXhM1YkGkeB1OE g/5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=04Ui5ZVOanN6S96ULx7r59C8kMoqyjA71CaJbEASneY=; b=RX/Vprrzc/tPX0rfPSup55UuFYHU4Di82z2A1BumZ5+RVdU27EyGzZH08+kw1J1bvi XpblA/ZU3aqVV2yo/qBLO0hvZ/4oFolFaM7eEa1FGMdCth95DzPrPvn7FcEjJRleNegG LhRt/ccmzws4pv+JloqTAh81a/J8U5X3+rwum7EOu4dXDSKPAfdo0hUG6YhnoNL59ySt ojzI7J1oiKYhO1AeykQzwxMkvW7WNg4bBxHcZIBk0RtekW/zNNz9QhHhMkwwbusnGMOP 8TWjdzs7bOs8vLv6s5Z9k78qkSsPrREFCrsYeSiCS0K/poJbQutl7fGDYaxYifIr4nat np8A== X-Gm-Message-State: AOAM5323Ha3u6QTrev7dQTi6RdDOQVLIBJrfZZYM3XenKo5aUVnifb4G 5UXzBnL0sq4iyZSLGqJGON5c5ATKBA1v+w== X-Google-Smtp-Source: ABdhPJwSZoTdfmXpGGewa9J/+SUvYf6K2wDvHJGpS/ZHd+le+Vf0vkWlyDZyv+GZY8uTMVxESD0AhQ== X-Received: by 2002:a63:4f22:: with SMTP id d34mr58712782pgb.12.1641623814780; Fri, 07 Jan 2022 22:36:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 06/12] tcg/mips: Create and use TCG_REG_TB Date: Fri, 7 Jan 2022 22:36:38 -0800 Message-Id: <20220108063644.478043-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063644.478043-1-richard.henderson@linaro.org> References: <20220108063644.478043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::535 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641626404013100001 Content-Type: text/plain; charset="utf-8" This vastly reduces the size of code generated for 64-bit addresses. The code for exit_tb, for instance, where we load a (tagged) pointer to the current TB, goes from 0x400aa9725c: li v0,64 0x400aa97260: dsll v0,v0,0x10 0x400aa97264: ori v0,v0,0xaa9 0x400aa97268: dsll v0,v0,0x10 0x400aa9726c: j 0x400aa9703c 0x400aa97270: ori v0,v0,0x7083 to 0x400aa97240: j 0x400aa97040 0x400aa97244: daddiu v0,s6,-189 Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 75 ++++++++++++++++++++++++++++++++------- 1 file changed, 62 insertions(+), 13 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 46616784f8..76fb1dada0 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -88,6 +88,11 @@ static const char * const tcg_target_reg_names[TCG_TARGE= T_NB_REGS] =3D { #ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG TCG_REG_S7 #endif +#if TCG_TARGET_REG_BITS =3D=3D 64 +#define TCG_REG_TB TCG_REG_S6 +#else +#define TCG_REG_TB (qemu_build_not_reached(), TCG_REG_ZERO) +#endif =20 /* check if we really need so many registers :P */ static const int tcg_target_reg_alloc_order[] =3D { @@ -1971,34 +1976,72 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, switch (opc) { case INDEX_op_exit_tb: { - TCGReg b0 =3D TCG_REG_ZERO; + TCGReg base =3D TCG_REG_ZERO; + int16_t lo =3D 0; =20 - a0 =3D (intptr_t)a0; - if (a0 & ~0xffff) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); - b0 =3D TCG_REG_V0; + if (a0) { + intptr_t ofs; + if (TCG_TARGET_REG_BITS =3D=3D 64) { + ofs =3D tcg_tbrel_diff(s, (void *)a0); + lo =3D ofs; + if (ofs =3D=3D lo) { + base =3D TCG_REG_TB; + } else { + base =3D TCG_REG_V0; + tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); + tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG= _TB); + } + } else { + ofs =3D a0; + lo =3D ofs; + base =3D TCG_REG_V0; + tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); + } } if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); } - tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); } break; case INDEX_op_goto_tb: /* indirect jump method */ tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, - (uintptr_t)(s->tb_jmp_target_addr + a0)); - tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); - tcg_out_nop(s); - set_jmp_reset_offset(s, a0); + { + TCGReg base, dest; + intptr_t ofs; + + if (TCG_TARGET_REG_BITS =3D=3D 64) { + dest =3D base =3D TCG_REG_TB; + ofs =3D tcg_tbrel_diff(s, s->tb_jmp_target_addr + a0); + } else { + dest =3D TCG_TMP0; + base =3D TCG_REG_ZERO; + ofs =3D (intptr_t)(s->tb_jmp_target_addr + a0); + } + tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); + tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); + /* delay slot */ + tcg_out_nop(s); + + set_jmp_reset_offset(s, args[0]); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + /* For the unlinked case, need to reset TCG_REG_TB. */ + tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, + -tcg_current_code_size(s)); + } + } break; case INDEX_op_goto_ptr: /* jmp to the given host address (could be epilogue) */ tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); - tcg_out_nop(s); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); + } else { + tcg_out_nop(s); + } break; case INDEX_op_br: tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, @@ -2554,7 +2597,7 @@ static const int tcg_target_callee_save_regs[] =3D { TCG_REG_S3, TCG_REG_S4, TCG_REG_S5, - TCG_REG_S6, + TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */ TCG_REG_S7, /* used for guest_base */ TCG_REG_S8, /* used for the global env (TCG_AREG0) */ TCG_REG_RA, /* should be last for ABI compliance */ @@ -2682,6 +2725,9 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } #endif + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs= [1]); + } =20 /* Call generated code */ tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); @@ -2863,6 +2909,9 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address = */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer = */ + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ + } } =20 typedef struct { --=20 2.25.1 From nobody Mon May 6 17:08:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641628214547311.04643801060627; Fri, 7 Jan 2022 23:50:14 -0800 (PST) Received: from localhost ([::1]:46388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n66UP-0001bK-Hi for importer@patchew.org; Sat, 08 Jan 2022 02:50:13 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58186) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65Lf-0005i8-4B for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:37:09 -0500 Received: from [2607:f8b0:4864:20::533] (port=43645 helo=mail-pg1-x533.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65Lc-00047o-4G for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:37:06 -0500 Received: by mail-pg1-x533.google.com with SMTP id 8so7660251pgc.10 for ; Fri, 07 Jan 2022 22:36:57 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id z4sm840954pfh.215.2022.01.07.22.36.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:36:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MZajHEilU6k0lLPYYDZNQ8jEdB70Bcd5oTv/nQtoSnU=; b=h9tD3gqY/ZsxBj1V75fRpJ4CVnPcEk+8dJXEKUnzgHHS+QG+0JoLJxup6VZYZlZeUP 8HTb/UlQIE4wT3vMQOZC9Z+pCnqcgUzJd4mwf/GeGWyhjLVXJ1enrFy3evWrSrUAEPdl T8G6lWw0mR2wPhjPWxv4BmZ4e/NVEfzjfY2C+nokqr0WII0MFiHfkZ8iKexbK+4VlMbg CSYrxlSEVczRLUFaWhLSGTBvneLXjEg3StqYM0t2kcSpmpU8NNqnscYEXTg9rtnBFc01 OGxSch+IKR1y0Act55L7uQJnnuoanoZ/dmrCqmfMBjsqwNLsPq//pp9tqNxP9vZnmfFO GnVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MZajHEilU6k0lLPYYDZNQ8jEdB70Bcd5oTv/nQtoSnU=; b=Cp/qAttlZtggQvG8UIiGrxKa8fZCI8hj1maw6sJPXgH6+7t2l1aWU9UUyVjxfGp6D9 EcBNTObnvY0dgdaglCKCqoIQ6mtXyoOohxxIdbPe/BE/81Dl+bqfiWMnvZlToNswvCsn J7q7+8mKKDdm6yVH2prmgRAIF6/ffhgIXPiHPYa4e99qlpgnuwPmKJ4CEk2h/ltfgpDb T+2kjs7/g7jiIDSS0BzVbNpK/TFY9iCrHEH2JZK2G5d5KLmOOLPD3fnT2uPpW9ewklpx +fwNyx6Zxv0Ot1+S7xkhXivrq6gu9Qfo7aek13cnzJRgUpTCMHDyZ2Lm4yGG7Wyx0L4+ rHrw== X-Gm-Message-State: AOAM530C6CQyGd2ueUODl62YsQPlyQP3SwK2HVOAu3j1Wyr1cAlJqvdp 9c8Yj9e5LCmPOsmeO72camM5c05sn0IIQg== X-Google-Smtp-Source: ABdhPJw9yqOtgP/QBGvsV7fadslwzpmxoFEgD7tdkdDFYIc9m3I3DKxvBEDRXRt3YTOACN3GRzKjEQ== X-Received: by 2002:a63:b247:: with SMTP id t7mr13164194pgo.164.1641623816390; Fri, 07 Jan 2022 22:36:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/12] tcg/mips: Split out tcg_out_movi_one Date: Fri, 7 Jan 2022 22:36:39 -0800 Message-Id: <20220108063644.478043-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063644.478043-1-richard.henderson@linaro.org> References: <20220108063644.478043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::533 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641628216179100001 Content-Type: text/plain; charset="utf-8" Emit all constants that can be loaded in exactly one insn. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 76fb1dada0..8741fdd49c 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -524,20 +524,34 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, = TCGReg ret, TCGReg arg) return true; } =20 +static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long ar= g) +{ + if (arg =3D=3D (int16_t)arg) { + tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); + return true; + } + if (arg =3D=3D (uint16_t)arg) { + tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); + return true; + } + if (arg =3D=3D (int32_t)arg && (arg & 0xffff) =3D=3D 0) { + tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); + return true; + } + return false; +} + static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I32) { arg =3D (int32_t)arg; } - if (arg =3D=3D (int16_t)arg) { - tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); - return; - } - if (arg =3D=3D (uint16_t)arg) { - tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); + + if (tcg_out_movi_one(s, ret, arg)) { return; } + if (TCG_TARGET_REG_BITS =3D=3D 32 || arg =3D=3D (int32_t)arg) { tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); } else { --=20 2.25.1 From nobody Mon May 6 17:08:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641629477460115.10298812133851; Sat, 8 Jan 2022 00:11:17 -0800 (PST) Received: from localhost ([::1]:49976 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n66om-0007xi-4m for importer@patchew.org; Sat, 08 Jan 2022 03:11:16 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58190) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65Lf-0005iA-6H for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:37:09 -0500 Received: from [2607:f8b0:4864:20::435] (port=44990 helo=mail-pf1-x435.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65Lc-00048y-Pc for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:37:06 -0500 Received: by mail-pf1-x435.google.com with SMTP id t187so7048725pfb.11 for ; Fri, 07 Jan 2022 22:36:59 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id z4sm840954pfh.215.2022.01.07.22.36.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:36:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gNW3zpumLFHPqplHLKc2ywbGSNXOgU1ULWv67Fdx+a8=; b=p4eo/abBIlFS/qYjuGZmUf+oWl+obovIUlhDoS+TpyKGYvFl+mFMDV1B0+cPMQKtHr m38uHQ0PJ3PFviUpF+8koW5cswglxq/iJdXyjHefnK+jfT5wx+XsWzo5BZHTLTbXL5oJ Ad/m3zQRXhZwkEvGMI3/OmpZe4RJw9iw6tgmn50k0AunoUHLD3q/ZYtrbWLw1Wa49MDX YRD4OgUvr2ixticbw/3qWCxvTFtwg+Wk3CFQr8dyz4Xb0Q+qzMtbgMTdgnYeJDCKKuvZ bgOi3T/rANnXkcPmooCNLVRGBfOVzWPo7oPgPuzhut78Zq7AjrX5gHdhGBJxix7FtiB4 X+1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gNW3zpumLFHPqplHLKc2ywbGSNXOgU1ULWv67Fdx+a8=; b=FcML4AyQNqFwwf9GMe1wHhj8v8/35x4aGFgQyQkodQ3FTZSNvwoz9C56lRwIa6xh+j ABVpulsP71XFAm3+U2Pq+JgPsZdKJNxFgRwR/wSDstbJMlyOfVGKkbpBLE+gLBlo+/Qh XUCq+ds+a9P/CTS0DkgR5MDbhRRm3He0WjllvJgOUEF4c5Lc2SNtdqWyDo6TfYbzBhiV ASmUcWNzPbgNzdaRatfVhKV3DvvdzVK/YNcdyDdsvCbABhdpzi9lR40n+qjmJ1B7FM/Q D+dFh0LI0LDkMCjznoKXjDlaASCS4lOZ1KUNLzlwsroY6W/mqrrDQEr1zXUBG+JYZ6ov Z+1g== X-Gm-Message-State: AOAM5308Ud7kdwYR4O23rT0HiK0Vib0QkNmzcL/n5vkJ5j1JARZTkskr IsyIP6PhVjaROsQajbAUIh7EzSy53GmOoQ== X-Google-Smtp-Source: ABdhPJxUL+OLfbv5RkWS8wytmki4ieXMSOx1hZyF0Kq/5cbmMnbDrhbCR4ZgxlRXXXCqGQYRiT/q1Q== X-Received: by 2002:a65:6aa7:: with SMTP id x7mr21572871pgu.273.1641623818644; Fri, 07 Jan 2022 22:36:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 08/12] tcg/mips: Split out tcg_out_movi_two Date: Fri, 7 Jan 2022 22:36:40 -0800 Message-Id: <20220108063644.478043-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063644.478043-1-richard.henderson@linaro.org> References: <20220108063644.478043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::435 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641629479460100001 Content-Type: text/plain; charset="utf-8" Emit all 32-bit signed constants, which can be loaded in two insns. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 8741fdd49c..142583b613 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -541,6 +541,22 @@ static bool tcg_out_movi_one(TCGContext *s, TCGReg ret= , tcg_target_long arg) return false; } =20 +static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long ar= g) +{ + /* + * All signed 32-bit constants are loadable with two immediates, + * and everything else requires more work. + */ + if (arg =3D=3D (int32_t)arg) { + if (!tcg_out_movi_one(s, ret, arg)) { + tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); + tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); + } + return true; + } + return false; +} + static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { @@ -548,21 +564,18 @@ static void tcg_out_movi(TCGContext *s, TCGType type, arg =3D (int32_t)arg; } =20 - if (tcg_out_movi_one(s, ret, arg)) { + /* Load all 32-bit constants. */ + if (tcg_out_movi_two(s, ret, arg)) { return; } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 || arg =3D=3D (int32_t)arg) { - tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); + tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); + if (arg & 0xffff0000ull) { + tcg_out_dsll(s, ret, ret, 16); + tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); + tcg_out_dsll(s, ret, ret, 16); } else { - tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); - if (arg & 0xffff0000ull) { - tcg_out_dsll(s, ret, ret, 16); - tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); - tcg_out_dsll(s, ret, ret, 16); - } else { - tcg_out_dsll(s, ret, ret, 32); - } + tcg_out_dsll(s, ret, ret, 32); } if (arg & 0xffff) { tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); --=20 2.25.1 From nobody Mon May 6 17:08:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641628521669594.725922529061; Fri, 7 Jan 2022 23:55:21 -0800 (PST) Received: from localhost ([::1]:54814 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n66ZM-00084n-H4 for importer@patchew.org; Sat, 08 Jan 2022 02:55:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58192) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65Lf-0005iB-9f for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:37:09 -0500 Received: from [2607:f8b0:4864:20::529] (port=33755 helo=mail-pg1-x529.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65Lc-000493-Pi for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:37:07 -0500 Received: by mail-pg1-x529.google.com with SMTP id i30so7711793pgl.0 for ; Fri, 07 Jan 2022 22:37:01 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id z4sm840954pfh.215.2022.01.07.22.36.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:36:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JsQkGFvS1Fhc2RIvE2HvJnqLrbMFFGBcon9lp8/VH2c=; b=tsbKgldvf6L+GXkKXTi8v2C2D159nx4nVJKDlZhbfqvgQjflbcKJGrcGGjupWPXvTy +cHiiTW6gKSGl8XkMt2Kjbc8hcqpYvxSq+b+lRZR2OZRrU0BT97v0VZl/mAgtPOg2VeP D0fzkq1vfakGDFf//UB7QJJXC8TEg9J9a6mkL2hC+cV0Sfq0A+aOIrGl5r7RY6SvHyDx YfBT6+4oEzeFJDlAM27LZ8PezN/fbbijzHe3auKsyU0NqfzEawVNBonev/LzxoE7SPN+ mqaD6lYkyttaDuydegcKaDvDAm2DOHJIkEFlm+McORLGSyahsOiEhypwL5PF/IogxUMm hs2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JsQkGFvS1Fhc2RIvE2HvJnqLrbMFFGBcon9lp8/VH2c=; b=uBPlylTZXWzW+rxCdyugh9EbDltHyY/Fjcn+PUNVvPRNy+ksZCrALZkNfQYORNdXv1 h2aZpgMBXArlvDMmgZPfcZckB0MGd2K6hEE0O9wrE4JpFyPhW7cUI4bIUOcExXPuSYTW ZVBTrMPiHqvf2DqDdCqx30X+2J1U8bD3q8nW/pfARcrOG0Nt8gtTxXnrF/jv7FT8sD/P 9gOVUC9QihzrVVBlG18CBbVEgVJJqMEylqOpoK5WDaDxkkAlqqokr1D1tB47fXClu3a5 ICvTdTIyv/jAFD1LGw/u8kLKp+KNJ7IaiyKBewWbd4vDmHYRKbr0fEh8qbG3tJc043+E 62Xg== X-Gm-Message-State: AOAM533ugn/7xaGhABDDHrhLhcpF3/FweXXlZ+B6ImjE65htxJgLLduj XRF03N2heb7Fcer9kAAWcWh4xYQ7eva+yw== X-Google-Smtp-Source: ABdhPJzsqLHw6UcLlkycKzDD9jPQ4PWQ6kSjTuug8BYdz7eygXJ582MhV6EabJ9AR4M0TAlGc7iPpA== X-Received: by 2002:a63:7250:: with SMTP id c16mr1438071pgn.359.1641623820213; Fri, 07 Jan 2022 22:37:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 09/12] tcg/mips: Use the constant pool for 64-bit constants Date: Fri, 7 Jan 2022 22:36:41 -0800 Message-Id: <20220108063644.478043-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063644.478043-1-richard.henderson@linaro.org> References: <20220108063644.478043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::529 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641628522654100001 Content-Type: text/plain; charset="utf-8" During normal processing, the constant pool is accessible via TCG_REG_TB. During the prologue, it is accessible via TCG_REG_T9. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 1 + tcg/mips/tcg-target.c.inc | 65 +++++++++++++++++++++++++++++---------- 2 files changed, 49 insertions(+), 17 deletions(-) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 28c42e23e1..839364b493 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -208,5 +208,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t) QEMU_ERROR("code path is reachable"); =20 #define TCG_TARGET_NEED_LDST_LABELS +#define TCG_TARGET_NEED_POOL_LABELS =20 #endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 142583b613..41cb155eb0 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -25,6 +25,7 @@ */ =20 #include "../tcg-ldst.c.inc" +#include "../tcg-pool.c.inc" =20 #ifdef HOST_WORDS_BIGENDIAN # define MIPS_BE 1 @@ -166,9 +167,18 @@ static bool reloc_pc16(tcg_insn_unit *src_rw, const tc= g_insn_unit *target) static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - tcg_debug_assert(type =3D=3D R_MIPS_PC16); - tcg_debug_assert(addend =3D=3D 0); - return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); + value +=3D addend; + switch (type) { + case R_MIPS_PC16: + return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); + case R_MIPS_16: + if (value !=3D (int16_t)value) { + return false; + } + *code_ptr =3D deposit32(*code_ptr, 0, 16, value); + return true; + } + g_assert_not_reached(); } =20 #define TCG_CT_CONST_ZERO 0x100 @@ -500,6 +510,11 @@ static void tcg_out_nop(TCGContext *s) tcg_out32(s, 0); } =20 +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + memset(p, 0, count * sizeof(tcg_insn_unit)); +} + static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); @@ -557,8 +572,15 @@ static bool tcg_out_movi_two(TCGContext *s, TCGReg ret= , tcg_target_long arg) return false; } =20 -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) +static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, + tcg_target_long arg, TCGReg tbreg) +{ + new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL)= ); + tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0); +} + +static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long arg, TCGReg tbreg) { if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I32) { arg =3D (int32_t)arg; @@ -568,18 +590,17 @@ static void tcg_out_movi(TCGContext *s, TCGType type, if (tcg_out_movi_two(s, ret, arg)) { return; } + assert(TCG_TARGET_REG_BITS =3D=3D 64); =20 - tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); - if (arg & 0xffff0000ull) { - tcg_out_dsll(s, ret, ret, 16); - tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); - tcg_out_dsll(s, ret, ret, 16); - } else { - tcg_out_dsll(s, ret, ret, 32); - } - if (arg & 0xffff) { - tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); - } + /* Otherwise, put 64-bit constants into the constant pool. */ + tcg_out_movi_pool(s, ret, arg, tbreg); +} + +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) +{ + TCGReg tbreg =3D TCG_TARGET_REG_BITS =3D=3D 64 ? TCG_REG_TB : 0; + tcg_out_movi_int(s, type, ret, arg, tbreg); } =20 static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int fla= gs) @@ -2748,10 +2769,20 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 #ifndef CONFIG_SOFTMMU if (guest_base !=3D (int16_t)guest_base) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + /* + * The function call abi for n32 and n64 will have loaded $25 (t9) + * with the address of the prologue, so we can use that instead + * of TCG_REG_TB. + */ +#if TCG_TARGET_REG_BITS =3D=3D 64 && !defined(__mips_abicalls) +# error "Unknown mips abi" +#endif + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, + TCG_TARGET_REG_BITS =3D=3D 64 ? TCG_REG_T9 : 0); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } #endif + if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs= [1]); } --=20 2.25.1 From nobody Mon May 6 17:08:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16416256080981023.9784669662268; Fri, 7 Jan 2022 23:06:48 -0800 (PST) Received: from localhost ([::1]:52278 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n65oM-0004tn-Nz for importer@patchew.org; Sat, 08 Jan 2022 02:06:46 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58162) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65Le-0005i6-9y for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:37:09 -0500 Received: from [2607:f8b0:4864:20::62f] (port=34490 helo=mail-pl1-x62f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65Lc-000497-3h for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:37:06 -0500 Received: by mail-pl1-x62f.google.com with SMTP id x15so6721549plg.1 for ; Fri, 07 Jan 2022 22:37:02 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id z4sm840954pfh.215.2022.01.07.22.37.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:37:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/LG8DOHxYfb1kWl3G1waKqt5lQyEB1CM556IjrEgvw4=; b=TBf0jrt081oDxr5ry+y0WZY1I7Dl3FcHsjEY/Hftnyn+RQpiXu+c1IAWI3IP8YMBFW uLWgVNUmtaXcPNn+5aqgNYMiM6l9MA/kISRoBvfvQ2e9wm7cJG18+hjiJTShtCMlIvQO 7hcthTm0ta8sITjVy5VTIKRjOc9eJfa/HJSy6uxPEHVuvTpHTiqk9oln/Yek2Y48AzCH raFcplFDKSjXscfKy8D9b/TdMyDH7/+932fj0nRBFB74IcwItG6D5iJXOa55UY3S/i6x 54wqZi34gFKVnyJIjneLI12uwV/yjfob6TvPnyN/pKOxhNEcxIEpaP8PVY+YQsnV+BPM 35PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/LG8DOHxYfb1kWl3G1waKqt5lQyEB1CM556IjrEgvw4=; b=KFM25Fg1f1M1uxRUvDELsoSc0C8cqK1VPTQP2lYh7YUkIcZn6VzJp2EGAOyzmQxYsn cPuOJikQAe1ESb0hJMk0tm7HPw31JZaeaBhiWfktKzoX5vlK9n0qTLs9MbxuEUay/xJw tnuPIrOiLUxye6ZksdetgnweeYtY6k/ApRC5r35u15atDcrPCP9Rp3BWFarugq7JPS6q JaO7iQnbz/fp/GRBwJv32KFpQNCik8nZYWab6RX3TnV75/2afjC4/aSRi01Q74aJAnEO dAMokCg/4LTT7W33kT7Tzyyz3FLUaik++3ET59hqwL086DUwQ9gpFVpY1gxXy9CGJHAA 545g== X-Gm-Message-State: AOAM532p8T6qgrvwRbiV/Ad91dupC46UkpMeCTrFMohlsINmefZXqRuw /PTfXdVD3EQ9OndoE7x2hWbJ80x38k3Mug== X-Google-Smtp-Source: ABdhPJzQVPpmhx6QoxssDyGdj8dloLw7U2oeO1jjvSz+5/AecTu+y5nY13ZC6eZaD+qF2ipL34C5mw== X-Received: by 2002:a17:902:e5c2:b0:149:3cd:ebf5 with SMTP id u2-20020a170902e5c200b0014903cdebf5mr66215001plf.1.1641623822095; Fri, 07 Jan 2022 22:37:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 10/12] tcg/mips: Aggressively use the constant pool for n64 calls Date: Fri, 7 Jan 2022 22:36:42 -0800 Message-Id: <20220108063644.478043-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063644.478043-1-richard.henderson@linaro.org> References: <20220108063644.478043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641625610712100001 Content-Type: text/plain; charset="utf-8" Repeated calls to a single helper are common -- especially the ones for softmmu memory access. Prefer the constant pool to longer sequences to increase sharing. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 41cb155eb0..e967f62869 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1057,9 +1057,19 @@ static void tcg_out_movcond(TCGContext *s, TCGCond c= ond, TCGReg ret, =20 static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool= tail) { - /* Note that the ABI requires the called function's address to be - loaded into T9, even if a direct branch is in range. */ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); + /* + * Note that __mips_abicalls requires the called function's address + * to be loaded into $25 (t9), even if a direct branch is in range. + * + * For n64, always drop the pointer into the constant pool. + * We can re-use helper addresses often and do not want any + * of the longer sequences tcg_out_movi may try. + */ + if (sizeof(uintptr_t) =3D=3D 8) { + tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); + } =20 /* But do try a direct branch, allowing the cpu better insn prefetch. = */ if (tail) { --=20 2.25.1 From nobody Mon May 6 17:08:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641625956712730.6789622865028; Fri, 7 Jan 2022 23:12:36 -0800 (PST) Received: from localhost ([::1]:60726 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n65tz-0002IZ-EO for importer@patchew.org; Sat, 08 Jan 2022 02:12:35 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58188) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65Lf-0005i9-5W for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:37:09 -0500 Received: from [2607:f8b0:4864:20::42f] (port=39589 helo=mail-pf1-x42f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65Lc-00049B-QA for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:37:06 -0500 Received: by mail-pf1-x42f.google.com with SMTP id s15so7086484pfk.6 for ; Fri, 07 Jan 2022 22:37:04 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id z4sm840954pfh.215.2022.01.07.22.37.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:37:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=APMyiBbMfTnvrByjN9FXgMAg/ptb1gS5tnwqgT0NITM=; b=Nc7LM3r+QxnF1xD/qeyvVsh0T1IyzObZ6wO8mvCw671nRdSygDXudC2YyLHrrAkZpV 0ihMzhWS3mrg+8C6eCVtzxkhyJe3r1dqKhFnP3o5q11Z3OcU2XousGPAcr9IMcSvWdsU NeFK/MD5YyyfUFK7UjKkUVNEG7mN461GRnNxM0aIrAQyL3DiqthvI40vN4rLLm6D2te2 jUOo8Vp0YSg0dqZtvkirOGoN0TGoqhNvfZYQWQCUs6EwOKeBMOzMuUH46aUck0+AXNnB 70/gut37W7b3tSxHGR/aeBlFsM7QQx8GCnbh69JDlRNIhUgSf/YFFGfvgQzqiceN2LuK 7dYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=APMyiBbMfTnvrByjN9FXgMAg/ptb1gS5tnwqgT0NITM=; b=J0rEtL5D6h9Im0LI2IynjijQNcEFOr2yWJNJQeBGYDrUcTiL9k/cJ5bcz8uTbzmmV3 41xEnIca/RbVfixputG+NLOOrx8jK2Uoxs5bc0cpNF+IwPfTHNLIA0RQxKzUAh1V5phW p4NWOebYSKjAMqQrzARhyHkUeKCacq5D0VDb+zPMTQIUHgxL1w/yNubq3FWS2QP7ij8U IP61pRoAB9epe1TVcmwHP5Hw+gg1JbaRAsyXYnZ5GQ8gxEVn88rrsRezrKUAPmOvih0w BFKwK2hKSZ0DKSDdaxFClRm1zEVfxeursaSqgjRfMwBr1iDeqOUUTb5QsyaF5tK6bJnT cnbQ== X-Gm-Message-State: AOAM5304gf8ag4sZisGpaRyzrbB1EsWjadntwOmGVHQJSs0iFJVb1quL Vpb821WwwwCwfiMpPQ7em+I/O3HBOx7hPw== X-Google-Smtp-Source: ABdhPJyYVwc41DamJTDCLhOl4Gj9ZcWeCFz9GuTr5COO05YiayQzLgNtglDpZ6MSMTIBVYh+siWyZw== X-Received: by 2002:a63:1422:: with SMTP id u34mr59839850pgl.135.1641623823254; Fri, 07 Jan 2022 22:37:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 11/12] tcg/mips: Try tb-relative addresses in tcg_out_movi Date: Fri, 7 Jan 2022 22:36:43 -0800 Message-Id: <20220108063644.478043-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063644.478043-1-richard.henderson@linaro.org> References: <20220108063644.478043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641625958944100001 Content-Type: text/plain; charset="utf-8" These addresses are often loaded by the qemu_ld/st slow path, for loading the retaddr value. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index e967f62869..a128c70154 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -582,6 +582,8 @@ static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg, TCGReg tbreg) { + tcg_target_long tmp; + if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I32) { arg =3D (int32_t)arg; } @@ -592,6 +594,17 @@ static void tcg_out_movi_int(TCGContext *s, TCGType ty= pe, TCGReg ret, } assert(TCG_TARGET_REG_BITS =3D=3D 64); =20 + /* Load addresses within 2GB of TB with 1 or 3 insns. */ + tmp =3D tcg_tbrel_diff(s, (void *)arg); + if (tmp =3D=3D (int16_t)tmp) { + tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp); + return; + } + if (tcg_out_movi_two(s, ret, tmp)) { + tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg); + return; + } + /* Otherwise, put 64-bit constants into the constant pool. */ tcg_out_movi_pool(s, ret, arg, tbreg); } --=20 2.25.1 From nobody Mon May 6 17:08:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16416263314583.973661605202551; Fri, 7 Jan 2022 23:18:51 -0800 (PST) Received: from localhost ([::1]:39594 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n6602-0001Ef-CD for importer@patchew.org; Sat, 08 Jan 2022 02:18:50 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58202) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65Lg-0005iD-Dd for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:37:09 -0500 Received: from [2607:f8b0:4864:20::536] (port=39711 helo=mail-pg1-x536.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65Le-00049X-TW for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:37:08 -0500 Received: by mail-pg1-x536.google.com with SMTP id a22so3298904pgd.6 for ; Fri, 07 Jan 2022 22:37:06 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id z4sm840954pfh.215.2022.01.07.22.37.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:37:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1PgEAjuvJVWdLvX5wSFmndrZo74W/oucIMftf9RLc6U=; b=wvb9IRHnNqF6+gsgUPQ6JE5DBeWftiA8x2efzd02CCXnANqqDPKx4H32ohL5FW/aM2 vnVyd8zkYONbi43SUig3CJTjvyAlZmIRYD1uE8Etpn85d6LVZYJbpM2WU+jPMDopS75X T6tq5j/8bdwsctQIYieaWD6AxgGocmhGBlGusojypNENv+bPlghg80vEp4PG5Cso82Uz aTnt6o525vEmtHbWxX+fy6Hjy7V8TqhY9qg98tKIu/q5C2xLKlQp8LAXqWk1l+y4tpdg baBoUvbldSeuhJyrPhq/9po+qvl2AiJGJIAz40E+jjdVXmYPkySYOdNQ4rOWi/Emaufl EQcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1PgEAjuvJVWdLvX5wSFmndrZo74W/oucIMftf9RLc6U=; b=DMlYOkvfNZSOVlzdlb8yVp3bsdsHac6Lqcd2VUCFlwt5BB/JZ0ge1Bx6Vt4RsAnJmj t0sj5UeRMXS8aHKL6diBf836GieTDsp4MDoDrd5n0rlbelbbJLtnIupIC5CgZgYLX0h3 BkriBPAIqa0KsQDYooeRG3Z7WY+r2Xq8HbRJVbblCqdtUaGCp+w9sZiPYdyGO+yGmk7H JYvKf+nvd+fFywdLfdtAnTHdlk37+pGC56kC1c/w7ob/zWt32J8aCKhAQb7lFMsotwie QvcKizsks+c2eEujxKjJ5zj6G+2H14MgYKwnVBQVqAI1Z1FO38IhopkZJlU4gCGn2rUe FjlA== X-Gm-Message-State: AOAM533zal0Pd3T8v/Vigs/KW9+w52wpdHbTddF84Z0y/kOTZp6Tbbrr 2k5ls5W6rfbsaxRi78xhKeeJOQRfgR1QiQ== X-Google-Smtp-Source: ABdhPJw8DF1vCa3gKbdEKGrlb3GDYcdNWG1LsYlXxrOTZ0UqWIVbDZL96Ed63lrnmai6uUSzQzfslA== X-Received: by 2002:a62:180d:0:b0:4bb:dafb:ff50 with SMTP id 13-20020a62180d000000b004bbdafbff50mr57641672pfy.45.1641623825613; Fri, 07 Jan 2022 22:37:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/12] tcg/mips: Try three insns with shift and add in tcg_out_movi Date: Fri, 7 Jan 2022 22:36:44 -0800 Message-Id: <20220108063644.478043-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063644.478043-1-richard.henderson@linaro.org> References: <20220108063644.478043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::536 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641626333524100001 Content-Type: text/plain; charset="utf-8" These sequences are inexpensive to test. Maxing out at three insns results in the same space as a load plus the constant pool entry. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 44 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index a128c70154..185241da17 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -583,6 +583,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, tcg_target_long arg, TCGReg tbreg) { tcg_target_long tmp; + int sh, lo; =20 if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I32) { arg =3D (int32_t)arg; @@ -605,6 +606,49 @@ static void tcg_out_movi_int(TCGContext *s, TCGType ty= pe, TCGReg ret, return; } =20 + /* + * Load bitmasks with a right-shift. This is good for things + * like 0x0fff_ffff_ffff_fff0: ADDUI r,0xff00 + DSRL r,r,4. + * or similarly using LUI. For this to work, bit 31 must be set. + */ + if (arg > 0 && (int32_t)arg < 0) { + sh =3D clz64(arg); + if (tcg_out_movi_one(s, ret, arg << sh)) { + tcg_out_dsrl(s, ret, ret, sh); + return; + } + } + + /* + * Load slightly larger constants using left-shift. + * Limit this sequence to 3 insns to avoid too much expansion. + */ + sh =3D ctz64(arg); + if (sh && tcg_out_movi_two(s, ret, arg >> sh)) { + tcg_out_dsll(s, ret, ret, sh); + return; + } + + /* + * Load slightly larger constants using left-shift and add/or. + * Prefer addi with a negative immediate when that would produce + * a larger shift. For this to work, bits 15 and 16 must be set. + */ + lo =3D arg & 0xffff; + if (lo) { + if ((arg & 0x18000) =3D=3D 0x18000) { + lo =3D (int16_t)arg; + } + tmp =3D arg - lo; + sh =3D ctz64(tmp); + tmp >>=3D sh; + if (tcg_out_movi_one(s, ret, tmp)) { + tcg_out_dsll(s, ret, ret, sh); + tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo= ); + return; + } + } + /* Otherwise, put 64-bit constants into the constant pool. */ tcg_out_movi_pool(s, ret, arg, tbreg); } --=20 2.25.1