From nobody Wed May 1 18:02:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1641623762; cv=none; d=zohomail.com; s=zohoarc; b=kZcOwQ88bkHZ9K9sklbxr+6SfeaDUWPdidlTOK5H1dWpTT8E9vNrWBJb4wQLnGKzk5RaJvxK/kVfa7i6hiFFqByX2b5Ck1kEObdYFZMrMLv5fSheUo98Ti+ifrKl5t6WmMe1cqVfJVmdS1IeJMkh+K9WdUCsWiKZcOGojrvSb3o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1641623762; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=z+1Bpm5gmuPz16kiapG0JjFHPuZTPa8QQ9sXQBalCt4=; b=a8CYQkQvyKG2ICP3wr06MnlDzvn1e/xb5NeCGDyxu2z5kvfDFAalmxEoilMk9KcHhyop6j99wtCGKAT9Y/545xFzw6RJuVtevoWgrcMUZXEXj6988s99eZHEEbQEV+haGlYW7pF2mAcNyLiAJu0qqnuiNTYlbRUOLKEllqfo5o4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641623762862756.1251879489787; Fri, 7 Jan 2022 22:36:02 -0800 (PST) Received: from localhost ([::1]:58522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n65Kb-0003Sr-MA for importer@patchew.org; Sat, 08 Jan 2022 01:36:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57672) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65I3-0001Lr-Ie for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:33:30 -0500 Received: from [2607:f8b0:4864:20::534] (port=43629 helo=mail-pg1-x534.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65Hy-0003bu-NN for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:33:19 -0500 Received: by mail-pg1-x534.google.com with SMTP id 8so7653523pgc.10 for ; Fri, 07 Jan 2022 22:33:18 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id s7sm834760pfu.133.2022.01.07.22.33.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:33:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z+1Bpm5gmuPz16kiapG0JjFHPuZTPa8QQ9sXQBalCt4=; b=taCLNPZqfDZPzzGQ/xcgCYXhgB+pxau+4e5jumxUni3F2Rb4BbGyeIf3UhgNKtmMc4 cz88TyX5OQdJdDQ7tZdbu7HQL5Br1ceF38OwkQSakoTVJHJ0V5fgKbeYGsblD0Eo9ho2 KHykZspD4GlgkrKGNRLlP/KHGq+2F9oB1Fv0tbPJ3tazU5+QXV6FnLvmxB2+zyzhBOkO NKHEi4TmbrAq1tacu1qOyd7oztaZkQmT6IErIxpdDbGROPi8CAgByUQAh5na0E8gWuZU pHaV8OcsCpFXU5mRfxEFXWjvb8y7FHwMzDTFuvLRtkdLfiDabjRxIaFhAd8UwpHbRnx0 XNUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z+1Bpm5gmuPz16kiapG0JjFHPuZTPa8QQ9sXQBalCt4=; b=C/Sw7YgFfzZG5DkU7grArIHP81Xj3bjLQbWWPthwnSluHzTJSSPJ/zoKMqrfbrU2Ed z+JJOPlNE8AGNIbSDmTqFnRLX/4MWn0tdLOEszelwQLF3LWOnHcMpkQeTNskTeHBJQFh 3fz0y87a63mBCNUgzjbGKrhM/g4N4UxbirQFJe7r3PBNcV0u3yg968sJ2Y9aSxL8WOml GQD1mS6j9HO3hmguyYAbMlqIgl2FN1nDZTgVobiOQTJKPve9foWrBGh/JNRuiRzIH8rI 9wSE9qGZ4yyyVICBITNACXdmkiILHAUDQM5D4xzuYlPpbuygjL36O9kCM2mfGCDKeU4n 7LgA== X-Gm-Message-State: AOAM530yfEkobVMy3i4gFt6tjEAEE8eSVZZLWZ0hsBbaOtMkIdkRb8hS OtAnQE0nZcOnHv9+3wHacPgDTjYTQpwNuA== X-Google-Smtp-Source: ABdhPJx6r+ciPyH6Y6YsISdufQvH3+TJUYwcbEpiC2tSf3GjFVpFpxy63nBsWgUgY9xX6etkkEBLkQ== X-Received: by 2002:a63:905:: with SMTP id 5mr59709924pgj.485.1641623597268; Fri, 07 Jan 2022 22:33:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 1/7] tcg/arm: Drop support for armv4 and armv5 hosts Date: Fri, 7 Jan 2022 22:33:07 -0800 Message-Id: <20220108063313.477784-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063313.477784-1-richard.henderson@linaro.org> References: <20220108063313.477784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::534 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1641623764094100001 Content-Type: text/plain; charset="utf-8" Support for unaligned accesses is difficult for pre-v6 hosts. While debian still builds for armv4, we cannot use a compile time test, so test the architecture at runtime and error out. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.c.inc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 9d322cdba6..72b384cc28 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2474,6 +2474,11 @@ static void tcg_target_init(TCGContext *s) if (pl !=3D NULL && pl[0] =3D=3D 'v' && pl[1] >=3D '4' && pl[1] <= =3D '9') { arm_arch =3D pl[1] - '0'; } + + if (arm_arch < 6) { + error_report("TCG: ARMv%d is unsupported; exiting", arm_arch); + exit(EXIT_FAILURE); + } } =20 tcg_target_available_regs[TCG_TYPE_I32] =3D ALL_GENERAL_REGS; --=20 2.25.1 From nobody Wed May 1 18:02:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1641627843; cv=none; d=zohomail.com; s=zohoarc; b=hxuG9akEKaxf3N0CMR09bHt1qFktfLZqbe37eihQTD5x3rKHykKRrD9PX7PPRNA0cvDbfP0A708IOw0zx2AbfvZM+yjmkLV9oqxeNbkaB7LbIV2x/2ojPgXUrIcMe1PcDEN7PQoBHqIbJVUMG8IOQc4Sfv/PnLpNYa2vODQZ/iI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1641627843; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/wvvWwr9jsUcspAJECVR8Zmg/KsBGBPI4le3BDg1sNA=; b=eSaYrpo52F1fNiJvsYdECCSDVST5C6oZVMx/LUWQOmjKVGujw58dZyJBVeUN2bZSJI1aIFGw8Vj4kot5Hcdwejl4ZsKjo7VJNnTRKpdGSZR0HvHBiS9KPwIrlEl/0SjkbRZGOv9QyOM7g9v1DWy4Db+HUM4gilzYhMy8iQvrwag= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641627843240534.3003720639468; Fri, 7 Jan 2022 23:44:03 -0800 (PST) Received: from localhost ([::1]:35418 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n66OQ-00020X-7A for importer@patchew.org; Sat, 08 Jan 2022 02:44:02 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57674) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65I3-0001Ls-Hy for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:33:30 -0500 Received: from [2607:f8b0:4864:20::630] (port=36353 helo=mail-pl1-x630.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65Hz-0003c6-PT for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:33:21 -0500 Received: by mail-pl1-x630.google.com with SMTP id p14so6707009plf.3 for ; Fri, 07 Jan 2022 22:33:19 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id s7sm834760pfu.133.2022.01.07.22.33.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:33:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/wvvWwr9jsUcspAJECVR8Zmg/KsBGBPI4le3BDg1sNA=; b=BrWyzOcvw5+O6m5MmxTTNdvX8RQ2+PpNQOu52DPu2cYE6wejTy97EWwmPxbYDV1gbE YyTXiru5KF/9Ih1vrKO6X176Op4i4IPHU23bVHPx4+pRExju8zLlafpRzzXx7NAh/xPX cpAatqlfRGvKxuEueJLBV+Z7rB6TGZ75h5bfFHSsloHZrXVVu+oIY6gGh9m7yYkloOQQ 7eRBf0CB/JltSPM0mgpbi0fLoLjZRXl+Dt20tmwYTrQMwEwEciI3SVsbtC1WaYg80aAu 0MZ74QjeO6ZMTAn585pNsT1nvCBlfsdRynZLk6Cw/Xz23+KZWK7JUrjdXc3ooR0c/Uqa u9Jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/wvvWwr9jsUcspAJECVR8Zmg/KsBGBPI4le3BDg1sNA=; b=PfClUnFLwpYQRLQI1U+dBXQtYaJjz1AifcFLSCYYWRFOymKJXNN+XzQQdWZqsxAxzD oL87Z28wXtY5s0k0BSI+jBHtNDI9+HxNzKaxjUEr4i7kliPhab6WtSR8pB/H+2L0sYkI DSz5tcMxb7AmrkyFCtt5QsMo4Q22NjMe7aE4tSl3iQlmdK3OFVLu7G2prArN73rqF9UJ G6JQKQf2qmb6E3Svdaho/0jdLjnOCDR/5I9JHWuMaMFlPr9+ojF1hDEd5lwMzNNR5qW9 ujVgpF5nYANgjs6Bb92SXUqA+a5spPDMdRG6PdfD5p7s2WNJvzuu6Zp33Ilf34NRZq37 Czpw== X-Gm-Message-State: AOAM530JXkf7Z8206FCf8eLMZDcm8HNPhEb9mYL9LHl5k8Yi0CyZEUyE GrNc2nQ4wvdbmhjBYf6BYbXvQ4V7INIeUg== X-Google-Smtp-Source: ABdhPJy5NC4v8Wlao5OqR+jyl2hNe9O6F8sKG8u245nV0K7nGQAQfQOJnlidGyQ9t/I9k/RykmgmMA== X-Received: by 2002:a17:902:76c3:b0:149:ac0a:1662 with SMTP id j3-20020a17090276c300b00149ac0a1662mr35086311plt.92.1641623598467; Fri, 07 Jan 2022 22:33:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 2/7] tcg/arm: Remove use_armv5t_instructions Date: Fri, 7 Jan 2022 22:33:08 -0800 Message-Id: <20220108063313.477784-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063313.477784-1-richard.henderson@linaro.org> References: <20220108063313.477784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::630 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1641627845682100001 Content-Type: text/plain; charset="utf-8" This is now always true, since we require armv6. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.h | 3 +-- tcg/arm/tcg-target.c.inc | 35 ++++++----------------------------- 2 files changed, 7 insertions(+), 31 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index f41b809554..5c9ba5feea 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -28,7 +28,6 @@ =20 extern int arm_arch; =20 -#define use_armv5t_instructions (__ARM_ARCH >=3D 5 || arm_arch >=3D 5) #define use_armv6_instructions (__ARM_ARCH >=3D 6 || arm_arch >=3D 6) #define use_armv7_instructions (__ARM_ARCH >=3D 7 || arm_arch >=3D 7) =20 @@ -109,7 +108,7 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 -#define TCG_TARGET_HAS_clz_i32 use_armv5t_instructions +#define TCG_TARGET_HAS_clz_i32 1 #define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions #define TCG_TARGET_HAS_ctpop_i32 0 #define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 72b384cc28..fd30e6e99e 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -596,11 +596,7 @@ static void tcg_out_b_reg(TCGContext *s, ARMCond cond,= TCGReg rn) * Unless the C portion of QEMU is compiled as thumb, we don't need * true BX semantics; merely a branch to an address held in a register. */ - if (use_armv5t_instructions) { - tcg_out_bx_reg(s, cond, rn); - } else { - tcg_out_mov_reg(s, cond, TCG_REG_PC, rn); - } + tcg_out_bx_reg(s, cond, rn); } =20 static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, @@ -1247,14 +1243,7 @@ static void tcg_out_goto(TCGContext *s, ARMCond cond= , const tcg_insn_unit *addr) } =20 /* LDR is interworking from v5t. */ - if (arm_mode || use_armv5t_instructions) { - tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); - return; - } - - /* else v4t */ - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); - tcg_out_bx_reg(s, COND_AL, TCG_REG_TMP); + tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); } =20 /* @@ -1270,26 +1259,14 @@ static void tcg_out_call(TCGContext *s, const tcg_i= nsn_unit *addr) if (disp - 8 < 0x02000000 && disp - 8 >=3D -0x02000000) { if (arm_mode) { tcg_out_bl_imm(s, COND_AL, disp); - return; - } - if (use_armv5t_instructions) { + } else { tcg_out_blx_imm(s, disp); - return; } + return; } =20 - if (use_armv5t_instructions) { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); - tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); - } else if (arm_mode) { - /* ??? Know that movi_pool emits exactly 1 insn. */ - tcg_out_mov_reg(s, COND_AL, TCG_REG_R14, TCG_REG_PC); - tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri); - } else { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); - tcg_out_mov_reg(s, COND_AL, TCG_REG_R14, TCG_REG_PC); - tcg_out_bx_reg(s, COND_AL, TCG_REG_TMP); - } + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); + tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); } =20 static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) --=20 2.25.1 From nobody Wed May 1 18:02:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1641626328; cv=none; d=zohomail.com; s=zohoarc; b=e121qWi9gY8m9nplUDI7iF2FY4ODTM9Bkobu/OSEdDfZjTlBu7C15Bf6HtK4Ls8uF4q37B7U507gB/AwUcOh8z/ACPUgqsWESGYPUcKuDmdHSIpg5DkoAZnuil+MXnTrqYO2dQim/R68NMXkQ4WklpQwCubGYZyerauzcCj3uEU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1641626328; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qiheRZfPkN/WV7mHuxWK1QcAkexQvnGwQPuHTMHYn+4=; b=KRMStfXcJwhxn92Df5yRtdJOxRDYnW60ZY1BDJ3VEd5Kxw7fJOZgeuQTCV8oSRKnG1Nkum+JRc8Nkd+JzExnbo1tJPfkGfflRP5mZZmBHIOMX40/fjxtY4i1H2bTKCgfY0V+AdDA/IOIywlmfoLzsk1FDjXkvI5Kv2I1964vFcQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641626328230134.7409604989282; Fri, 7 Jan 2022 23:18:48 -0800 (PST) Received: from localhost ([::1]:39356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n65zz-0000Cy-2u for importer@patchew.org; Sat, 08 Jan 2022 02:18:47 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57696) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65I3-0001Lt-Jo for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:33:30 -0500 Received: from [2607:f8b0:4864:20::102f] (port=53010 helo=mail-pj1-x102f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65I1-0003cH-KD for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:33:23 -0500 Received: by mail-pj1-x102f.google.com with SMTP id pj2so5878023pjb.2 for ; Fri, 07 Jan 2022 22:33:21 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id s7sm834760pfu.133.2022.01.07.22.33.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:33:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qiheRZfPkN/WV7mHuxWK1QcAkexQvnGwQPuHTMHYn+4=; b=NH15t+vY1L+ytv+reMmyoaTPmm03JpeJiBcz/qBYOD199UK9+h6TaYiGsuCBO46E1i 3bK4NJzsS1K0GU1WUTy5RxIwBRSZBjejG27esweGYvwhrUGCeTXN1LiBGnMsNgSkJ0g8 Y7sH44syptNf4TsQdLYbSCRNdLG/i9jI4CGrr9+0xweqGcvx70PbeOfa1cX/qwny3fNj sVP1Cxf9Nw6Z2h/fa55xNizm6J2+NUsO30xBjbr3hDIWb9rOiNN7kEA+N+GctVUNqK9h BATGLn76tNdO61ERZ9SRI5CxGRGObKwRthlj3ML1OHYTJnaXczZ9OKL3Y0MdBBRCKdDX FI3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qiheRZfPkN/WV7mHuxWK1QcAkexQvnGwQPuHTMHYn+4=; b=rdxl37VfB5wphorPWuMHbFZuUvs0VlkAZwgDy5kPFnnaADwkNYWBGBYi0pr5nZqT1p COcIzbCcmxuBq1xJxlrCZOfG5ARvkjs3Kh8LHK4YfWPLO73k1D5WgAukarPHI2F+cfz3 NytKWAIf1g4fXYuuSEuuEACJ9/o9AgbzXh5bRCZcZpjVvpwy/+1Y3JYSJOYf38ADio0N 3HYJjWJ5CBzpR7TLXdZyY66KzzEUDwf/N9i9QiF6d4b6DE6Do7SvKOvpz8bM6oWZcR60 UWPIq/sQFgCOZjeGAXdUROR+UgVSJxCTviHB1N7eP2bIhZmh/w2uYLdYBWsExKqDe6jA pUzw== X-Gm-Message-State: AOAM53163TWjZcvSFGHcJP3iT1fCXgQ5cz1NjMdJ5E3JZQsoTyNiu1DR Aq8M5CZ7xYMwGacYIRIvbTAXtQKkqEcKzg== X-Google-Smtp-Source: ABdhPJxOTxfbo9OrBHPH+x+11FB2/MgDwe5uELHNi8wHxaBVEzm63p7gYS+hS9DRK3RtmboFY1jq1A== X-Received: by 2002:a17:903:32c3:b0:14a:1597:99ff with SMTP id i3-20020a17090332c300b0014a159799ffmr2594309plr.13.1641623600254; Fri, 07 Jan 2022 22:33:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 3/7] tcg/arm: Remove use_armv6_instructions Date: Fri, 7 Jan 2022 22:33:09 -0800 Message-Id: <20220108063313.477784-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063313.477784-1-richard.henderson@linaro.org> References: <20220108063313.477784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1641626329603100001 Content-Type: text/plain; charset="utf-8" This is now always true, since we require armv6. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.h | 1 - tcg/arm/tcg-target.c.inc | 192 ++++++--------------------------------- 2 files changed, 27 insertions(+), 166 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 5c9ba5feea..1dd4cd5377 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -28,7 +28,6 @@ =20 extern int arm_arch; =20 -#define use_armv6_instructions (__ARM_ARCH >=3D 6 || arm_arch >=3D 6) #define use_armv7_instructions (__ARM_ARCH >=3D 7 || arm_arch >=3D 7) =20 #undef TCG_TARGET_STACK_GROWSUP diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index fd30e6e99e..ea8b90e6e2 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -923,17 +923,6 @@ static void tcg_out_dat_rIN(TCGContext *s, ARMCond con= d, ARMInsn opc, static void tcg_out_mul32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn, TCGReg rm) { - /* if ArchVersion() < 6 && d =3D=3D n then UNPREDICTABLE; */ - if (!use_armv6_instructions && rd =3D=3D rn) { - if (rd =3D=3D rm) { - /* rd =3D=3D rn =3D=3D rm; copy an input to tmp first. */ - tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn); - rm =3D rn =3D TCG_REG_TMP; - } else { - rn =3D rm; - rm =3D rd; - } - } /* mul */ tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn); } @@ -941,17 +930,6 @@ static void tcg_out_mul32(TCGContext *s, ARMCond cond,= TCGReg rd, static void tcg_out_umull32(TCGContext *s, ARMCond cond, TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) { - /* if ArchVersion() < 6 && (dHi =3D=3D n || dLo =3D=3D n) then UNPREDI= CTABLE; */ - if (!use_armv6_instructions && (rd0 =3D=3D rn || rd1 =3D=3D rn)) { - if (rd0 =3D=3D rm || rd1 =3D=3D rm) { - tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn); - rn =3D TCG_REG_TMP; - } else { - TCGReg t =3D rn; - rn =3D rm; - rm =3D t; - } - } /* umull */ tcg_out32(s, (cond << 28) | 0x00800090 | (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); @@ -960,17 +938,6 @@ static void tcg_out_umull32(TCGContext *s, ARMCond con= d, TCGReg rd0, static void tcg_out_smull32(TCGContext *s, ARMCond cond, TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) { - /* if ArchVersion() < 6 && (dHi =3D=3D n || dLo =3D=3D n) then UNPREDI= CTABLE; */ - if (!use_armv6_instructions && (rd0 =3D=3D rn || rd1 =3D=3D rn)) { - if (rd0 =3D=3D rm || rd1 =3D=3D rm) { - tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn); - rn =3D TCG_REG_TMP; - } else { - TCGReg t =3D rn; - rn =3D rm; - rm =3D t; - } - } /* smull */ tcg_out32(s, (cond << 28) | 0x00c00090 | (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); @@ -990,15 +957,8 @@ static void tcg_out_udiv(TCGContext *s, ARMCond cond, =20 static void tcg_out_ext8s(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg r= n) { - if (use_armv6_instructions) { - /* sxtb */ - tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn); - } else { - tcg_out_dat_reg(s, cond, ARITH_MOV, - rd, 0, rn, SHIFT_IMM_LSL(24)); - tcg_out_dat_reg(s, cond, ARITH_MOV, - rd, 0, rd, SHIFT_IMM_ASR(24)); - } + /* sxtb */ + tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn); } =20 static void __attribute__((unused)) @@ -1009,113 +969,37 @@ tcg_out_ext8u(TCGContext *s, ARMCond cond, TCGReg r= d, TCGReg rn) =20 static void tcg_out_ext16s(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg = rn) { - if (use_armv6_instructions) { - /* sxth */ - tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn); - } else { - tcg_out_dat_reg(s, cond, ARITH_MOV, - rd, 0, rn, SHIFT_IMM_LSL(16)); - tcg_out_dat_reg(s, cond, ARITH_MOV, - rd, 0, rd, SHIFT_IMM_ASR(16)); - } + /* sxth */ + tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn); } =20 static void tcg_out_ext16u(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg = rn) { - if (use_armv6_instructions) { - /* uxth */ - tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn); - } else { - tcg_out_dat_reg(s, cond, ARITH_MOV, - rd, 0, rn, SHIFT_IMM_LSL(16)); - tcg_out_dat_reg(s, cond, ARITH_MOV, - rd, 0, rd, SHIFT_IMM_LSR(16)); - } + /* uxth */ + tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn); } =20 static void tcg_out_bswap16(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn, int flags) { - if (use_armv6_instructions) { - if (flags & TCG_BSWAP_OS) { - /* revsh */ - tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn); - return; - } - - /* rev16 */ - tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); - if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) =3D=3D TCG_BSWAP_OZ) { - /* uxth */ - tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rd); - } + if (flags & TCG_BSWAP_OS) { + /* revsh */ + tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn); return; } =20 - if (flags =3D=3D 0) { - /* - * For stores, no input or output extension: - * rn =3D xxAB - * lsr tmp, rn, #8 tmp =3D 0xxA - * and tmp, tmp, #0xff tmp =3D 000A - * orr rd, tmp, rn, lsl #8 rd =3D xABA - */ - tcg_out_dat_reg(s, cond, ARITH_MOV, - TCG_REG_TMP, 0, rn, SHIFT_IMM_LSR(8)); - tcg_out_dat_imm(s, cond, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, 0xff= ); - tcg_out_dat_reg(s, cond, ARITH_ORR, - rd, TCG_REG_TMP, rn, SHIFT_IMM_LSL(8)); - return; + /* rev16 */ + tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); + if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) =3D=3D TCG_BSWAP_OZ) { + /* uxth */ + tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rd); } - - /* - * Byte swap, leaving the result at the top of the register. - * We will then shift down, zero or sign-extending. - */ - if (flags & TCG_BSWAP_IZ) { - /* - * rn =3D 00AB - * ror tmp, rn, #8 tmp =3D B00A - * orr tmp, tmp, tmp, lsl #16 tmp =3D BA00 - */ - tcg_out_dat_reg(s, cond, ARITH_MOV, - TCG_REG_TMP, 0, rn, SHIFT_IMM_ROR(8)); - tcg_out_dat_reg(s, cond, ARITH_ORR, - TCG_REG_TMP, TCG_REG_TMP, TCG_REG_TMP, - SHIFT_IMM_LSL(16)); - } else { - /* - * rn =3D xxAB - * and tmp, rn, #0xff00 tmp =3D 00A0 - * lsl tmp, tmp, #8 tmp =3D 0A00 - * orr tmp, tmp, rn, lsl #24 tmp =3D BA00 - */ - tcg_out_dat_rI(s, cond, ARITH_AND, TCG_REG_TMP, rn, 0xff00, 1); - tcg_out_dat_reg(s, cond, ARITH_MOV, - TCG_REG_TMP, 0, TCG_REG_TMP, SHIFT_IMM_LSL(8)); - tcg_out_dat_reg(s, cond, ARITH_ORR, - TCG_REG_TMP, TCG_REG_TMP, rn, SHIFT_IMM_LSL(24)); - } - tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, TCG_REG_TMP, - (flags & TCG_BSWAP_OS - ? SHIFT_IMM_ASR(8) : SHIFT_IMM_LSR(8))); } =20 static void tcg_out_bswap32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg= rn) { - if (use_armv6_instructions) { - /* rev */ - tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); - } else { - tcg_out_dat_reg(s, cond, ARITH_EOR, - TCG_REG_TMP, rn, rn, SHIFT_IMM_ROR(16)); - tcg_out_dat_imm(s, cond, ARITH_BIC, - TCG_REG_TMP, TCG_REG_TMP, 0xff | 0x800); - tcg_out_dat_reg(s, cond, ARITH_MOV, - rd, 0, rn, SHIFT_IMM_ROR(8)); - tcg_out_dat_reg(s, cond, ARITH_EOR, - rd, rd, TCG_REG_TMP, SHIFT_IMM_LSR(8)); - } + /* rev */ + tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); } =20 static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, @@ -1283,7 +1167,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) { if (use_armv7_instructions) { tcg_out32(s, INSN_DMB_ISH); - } else if (use_armv6_instructions) { + } else { tcg_out32(s, INSN_DMB_MCR); } } @@ -1489,8 +1373,7 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg= argreg, if (argreg & 1) { argreg++; } - if (use_armv6_instructions && argreg >=3D 4 - && (arglo & 1) =3D=3D 0 && arghi =3D=3D arglo + 1) { + if (argreg >=3D 4 && (arglo & 1) =3D=3D 0 && arghi =3D=3D arglo + 1) { tcg_out_strd_8(s, COND_AL, arglo, TCG_REG_CALL_STACK, (argreg - 4) * 4); return argreg + 2; @@ -1520,8 +1403,6 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg = addrlo, TCGReg addrhi, int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); - int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); =20 @@ -1534,12 +1415,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg= addrlo, TCGReg addrhi, } =20 /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ - if (use_armv6_instructions) { - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); - } else { - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R0, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R1, TCG_AREG0, table_off); - } + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); =20 /* Extract the tlb index from the address into R0. */ tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, @@ -1550,7 +1426,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg = addrlo, TCGReg addrhi, * Load the tlb comparator into R2/R3 and the fast path addend into R1. */ if (cmp_off =3D=3D 0) { - if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { + if (TARGET_LONG_BITS =3D=3D 64) { tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); } else { tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); @@ -1558,15 +1434,12 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, } else { tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); - if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { + if (TARGET_LONG_BITS =3D=3D 64) { tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); } else { tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); } } - if (!use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R3, TCG_REG_R1, cmp_off + 4); - } =20 /* Load the tlb addend. */ tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, @@ -1631,7 +1504,6 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) TCGReg argreg, datalo, datahi; MemOpIdx oi =3D lb->oi; MemOp opc =3D get_memop(oi); - void *func; =20 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; @@ -1646,18 +1518,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) argreg =3D tcg_out_arg_imm32(s, argreg, oi); argreg =3D tcg_out_arg_reg32(s, argreg, TCG_REG_R14); =20 - /* For armv6 we can use the canonical unsigned helpers and minimize - icache usage. For pre-armv6, use the signed helpers since we do - not have a single insn sign-extend. */ - if (use_armv6_instructions) { - func =3D qemu_ld_helpers[opc & MO_SIZE]; - } else { - func =3D qemu_ld_helpers[opc & MO_SSIZE]; - if (opc & MO_SIGN) { - opc =3D MO_UL; - } - } - tcg_out_call(s, func); + /* Use the canonical unsigned helpers and minimize icache usage. */ + tcg_out_call(s, qemu_ld_helpers[opc & MO_SIZE]); =20 datalo =3D lb->datalo_reg; datahi =3D lb->datahi_reg; @@ -1760,7 +1622,7 @@ static void tcg_out_qemu_ld_index(TCGContext *s, MemO= p opc, break; case MO_Q: /* Avoid ldrd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU && use_armv6_instructions + if (USING_SOFTMMU && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend); } else if (datalo !=3D addend) { @@ -1803,7 +1665,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, Mem= Op opc, TCGReg datalo, break; case MO_Q: /* Avoid ldrd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU && use_armv6_instructions + if (USING_SOFTMMU && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, 0); } else if (datalo =3D=3D addrlo) { @@ -1880,7 +1742,7 @@ static void tcg_out_qemu_st_index(TCGContext *s, ARMC= ond cond, MemOp opc, break; case MO_64: /* Avoid strd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU && use_armv6_instructions + if (USING_SOFTMMU && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_strd_r(s, cond, datalo, addrlo, addend); } else { @@ -1912,7 +1774,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Mem= Op opc, TCGReg datalo, break; case MO_64: /* Avoid strd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU && use_armv6_instructions + if (USING_SOFTMMU && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0); } else { --=20 2.25.1 From nobody Wed May 1 18:02:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1641627428; cv=none; d=zohomail.com; s=zohoarc; b=ioC79CQ0s4sHsYbvDxzGx+qQNFaum5HoM/Cm2c8nx6D6AHzyK4snYEqOkABQ67Uv1ZBeYfpU16BQhZ96Nr3S1LmD730rOto2EEHWtGyqZE+ohODwZARpUle8jfKxzcHBcGC+0z//WYcMHhExfODoKQSqvFe8Goj4I4uDzw11tkU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1641627428; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/AYwq3dHnlsFGe0HxehxjaeDvoLxdWXzGgDqUZldkDo=; b=fgVUX70lHIx0jPZOOEaBWeepksMnWESIvyJolD7YHHx3ljiRP/ORuHtx2oc+dpz6pGeHhL4YpmKX30hG6qcMJVhSDTlSawPPRUr0Bo5x342cXnEYMGgIxA5ZULYHR5N8Ke9H32t3PEe5Y+G7gz09pL9H3GpwWPCuoR6qjKojWQ8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641627428827250.76471296683462; Fri, 7 Jan 2022 23:37:08 -0800 (PST) Received: from localhost ([::1]:55318 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n66Hd-00049P-V7 for importer@patchew.org; Sat, 08 Jan 2022 02:37:02 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65I4-0001Lu-KN for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:33:30 -0500 Received: from [2607:f8b0:4864:20::62a] (port=36860 helo=mail-pl1-x62a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65I3-0003cY-5Q for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:33:24 -0500 Received: by mail-pl1-x62a.google.com with SMTP id p14so6707086plf.3 for ; Fri, 07 Jan 2022 22:33:22 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id s7sm834760pfu.133.2022.01.07.22.33.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:33:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/AYwq3dHnlsFGe0HxehxjaeDvoLxdWXzGgDqUZldkDo=; b=TBmM4wK2YA18yUt9+NsWvwgYuCjxSZ5BWVk7I1bBOY1bsZCnuEbgeZk5gQHAEZfxXM rf/wN4BTE+5/ygM7NP3YyyMkfymTQu8P9kIocaRXqi/CrMyifCoD6C/d0iLBoHDuR0mo kabh3z6GyL68Q+uyjMfE5+lel0VgNMUsXuBeu28ZRQU3IXGcpOHHX1NfLop1zamTy+Oy /RZQshH9+KUgtpFCGCkSWp9yS2RHBzQzvzpMTx2yC5OjEzz/VFW3e81XGl0iC2/z+3nG nl8EYwTQXr8YWf5Ugh/VNaXxZq8Jo5DrkHjLCFqjEeHbqZYBfuV8uBLQxPaE6flo+MSJ 1Q7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/AYwq3dHnlsFGe0HxehxjaeDvoLxdWXzGgDqUZldkDo=; b=z3VCNlHI2w6sl1NeAf4G+f/BWnsz5g/Aa0wO5qYtR/mHb+CrhqsSPKk/G/kiDU7kda g89D5qnLMmUlckBBgXywfy7gXNND2nudtlfRUDtwOcXdb36iNvq90338aw0oyyf9wuhY DparLlUMTgeMaR30sbsBhdqCpS/q6gbZJLkHLjn7iOL9hbECofB8PSR6eLy9AbJ1tZeR aHwCtK8GdAtQGGvgkubhTjqaMZDXMuN34Gm5zlYLCURo0UYVNKAeTPhwryC3o8hgCIbv YL4EvVWtg0YncbP3FIyKy20Amj4MKbnbNmmqmKKC9FET5F1yNXGGVjm58W4Muvy36ySs BTwQ== X-Gm-Message-State: AOAM530g8xp/VODls92Ed6YmIaK+sWJzpGFk8E91g3ZLLP/3AvdRhb/L wY93MQCT63PrGePv0pzylIoL1Z2LZExwnA== X-Google-Smtp-Source: ABdhPJxrNG+2jljTKdsYolxSCwaoVg8OL07yoLqjVN9Dm4gS7F4yed3KIYxckLU7fIfIxY16WWqxyg== X-Received: by 2002:a17:902:d4c8:b0:149:c99e:dd83 with SMTP id o8-20020a170902d4c800b00149c99edd83mr16295027plg.146.1641623601943; Fri, 07 Jan 2022 22:33:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 4/7] tcg/arm: Check alignment for ldrd and strd Date: Fri, 7 Jan 2022 22:33:10 -0800 Message-Id: <20220108063313.477784-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063313.477784-1-richard.henderson@linaro.org> References: <20220108063313.477784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62a (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1641627431130100001 Content-Type: text/plain; charset="utf-8" We will shortly allow the use of unaligned memory accesses, and these require proper alignment. Use get_alignment_bits to verify and remove USING_SOFTMMU. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.c.inc | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index ea8b90e6e2..8a20224dd1 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -35,12 +35,6 @@ bool use_neon_instructions; #endif =20 /* ??? Ought to think about changing CONFIG_SOFTMMU to always defined. */ -#ifdef CONFIG_SOFTMMU -# define USING_SOFTMMU 1 -#else -# define USING_SOFTMMU 0 -#endif - #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", @@ -1621,8 +1615,8 @@ static void tcg_out_qemu_ld_index(TCGContext *s, MemO= p opc, tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend); break; case MO_Q: - /* Avoid ldrd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU + /* LDRD requires alignment; double-check that. */ + if (get_alignment_bits(opc) >=3D MO_64 && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend); } else if (datalo !=3D addend) { @@ -1664,8 +1658,8 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, Mem= Op opc, TCGReg datalo, tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); break; case MO_Q: - /* Avoid ldrd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU + /* LDRD requires alignment; double-check that. */ + if (get_alignment_bits(opc) >=3D MO_64 && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, 0); } else if (datalo =3D=3D addrlo) { @@ -1741,8 +1735,8 @@ static void tcg_out_qemu_st_index(TCGContext *s, ARMC= ond cond, MemOp opc, tcg_out_st32_r(s, cond, datalo, addrlo, addend); break; case MO_64: - /* Avoid strd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU + /* STRD requires alignment; double-check that. */ + if (get_alignment_bits(opc) >=3D MO_64 && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_strd_r(s, cond, datalo, addrlo, addend); } else { @@ -1773,8 +1767,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Mem= Op opc, TCGReg datalo, tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); break; case MO_64: - /* Avoid strd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU + /* STRD requires alignment; double-check that. */ + if (get_alignment_bits(opc) >=3D MO_64 && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0); } else { --=20 2.25.1 From nobody Wed May 1 18:02:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1641624902; cv=none; d=zohomail.com; s=zohoarc; b=haamdVTBkFzIib8rEo+aeXFUfbGuZWR7IIE2/8ZjJ2VO+dQm6onRS898PbYcfWnegkvdiq5hcHm6806Z7MRO+XgDJ71sKtrbzuhJM8z2fYcSuwvS7vHZ2J4nKx9cSmbN10UbJu+1sou2cDTf9r0MogSx1igjZH3OnaZyXeFUJ2A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1641624902; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Y0Tsxo+6wwyGjGP1LUKn3jwXiyZIm9+mz8iPkc8Ojds=; b=maCqBdupsw9KOkfz3dlthECAqoDqrNzevOjVR+Lw0n/Wg6q3i34wZupiob3ePFyv7L5eu/P2mBICzaXlnZ32wPFdCqOkjWz6rrmLigy+qX6R4ht4EyJ36/LS7wFxpLWDOVdTFKQDCWc5BaPquR9pE4So36YI0uT/c9bLMV5N1zU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641624902283952.9586603745025; Fri, 7 Jan 2022 22:55:02 -0800 (PST) Received: from localhost ([::1]:38536 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n65cy-0001bO-L8 for importer@patchew.org; Sat, 08 Jan 2022 01:55:00 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57722) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65I6-0001M2-9Q for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:33:34 -0500 Received: from [2607:f8b0:4864:20::102a] (port=54952 helo=mail-pj1-x102a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65I4-0003ch-RF for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:33:26 -0500 Received: by mail-pj1-x102a.google.com with SMTP id oa15so6230868pjb.4 for ; Fri, 07 Jan 2022 22:33:24 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id s7sm834760pfu.133.2022.01.07.22.33.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:33:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y0Tsxo+6wwyGjGP1LUKn3jwXiyZIm9+mz8iPkc8Ojds=; b=Ln4P5WnsUcLvpdXdqnMPVLWmUroSdcwfUscxRuHu80Trv1uVLnyBrAxtTFJjX5wo5K K6BJcUSrtLTt7Y64+ZO2OPh5VgOzNx2QWnzcYR7qsCE36J+IV/mTw3Ake5khoEW12KsU ZbaFxeelcIjZ3LowekyLkoRkTMWFJmG/b+x1nWvrmsuR6FBNkDRBG7TSlhmblmcj9c2p aAUrAZKr7T7SkRdlUwqBVzLeEKfVwIm10U7zSRVXeoOhAvhEcZvKwNYvlEeeoFXNWr7y SvZvzTGxjKxvMthalQOrVdMcw0ey53SSxvjyj8JfIvAFUtGKVUNHieQCGmOtkbVc+TAp Pnig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y0Tsxo+6wwyGjGP1LUKn3jwXiyZIm9+mz8iPkc8Ojds=; b=fbCQVF732Edvcm7E4FEULLZzaeBzzzd4Zrxl/D7bchwVwULnmxUACCRDCLMmhR8lDG YYF89x0ZhQDHXFw/tddn3rZs7s/CLvqwh4GIRcPcnmVu2ezJaXBozf50Rvef+hWA9peF qrvN4o4gDfQllx99ZLzSA8AsO2qesk0UYZv5UIfk+lArQLb6HylVAev1uS9efStnq3sa t4BqRThKKgWEjqaGoxxLixpgMCRekhJzQr39ZE5Q/Vhr+3N/bPB3LW8kvv8om65lWASp UIAZbjm+/vX34Xe0lcsa85t+n4tZd5KJ/WRSLcf5uurh+V7CptoBZN6PjxhWFgkY6dIt bLrg== X-Gm-Message-State: AOAM530fFv3fnRByqkluiGj0CsKsH93PvBPVsAjPFo9xEwK1kSO7PAxj drgskuVzKRFy60w2VvVKQzSJsyNuymiT9A== X-Google-Smtp-Source: ABdhPJx80KxOdH5QdcxR3uSUDM8+sYMHGvbaRVTHJQWGzDhvxgbmxzsUBQkGOhKlVpb01aZjOVzpLw== X-Received: by 2002:a17:90b:1bd1:: with SMTP id oa17mr19220455pjb.242.1641623603554; Fri, 07 Jan 2022 22:33:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 5/7] tcg/arm: Support unaligned access for softmmu Date: Fri, 7 Jan 2022 22:33:11 -0800 Message-Id: <20220108063313.477784-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063313.477784-1-richard.henderson@linaro.org> References: <20220108063313.477784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102a (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1641624903517100001 Content-Type: text/plain; charset="utf-8" From armv6, the architecture supports unaligned accesses. All we need to do is perform the correct alignment check in tcg_out_tlb_read. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.c.inc | 39 ++++++++++++++++++--------------------- 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 8a20224dd1..b6ef279cae 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -34,7 +34,6 @@ bool use_idiv_instructions; bool use_neon_instructions; #endif =20 -/* ??? Ought to think about changing CONFIG_SOFTMMU to always defined. */ #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", @@ -1397,16 +1396,9 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg= addrlo, TCGReg addrhi, int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_bits =3D get_alignment_bits(opc); - - /* - * We don't support inline unaligned acceses, but we can easily - * support overalignment checks. - */ - if (a_bits < s_bits) { - a_bits =3D s_bits; - } + unsigned s_mask =3D (1 << (opc & MO_SIZE)) - 1; + unsigned a_mask =3D (1 << get_alignment_bits(opc)) - 1; + TCGReg t_addr; =20 /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); @@ -1441,27 +1433,32 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, =20 /* * Check alignment, check comparators. - * Do this in no more than 3 insns. Use MOVW for v7, if possible, + * Do this in 2-4 insns. Use MOVW for v7, if possible, * to reduce the number of sequential conditional instructions. * Almost all guests have at least 4k pages, which means that we need * to clear at least 9 bits even for an 8-byte memory, which means it * isn't worth checking for an immediate operand for BIC. */ + /* For unaligned accesses, test the page of the last byte. */ + t_addr =3D addrlo; + if (a_mask < s_mask) { + t_addr =3D TCG_REG_R0; + tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, + addrlo, s_mask - a_mask); + } if (use_armv7_instructions && TARGET_PAGE_BITS <=3D 16) { - tcg_target_ulong mask =3D ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1)= ); - - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask); + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a_mas= k)); tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, - addrlo, TCG_REG_TMP, 0); + t_addr, TCG_REG_TMP, 0); tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP,= 0); } else { - if (a_bits) { - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, - (1 << a_bits) - 1); + if (a_mask) { + tcg_debug_assert(a_mask <=3D 0xff); + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); } - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, addrlo, + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); - tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, + tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); } --=20 2.25.1 From nobody Wed May 1 18:02:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1641627821; cv=none; d=zohomail.com; s=zohoarc; b=YphD9zkiimxb703pmRE1OyJkI+TjuZyLmKBF9RBYRwQ2F65pieY5n+vQz2uXVSSUp0G+1WRNf+wORUuuE/+lCGyue+m3bGJ/Z02+K5Hwi99NVL7XXymgLaiKCvapivZCdxqzkgm+IgxlMRDxYpeS7Ld2aMOTsVN/t0d/OnZ2pgY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1641627821; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=n8gyEPwJzcgJlBpee50d2KiUG6+KHxHBpSh7KBn9vpk=; b=Qd+9eW1BzLIyoi2Ccz9C9y58GM4ip5PTK7UbX7oUyvUbx+b+LnZeWpiw8IYO6hP/MD7bDe24Dt2tEEmIz0Ek+IeEcR4n4ld2X/fkx2j+YkWgPEM8i1UKuXQM27e5lHYOs/F6jFbLbPsaBzet+7VIOi4grTElCqzsFnbvPRVREeU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641627821374537.079120410748; Fri, 7 Jan 2022 23:43:41 -0800 (PST) Received: from localhost ([::1]:35076 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n66O4-0001mW-A3 for importer@patchew.org; Sat, 08 Jan 2022 02:43:40 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65IE-0001ME-Pd for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:33:36 -0500 Received: from [2607:f8b0:4864:20::102b] (port=50764 helo=mail-pj1-x102b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65I7-0003cv-6P for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:33:28 -0500 Received: by mail-pj1-x102b.google.com with SMTP id gp5so7109505pjb.0 for ; Fri, 07 Jan 2022 22:33:26 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id s7sm834760pfu.133.2022.01.07.22.33.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:33:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n8gyEPwJzcgJlBpee50d2KiUG6+KHxHBpSh7KBn9vpk=; b=TPdJ0Xdt8DFWsKDC9mvsysDkQ45FGcn0BTCRF7mMS80dzmEp2pO7AawXHuNhsxSOlP 7QlfvRK01fG3mcSRNCkEecrRD2F4HQPMP18cHCIEX5eyT7FWYFSDUmta8hxt5iyu7yT0 3dewr5P5sxiBMWUstXopFgQgYW1kQ+zQCGlSv+NCDlPaapVSxLVCfyypn8r9D134vg+z yJtRtl+cA95OhWMEGXGLw+yWSx6NCPi2zOhzkNlLcUMu5yvLJnGPCph2KgyS/4IscZNM lQmJCgl/W6KshdIwIuw/lSRZwnoFGIB1Kt4Yg9QO9Z+YJk7xeg9coQGvTRPCIZ0qNIVm voSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n8gyEPwJzcgJlBpee50d2KiUG6+KHxHBpSh7KBn9vpk=; b=sQvVLAUIaO8SZbBARyi0gQpJyoMxIhU9Fq0btIZHtTK5msYtUX9HOxV7XPCQjZy2OD H0fcq3xlAcYCzuKvbAj2CngLTuj9eGB9i7fDU5J+0luNjfk6yQMo8dvTAPhUo8mu6e9v DyHNj/y+gLOGG0HNbjW5L5BsO30sbEZm4BFH1fFfx+5tuIdlHxPWEBEvChB6Rn5ZlcnA KnW/uKpg7d9k5QeQiOKTcA0MA17+kXwJK0Nxi0GtqZcAJy0N4N/XfejQs3Q6X5uIs6f2 hVLqerdGUR3nLTiM4NRM/T33MZmH5lwaeHKUGMua9LFApvVN/34G8mH0kRa/NkPH0qMH Fkgg== X-Gm-Message-State: AOAM531SyjBVsTUPC6hG0DSQlSj1cqc6xdjnR67dkjaSUGkQDg1tE6G1 RT8/pbykfLEkdx5QiNqjjuYIVlYCk2n37A== X-Google-Smtp-Source: ABdhPJwq1rA9GOqX4+quYI7IsifetYTiCOAloLzFhSuHlEZhB1jgkqepZ9FtWsete2O1xnoAbPMyJQ== X-Received: by 2002:a17:90b:3ec5:: with SMTP id rm5mr19449380pjb.100.1641623605934; Fri, 07 Jan 2022 22:33:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 6/7] tcg/arm: Reserve a register for guest_base Date: Fri, 7 Jan 2022 22:33:12 -0800 Message-Id: <20220108063313.477784-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063313.477784-1-richard.henderson@linaro.org> References: <20220108063313.477784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1641627823590100001 Content-Type: text/plain; charset="utf-8" Reserve a register for the guest_base using aarch64 for reference. By doing so, we do not have to recompute it for every memory load. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.c.inc | 39 ++++++++++++++++++++++++++++----------- 1 file changed, 28 insertions(+), 11 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index b6ef279cae..1c00311877 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -84,6 +84,9 @@ static const int tcg_target_call_oarg_regs[2] =3D { =20 #define TCG_REG_TMP TCG_REG_R12 #define TCG_VEC_TMP TCG_REG_Q15 +#ifndef CONFIG_SOFTMMU +#define TCG_REG_GUEST_BASE TCG_REG_R11 +#endif =20 typedef enum { COND_EQ =3D 0x0, @@ -1590,7 +1593,8 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) =20 static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addend) + TCGReg addrlo, TCGReg addend, + bool scratch_addend) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); @@ -1616,7 +1620,7 @@ static void tcg_out_qemu_ld_index(TCGContext *s, MemO= p opc, if (get_alignment_bits(opc) >=3D MO_64 && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend); - } else if (datalo !=3D addend) { + } else if (scratch_addend) { tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo); tcg_out_ld32_12(s, COND_AL, datahi, addend, 4); } else { @@ -1700,14 +1704,14 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is64) label_ptr =3D s->code_ptr; tcg_out_bl_imm(s, COND_NE, 0); =20 - tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend); + tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend, true); =20 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ if (guest_base) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); - tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, TCG_REG_TMP); + tcg_out_qemu_ld_index(s, opc, datalo, datahi, + addrlo, TCG_REG_GUEST_BASE, false); } else { tcg_out_qemu_ld_direct(s, opc, datalo, datahi, addrlo); } @@ -1716,7 +1720,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) =20 static void tcg_out_qemu_st_index(TCGContext *s, ARMCond cond, MemOp opc, TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addend) + TCGReg addrlo, TCGReg addend, + bool scratch_addend) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); @@ -1736,9 +1741,14 @@ static void tcg_out_qemu_st_index(TCGContext *s, ARM= Cond cond, MemOp opc, if (get_alignment_bits(opc) >=3D MO_64 && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_strd_r(s, cond, datalo, addrlo, addend); - } else { + } else if (scratch_addend) { tcg_out_st32_rwb(s, cond, datalo, addend, addrlo); tcg_out_st32_12(s, cond, datahi, addend, 4); + } else { + tcg_out_dat_reg(s, cond, ARITH_ADD, TCG_REG_TMP, + addend, addrlo, SHIFT_IMM_LSL(0)); + tcg_out_st32_12(s, cond, datalo, TCG_REG_TMP, 0); + tcg_out_st32_12(s, cond, datahi, TCG_REG_TMP, 4); } break; default: @@ -1801,7 +1811,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) mem_index =3D get_mmuidx(oi); addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0); =20 - tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend); + tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, + addrlo, addend, true); =20 /* The conditional call must come last, as we're going to return here.= */ label_ptr =3D s->code_ptr; @@ -1811,9 +1822,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ if (guest_base) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); - tcg_out_qemu_st_index(s, COND_AL, opc, datalo, - datahi, addrlo, TCG_REG_TMP); + tcg_out_qemu_st_index(s, COND_AL, opc, datalo, datahi, + addrlo, TCG_REG_GUEST_BASE, false); } else { tcg_out_qemu_st_direct(s, opc, datalo, datahi, addrlo); } @@ -2955,6 +2965,13 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); =20 +#ifndef CONFIG_SOFTMMU + if (guest_base) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); + } +#endif + tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); =20 /* --=20 2.25.1 From nobody Wed May 1 18:02:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1641628182; cv=none; d=zohomail.com; s=zohoarc; b=D/T254DkTbFY/75zJQ3mKxKSmZFmj71BWc3No8OYhmt2tKUrKwgCnaK0g/RHESBlopAM/mzkMl+iCaChNB0+LFwxRGB43DbvLnG9FIux2VC8VmhP6zyLw6Rqb7g1ohf3UIETmDuA8KM7iAsTa4uEzKQYFT/G1sQJZuzXNaK+tVc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1641628182; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mVWQbudPOl/uR8TYUS3zfMkysmPkX3RNf4TSFjZ3tBg=; b=gDWyIu7HzKoz6LSyQwAvPdfARU0EfpbjoYIB44CAFO2Dh2EJ1UWzf/b2LOn0hCE6Nz23GaMF/Nk/nOj9eUIB4SHIdzcq91ij1uPvUxQv57o+G10zS6W+KtL4KfCZdmGWBXcafycXiktPDzjG3caKehkLRk2z+v73Vi0u8Bb+zqc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641628182101128.45160059364719; Fri, 7 Jan 2022 23:49:42 -0800 (PST) Received: from localhost ([::1]:44116 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n66Tt-0008Sh-28 for importer@patchew.org; Sat, 08 Jan 2022 02:49:41 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57760) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n65IE-0001MF-PW for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:33:36 -0500 Received: from [2607:f8b0:4864:20::1031] (port=46666 helo=mail-pj1-x1031.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n65I9-0003dC-RF for qemu-devel@nongnu.org; Sat, 08 Jan 2022 01:33:31 -0500 Received: by mail-pj1-x1031.google.com with SMTP id rj2-20020a17090b3e8200b001b1944bad25so8916094pjb.5 for ; Fri, 07 Jan 2022 22:33:29 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id s7sm834760pfu.133.2022.01.07.22.33.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 22:33:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mVWQbudPOl/uR8TYUS3zfMkysmPkX3RNf4TSFjZ3tBg=; b=iyphgsqxYs01DBAEg6Ngp0VYmLKlgCkTd9dX14k40zGsCL4hU+D/Hw2lLDR0udXCE7 qHqET75hcHqo764JVB2xEmz0i6xm6B5MvixxFGYnLF6khTbmZh6j90E26bQUOy4LlasQ tRYsJL1USXc9ChFOOF3WPvXFEw4EyddTInT3GVFJlz5VG24bWFLbEs3eNATkHJuwwsCh uo+MoNBSrSHYPxHY3yZJWWnaOwdf+ihe3OdY2ElYEoKsABBK3Extv2dJszgK1vZrWEKI FQJl9mkjS9hiro3l85jk81sFPEjHCrUG7FCuAGtbt+J+sigxBWYXnDR1jrMH96rx5wca S5eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mVWQbudPOl/uR8TYUS3zfMkysmPkX3RNf4TSFjZ3tBg=; b=PV0dfA1Wy529ZQjEPerZchwJ5UyATQza0DKzNXp/IZN5RitWyiWar7z+L2cenOXcGQ uec/BTWVKdp3mlPMTtLxSFPBg1TrBb+EoDmpcNkFvY0uYT0FKbjMZ84y5T/5DevksRtV xEWi5ptrptFbnU3piwhWZUI71LM0GGY7YgYKcrwEC4urdH/rKsaVWIgmfd3wpHKfNdRE APWadC6X/tpannnmgtlN/1lcIWEG4AxzpRrbmjM704SOzxWfoz5YIuG6w7bAbVFawa68 /qXsoRxu1pqQauKaArf9RFhskGcgINmYuu3wYgzfewffkjBJCtvsJ1QL1TSBW/ZmHNzb Wp1g== X-Gm-Message-State: AOAM532YGN89He5A4eV+mbGM1iuBYzNSBb7UBgNxZyqCOQ0kuoD62820 h9Op3s3DTRqJDahOF/neU50MwZOeMR5rsQ== X-Google-Smtp-Source: ABdhPJyFD9xi5hPg8mYwDAs67hgeYzXcmaT5Dn+X+kpFeKCkjuR9MShVs+fvLmBkeExOkVG1iSkMow== X-Received: by 2002:a17:902:7c15:b0:148:fddf:d828 with SMTP id x21-20020a1709027c1500b00148fddfd828mr24569119pll.2.1641623608606; Fri, 07 Jan 2022 22:33:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 7/7] tcg/arm: Support raising sigbus for user-only Date: Fri, 7 Jan 2022 22:33:13 -0800 Message-Id: <20220108063313.477784-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220108063313.477784-1-richard.henderson@linaro.org> References: <20220108063313.477784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1031 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1641628184029100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.h | 2 - tcg/arm/tcg-target.c.inc | 83 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 81 insertions(+), 4 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 1dd4cd5377..27c27a1f14 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -151,9 +151,7 @@ extern bool use_neon_instructions; /* not defined -- call should be eliminated at compile time */ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS =20 #endif diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 1c00311877..1e336a0eea 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -23,6 +23,7 @@ */ =20 #include "elf.h" +#include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" =20 int arm_arch =3D __ARM_ARCH; @@ -1289,8 +1290,6 @@ static void tcg_out_vldst(TCGContext *s, ARMInsn insn, } =20 #ifdef CONFIG_SOFTMMU -#include "../tcg-ldst.c.inc" - /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ @@ -1589,6 +1588,74 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); return true; } +#else + +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, + TCGReg addrhi, unsigned a_bits) +{ + unsigned a_mask =3D (1 << a_bits) - 1; + TCGLabelQemuLdst *label =3D new_ldst_label(s); + + label->is_ld =3D is_ld; + label->addrlo_reg =3D addrlo; + label->addrhi_reg =3D addrhi; + + /* We are expecting a_bits to max out at 7, and can easily support 8. = */ + tcg_debug_assert(a_mask <=3D 0xff); + /* tst addr, #mask */ + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); + + /* blne slow_path */ + label->label_ptr[0] =3D s->code_ptr; + tcg_out_bl_imm(s, COND_NE, 0); + + label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + if (!reloc_pc24(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { + return false; + } + + if (TARGET_LONG_BITS =3D=3D 64) { + /* 64-bit target address is aligned into R2:R3. */ + if (l->addrhi_reg !=3D TCG_REG_R2) { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, l->addrhi_reg); + } else if (l->addrlo_reg !=3D TCG_REG_R3) { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, l->addrhi_reg); + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, l->addrlo_reg); + } else { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, TCG_REG_R2); + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, TCG_REG_R3); + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, TCG_REG_R1); + } + } else { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, l->addrlo_reg); + } + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_AREG0); + + /* + * Tail call to the helper, with the return address back inline, + * just for the clarity of the debugging traceback -- the helper + * cannot return. We have used BLNE to arrive here, so LR is + * already set. + */ + tcg_out_goto(s, COND_AL, (const void *) + (l->is_ld ? helper_unaligned_ld : helper_unaligned_st)); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} #endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, @@ -1686,6 +1753,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) int mem_index; TCGReg addend; tcg_insn_unit *label_ptr; +#else + unsigned a_bits; #endif =20 datalo =3D *args++; @@ -1709,6 +1778,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is64) add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ + a_bits =3D get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); + } if (guest_base) { tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, TCG_REG_GUEST_BASE, false); @@ -1798,6 +1871,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) int mem_index; TCGReg addend; tcg_insn_unit *label_ptr; +#else + unsigned a_bits; #endif =20 datalo =3D *args++; @@ -1821,6 +1896,10 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is64) add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ + a_bits =3D get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); + } if (guest_base) { tcg_out_qemu_st_index(s, COND_AL, opc, datalo, datahi, addrlo, TCG_REG_GUEST_BASE, false); --=20 2.25.1