From nobody Mon Apr 29 17:32:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641548100571565.6474826001659; Fri, 7 Jan 2022 01:35:00 -0800 (PST) Received: from localhost ([::1]:54982 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5leF-00084D-59 for importer@patchew.org; Fri, 07 Jan 2022 04:34:59 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53320) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5lbM-0005x2-Sy for qemu-devel@nongnu.org; Fri, 07 Jan 2022 04:32:02 -0500 Received: from mga05.intel.com ([192.55.52.43]:22251) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5lbK-00077l-SZ for qemu-devel@nongnu.org; Fri, 07 Jan 2022 04:32:00 -0500 Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2022 01:31:44 -0800 Received: from 984fee00bf64.jf.intel.com ([10.165.54.77]) by fmsmga007.fm.intel.com with ESMTP; 07 Jan 2022 01:31:42 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1641547918; x=1673083918; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PnButU9Q6Pc0MQ22Fe1AaP0ULZ2IvO0f1IXWwo02ztk=; b=OOC4/zTcAxwX64wmkjWoAq98cm+lVXYqDgL6LrqAQGaQu51kT8vLc4Y9 GDe5QQBzXBgcdIYCJD82tdB4QZ7z8iuEa59EHKf+J3AkPH6GJzjk1aGEi 15lUHaaQCBCBWO4a+tT2bbZskmKBwbO7bEd8PFTELjyjXufWDsXPrnE/H DDeRTXbWWTqAregiOI8BAGMatWQSGxxvYgvgvRwzuQi4D/zPydY3QNiyk UDL2A/48a6XEyWbmOF7fHdAe6J1MG1DHMPXsZcBwUbm91TWZ5WYP/AMXh cMsFZ5KDGErE6uO164/strk1pZtn++j6kXJRLtlE//zAkdE/J+Jimvi6X Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10219"; a="329184201" X-IronPort-AV: E=Sophos;i="5.88,269,1635231600"; d="scan'208";a="329184201" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,269,1635231600"; d="scan'208";a="527239099" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [RFC PATCH 1/7] x86: Fix the 64-byte boundary enumeration for extended state Date: Fri, 7 Jan 2022 01:31:28 -0800 Message-Id: <20220107093134.136441-2-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220107093134.136441-1-yang.zhong@intel.com> References: <20220107093134.136441-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.43; envelope-from=yang.zhong@intel.com; helo=mga05.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.372, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641548102043100001 Content-Type: text/plain; charset="utf-8" From: Jing Liu The extended state subleaves (EAX=3D0Dh, ECX=3Dn, n>1).ECX[1] are all zero, while spec actually introduces that bit 01 should indicate if the extended state component locates on the next 64-byte boundary following the preceding state component when the compacted format of an XSAVE area is used. Fix the subleaves value according to the host supported cpuid. The upcoming AMX feature would be the first one using it. Signed-off-by: Jing Liu Signed-off-by: Yang Zhong --- target/i386/cpu.h | 1 + target/i386/cpu.c | 1 + target/i386/kvm/kvm-cpu.c | 3 +++ 3 files changed, 5 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 04f2b790c9..7f9700544f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1354,6 +1354,7 @@ QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) !=3D 0x8); typedef struct ExtSaveArea { uint32_t feature, bits; uint32_t offset, size; + uint32_t need_align; } ExtSaveArea; =20 #define XSAVE_STATE_AREA_COUNT (XSTATE_PKRU_BIT + 1) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index aa9e636800..47bc4d5c1a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5487,6 +5487,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, const ExtSaveArea *esa =3D &x86_ext_save_areas[count]; *eax =3D esa->size; *ebx =3D esa->offset; + *ecx =3D esa->need_align << 1; } } break; diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index d95028018e..6c4c1c6f9d 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -105,6 +105,9 @@ static void kvm_cpu_xsave_init(void) assert(esa->size =3D=3D sz); esa->offset =3D kvm_arch_get_supported_cpuid(s, 0xd, i, R_= EBX); } + + uint32_t ecx =3D kvm_arch_get_supported_cpuid(s, 0xd, i, R_ECX= ); + esa->need_align =3D ecx & (1u << 1) ? 1 : 0; } } } From nobody Mon Apr 29 17:32:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641548430043128.56885222100846; Fri, 7 Jan 2022 01:40:30 -0800 (PST) Received: from localhost ([::1]:38936 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5ljY-0007vw-Bm for importer@patchew.org; Fri, 07 Jan 2022 04:40:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53370) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5lbQ-0005y7-Bp for qemu-devel@nongnu.org; Fri, 07 Jan 2022 04:32:05 -0500 Received: from mga05.intel.com ([192.55.52.43]:22251) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5lbN-00077l-0H for qemu-devel@nongnu.org; Fri, 07 Jan 2022 04:32:03 -0500 Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2022 01:31:44 -0800 Received: from 984fee00bf64.jf.intel.com ([10.165.54.77]) by fmsmga007.fm.intel.com with ESMTP; 07 Jan 2022 01:31:42 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1641547921; x=1673083921; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ws/VgoWNa3UOYS/0yITKgvzTtuOkLiQPfrBN2aWTLhg=; b=Rgl0EMNEktRktQLpiJc49zdkdXGR+Ys7W069U2uwOIupk8lzATXmYNN8 nRReaqxC4kujZhVJ7V2gACm/xFOG132W2ZB5s6tAWvw6tz5ZfKqXl4PG9 /VtSbkzw/OACC67DpNRgMO2KngN+kcurvFmxLIXr6EY1uPVXxB1F+2GB6 vriNoa0GWtdDkmPfemlDcCYhvK9yq80LVEDV7vjLg8SId+fglDDOVn8/W GzBQ86NrwaXwohY8ws1CydBoZZadUK8NwQjcPU4QPe62kqtTHtRE1633J X1a2XefTMITFWmEXENLf8gZLaJx0JDHmkz2oPpjwkrfhWnJCOH0EFT47R g==; X-IronPort-AV: E=McAfee;i="6200,9189,10219"; a="329184203" X-IronPort-AV: E=Sophos;i="5.88,269,1635231600"; d="scan'208";a="329184203" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,269,1635231600"; d="scan'208";a="527239102" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [RFC PATCH 2/7] x86: Add AMX XTILECFG and XTILEDATA components Date: Fri, 7 Jan 2022 01:31:29 -0800 Message-Id: <20220107093134.136441-3-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220107093134.136441-1-yang.zhong@intel.com> References: <20220107093134.136441-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.43; envelope-from=yang.zhong@intel.com; helo=mga05.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.372, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641548432415100001 Content-Type: text/plain; charset="utf-8" From: Jing Liu AMX XTILECFG and XTILEDATA are managed by XSAVE feature set. State component 17 is used for 64-byte TILECFG register (XTILECFG state) and component 18 is used for 8192 bytes of tile data (XTILEDATA state). Add AMX feature bits to x86_ext_save_areas array to set up AMX components. Add structs that define the layout of AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the structs sizes. Signed-off-by: Jing Liu Signed-off-by: Yang Zhong --- target/i386/cpu.h | 16 +++++++++++++++- target/i386/cpu.c | 8 ++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7f9700544f..768a8218be 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -537,6 +537,8 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_BIT 6 #define XSTATE_Hi16_ZMM_BIT 7 #define XSTATE_PKRU_BIT 9 +#define XSTATE_XTILE_CFG_BIT 17 +#define XSTATE_XTILE_DATA_BIT 18 =20 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) @@ -1343,6 +1345,16 @@ typedef struct XSavePKRU { uint32_t padding; } XSavePKRU; =20 +/* Ext. save area 17: AMX XTILECFG state */ +typedef struct XSaveXTILE_CFG { + uint8_t xtilecfg[64]; +} XSaveXTILE_CFG; + +/* Ext. save area 18: AMX XTILEDATA state */ +typedef struct XSaveXTILE_DATA { + uint8_t xtiledata[8][1024]; +} XSaveXTILE_DATA; + QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) !=3D 0x100); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) !=3D 0x40); @@ -1350,6 +1362,8 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) !=3D 0x200); QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) !=3D 0x400); QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) !=3D 0x8); +QEMU_BUILD_BUG_ON(sizeof(XSaveXTILE_CFG) !=3D 0x40); +QEMU_BUILD_BUG_ON(sizeof(XSaveXTILE_DATA) !=3D 0x2000); =20 typedef struct ExtSaveArea { uint32_t feature, bits; @@ -1357,7 +1371,7 @@ typedef struct ExtSaveArea { uint32_t need_align; } ExtSaveArea; =20 -#define XSAVE_STATE_AREA_COUNT (XSTATE_PKRU_BIT + 1) +#define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1) =20 extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT]; =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 47bc4d5c1a..dd2c919c33 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1401,6 +1401,14 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUN= T] =3D { [XSTATE_PKRU_BIT] =3D { .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_PKU, .size =3D sizeof(XSavePKRU) }, + [XSTATE_XTILE_CFG_BIT] =3D { + .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_AMX_TILE, + .size =3D sizeof(XSaveXTILE_CFG), + }, + [XSTATE_XTILE_DATA_BIT] =3D { + .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_AMX_TILE, + .size =3D sizeof(XSaveXTILE_DATA), + }, }; =20 static uint32_t xsave_area_size(uint64_t mask) From nobody Mon Apr 29 17:32:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641548253013712.9172693752218; Fri, 7 Jan 2022 01:37:33 -0800 (PST) Received: from localhost ([::1]:33236 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5lgh-00043p-M9 for importer@patchew.org; Fri, 07 Jan 2022 04:37:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53366) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5lbQ-0005y5-BN for qemu-devel@nongnu.org; Fri, 07 Jan 2022 04:32:05 -0500 Received: from mga05.intel.com ([192.55.52.43]:22256) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5lbI-00077r-10 for qemu-devel@nongnu.org; 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d="scan'208";a="329184200" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,269,1635231600"; d="scan'208";a="527239103" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [RFC PATCH 3/7] x86: Grant AMX permission for guest Date: Fri, 7 Jan 2022 01:31:30 -0800 Message-Id: <20220107093134.136441-4-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220107093134.136441-1-yang.zhong@intel.com> References: <20220107093134.136441-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.43; envelope-from=yang.zhong@intel.com; helo=mga05.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.372, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641548254681100001 Content-Type: text/plain; charset="utf-8" Kernel mechanism for dynamically enabled XSAVE features asks userspace VMM requesting guest permission if it wants to expose the features. Only with the permission, kernel can try to enable the features when detecting the intention from guest in runtime. Qemu should request the permission for guest only once before the first vCPU is created. KVM checks the guest permission when Qemu advertises the features, and the advertising operation fails w/o permission. Signed-off-by: Yang Zhong Signed-off-by: Jing Liu --- target/i386/cpu.h | 7 +++++++ hw/i386/x86.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 768a8218be..79023fe723 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -549,6 +549,13 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) +#define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT) +#define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT) +#define XFEATURE_XTILE_MASK (XSTATE_XTILE_CFG_MASK \ + | XSTATE_XTILE_DATA_MASK) + +#define ARCH_GET_XCOMP_GUEST_PERM 0x1024 +#define ARCH_REQ_XCOMP_GUEST_PERM 0x1025 =20 /* CPUID feature words */ typedef enum FeatureWord { diff --git a/hw/i386/x86.c b/hw/i386/x86.c index b84840a1bb..0a204c375e 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -41,6 +41,8 @@ #include "sysemu/cpu-timers.h" #include "trace.h" =20 +#include + #include "hw/i386/x86.h" #include "target/i386/cpu.h" #include "hw/i386/topology.h" @@ -117,6 +119,30 @@ out: object_unref(cpu); } =20 +static void x86_xsave_req_perm(void) +{ + unsigned long bitmask; + + long rc =3D syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, + XSTATE_XTILE_DATA_BIT); + if (rc) { + /* + * The older kernel version(<5.15) can't support + * ARCH_REQ_XCOMP_GUEST_PERM and directly return. + */ + return; + } + + rc =3D syscall(SYS_arch_prctl, ARCH_GET_XCOMP_GUEST_PERM, &bitmask); + if (rc) { + error_report("prctl(ARCH_GET_XCOMP_GUEST_PERM) error: %ld", rc); + } else if (!(bitmask & XFEATURE_XTILE_MASK)) { + error_report("prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure " + "and bitmask=3D0x%lx", bitmask); + exit(EXIT_FAILURE); + } +} + void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version) { int i; @@ -124,6 +150,8 @@ void x86_cpus_init(X86MachineState *x86ms, int default_= cpu_version) MachineState *ms =3D MACHINE(x86ms); MachineClass *mc =3D MACHINE_GET_CLASS(x86ms); =20 + /* Request AMX pemission for guest */ + x86_xsave_req_perm(); x86_cpu_set_default_version(default_cpu_version); =20 /* From nobody Mon Apr 29 17:32:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641548257719464.5460891575816; Fri, 7 Jan 2022 01:37:37 -0800 (PST) Received: from localhost ([::1]:33332 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5lgm-00047Y-HD for importer@patchew.org; Fri, 07 Jan 2022 04:37:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53484) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5lbj-0006PX-2l for qemu-devel@nongnu.org; Fri, 07 Jan 2022 04:32:23 -0500 Received: from mga05.intel.com ([192.55.52.43]:22256) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5lbS-00077r-6X for qemu-devel@nongnu.org; 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d="scan'208";a="329184202" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,269,1635231600"; d="scan'208";a="527239107" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [RFC PATCH 4/7] x86: Add XFD faulting bit for state components Date: Fri, 7 Jan 2022 01:31:31 -0800 Message-Id: <20220107093134.136441-5-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220107093134.136441-1-yang.zhong@intel.com> References: <20220107093134.136441-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.43; envelope-from=yang.zhong@intel.com; helo=mga05.intel.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.372, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641548258686100001 Content-Type: text/plain; charset="utf-8" From: Jing Liu Intel introduces XFD faulting mechanism for extended XSAVE features to dynamically enable the features in runtime. If CPUID (EAX=3D0Dh, ECX=3Dn, n>1).ECX[2] is set as 1, it indicates support for XFD faulting of this state component. Signed-off-by: Jing Liu Signed-off-by: Yang Zhong --- target/i386/cpu.h | 2 +- target/i386/cpu.c | 2 +- target/i386/kvm/kvm-cpu.c | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 79023fe723..22f7ff40a6 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1375,7 +1375,7 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveXTILE_DATA) !=3D 0x2000= ); typedef struct ExtSaveArea { uint32_t feature, bits; uint32_t offset, size; - uint32_t need_align; + uint32_t need_align, support_xfd; } ExtSaveArea; =20 #define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index dd2c919c33..1adc3f0f99 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5495,7 +5495,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, const ExtSaveArea *esa =3D &x86_ext_save_areas[count]; *eax =3D esa->size; *ebx =3D esa->offset; - *ecx =3D esa->need_align << 1; + *ecx =3D (esa->need_align << 1) | (esa->support_xfd << 2); } } break; diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index 6c4c1c6f9d..3b3c203f11 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -108,6 +108,7 @@ static void kvm_cpu_xsave_init(void) =20 uint32_t ecx =3D kvm_arch_get_supported_cpuid(s, 0xd, i, R_ECX= ); esa->need_align =3D ecx & (1u << 1) ? 1 : 0; + esa->support_xfd =3D ecx & (1u << 2) ? 1 : 0; } } } From nobody Mon Apr 29 17:32:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641548103002936.0625382876048; Fri, 7 Jan 2022 01:35:03 -0800 (PST) Received: from localhost ([::1]:55104 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5leH-00089c-TC for importer@patchew.org; Fri, 07 Jan 2022 04:35:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53358) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5lbO-0005xv-Sf for qemu-devel@nongnu.org; Fri, 07 Jan 2022 04:32:02 -0500 Received: from mga05.intel.com ([192.55.52.43]:22268) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5lbL-00078O-Nb for qemu-devel@nongnu.org; Fri, 07 Jan 2022 04:32:01 -0500 Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2022 01:31:44 -0800 Received: from 984fee00bf64.jf.intel.com ([10.165.54.77]) by fmsmga007.fm.intel.com with ESMTP; 07 Jan 2022 01:31:43 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1641547919; x=1673083919; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bjEbZOqNPQg+4twx2D0e5cvrOJH4PkiI9d217mb5H/A=; b=AAVDg3rD73EYFp/lkUNtb7sjW/GMHVfaQuv+OX3EATanZDdK39dZCmOR xULRzV4kEW3Rf0K4DV2ZzWbZp8A9jWPjRdV82YjuWfzH7iJ0s8t+QhyLO whqbaC8mhIgZAy7VI+xHiFd9S6vI0nugbrZ/9wEVW3CEIJ+a6qqowj5B3 MHfmLAli7JY7PSHr+4nXK9P6Aua4v0odzgCYeQLCyHZbE6+BY7j4fUWlN yrV/CbYjvCiB4WGzBUqLzMxXGnr448xpYFA6jFvDzn8l/CLHxtRjEi/ht clvjyuzaaT5WvYFBU59ojzHkq0gLm6+C1BKQ9+KYMvSlXYWh93sRB5+ce A==; X-IronPort-AV: E=McAfee;i="6200,9189,10219"; a="329184204" X-IronPort-AV: E=Sophos;i="5.88,269,1635231600"; d="scan'208";a="329184204" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,269,1635231600"; d="scan'208";a="527239111" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [RFC PATCH 5/7] x86: Add AMX CPUIDs enumeration Date: Fri, 7 Jan 2022 01:31:32 -0800 Message-Id: <20220107093134.136441-6-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220107093134.136441-1-yang.zhong@intel.com> References: <20220107093134.136441-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.43; envelope-from=yang.zhong@intel.com; helo=mga05.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.372, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641548103670100003 Content-Type: text/plain; charset="utf-8" From: Jing Liu Add AMX primary feature bits XFD and AMX_TILE to enumerate the CPU's AMX capability. Meanwhile, add AMX TILE and TMUL CPUID leaf and subleaves which exist when AMX TILE is present to provide the maximum capability of TILE and TMUL. Signed-off-by: Jing Liu Signed-off-by: Yang Zhong --- target/i386/cpu.h | 2 ++ target/i386/cpu.c | 55 ++++++++++++++++++++++++++++++++++++++++--- target/i386/kvm/kvm.c | 3 ++- 3 files changed, 56 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 22f7ff40a6..245e8b5a1a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -849,6 +849,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) /* AVX512_FP16 instruction */ #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) +/* AMX tile (two-dimensional register)*/ +#define CPUID_7_0_EDX_AMX_TILE (1U << 24) /* Speculation Control */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Single Thread Indirect Branch Predictors */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1adc3f0f99..025e35471f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -574,6 +574,18 @@ static CPUCacheInfo legacy_l3_cache =3D { #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32= K,64K */ =20 +/* CPUID Leaf 0x1D constants: */ +#define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 +#define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 +#define INTEL_AMX_BYTES_PER_TILE 0x400 +#define INTEL_AMX_BYTES_PER_ROW 0x40 +#define INTEL_AMX_TILE_MAX_NAMES 0x8 +#define INTEL_AMX_TILE_MAX_ROWS 0x10 + +/* CPUID Leaf 0x1E constants: */ +#define INTEL_AMX_TMUL_MAX_K 0x10 +#define INTEL_AMX_TMUL_MAX_N 0x40 + void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, uint32_t vendor2, uint32_t vendor3) { @@ -843,8 +855,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "avx512-vp2intersect", NULL, "md-clear", NULL, NULL, NULL, "serialize", NULL, "tsx-ldtrk", NULL, NULL /* pconfig */, NULL, - NULL, NULL, NULL, "avx512-fp16", - NULL, NULL, "spec-ctrl", "stibp", + NULL, NULL, "amx-bf16", "avx512-fp16", + "amx-tile", "amx-int8", "spec-ctrl", "stibp", NULL, "arch-capabilities", "core-capability", "ssbd", }, .cpuid =3D { @@ -909,7 +921,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "xsaveopt", "xsavec", "xgetbv1", "xsaves", - NULL, NULL, NULL, NULL, + "xfd", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -5584,6 +5596,43 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } break; } + case 0x1D: { + /* AMX TILE */ + *eax =3D 0; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; + if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { + break; + } + + if (count =3D=3D 0) { + /* Highest numbered palette subleaf */ + *eax =3D INTEL_AMX_TILE_MAX_SUBLEAF; + } else if (count =3D=3D 1) { + *eax =3D INTEL_AMX_TOTAL_TILE_BYTES | + (INTEL_AMX_BYTES_PER_TILE << 16); + *ebx =3D INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES <= < 16); + *ecx =3D INTEL_AMX_TILE_MAX_ROWS; + } + break; + } + case 0x1E: { + /* AMX TMUL */ + *eax =3D 0; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; + if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { + break; + } + + if (count =3D=3D 0) { + /* Highest numbered palette subleaf */ + *ebx =3D INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); + } + break; + } case 0x40000000: /* * CPUID code in kvm_arch_init_vcpu() ignores stuff diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 13f8e30c2a..3fb3ddbe2b 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1758,7 +1758,8 @@ int kvm_arch_init_vcpu(CPUState *cs) c =3D &cpuid_data.entries[cpuid_i++]; } break; - case 0x14: { + case 0x14: + case 0x1d: { uint32_t times; =20 c->function =3D i; From nobody Mon Apr 29 17:32:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641548459050818.9124703706595; Fri, 7 Jan 2022 01:40:59 -0800 (PST) Received: from localhost ([::1]:39770 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5lk0-0008U9-6t for importer@patchew.org; Fri, 07 Jan 2022 04:40:56 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53482) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5lbj-0006PS-1s for qemu-devel@nongnu.org; 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X-IronPort-AV: E=McAfee;i="6200,9189,10219"; a="329184205" X-IronPort-AV: E=Sophos;i="5.88,269,1635231600"; d="scan'208";a="329184205" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,269,1635231600"; d="scan'208";a="527239119" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [RFC PATCH 6/7] x86: Use new XSAVE ioctls handling Date: Fri, 7 Jan 2022 01:31:33 -0800 Message-Id: <20220107093134.136441-7-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220107093134.136441-1-yang.zhong@intel.com> References: <20220107093134.136441-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.43; envelope-from=yang.zhong@intel.com; helo=mga05.intel.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.372, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641548460590100001 Content-Type: text/plain; charset="utf-8" From: Jing Liu Extended feature has large state while current kvm_xsave only allows 4KB. Use new XSAVE ioctls if the xstate size is large than kvm_xsave. Signed-off-by: Jing Liu Signed-off-by: Zeng Guang Signed-off-by: Wei Wang Signed-off-by: Yang Zhong --- linux-headers/asm-x86/kvm.h | 14 ++++++++++++++ linux-headers/linux/kvm.h | 2 ++ target/i386/cpu.h | 5 +++++ target/i386/kvm/kvm.c | 16 ++++++++++++++-- target/i386/xsave_helper.c | 35 +++++++++++++++++++++++++++++++++++ 5 files changed, 70 insertions(+), 2 deletions(-) diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h index 5a776a08f7..32f2a921e8 100644 --- a/linux-headers/asm-x86/kvm.h +++ b/linux-headers/asm-x86/kvm.h @@ -376,6 +376,20 @@ struct kvm_debugregs { /* for KVM_CAP_XSAVE */ struct kvm_xsave { __u32 region[1024]; + /* + * KVM_GET_XSAVE2 and KVM_SET_XSAVE write and read as many bytes + * as are returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2) + * respectively, when invoked on the vm file descriptor. + * + * The size value returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2) + * will always be at least 4096. Currently, it is only greater + * than 4096 if a dynamic feature has been enabled with + * ``arch_prctl()``, but this may change in the future. + * + * The offsets of the state save areas in struct kvm_xsave follow + * the contents of CPUID leaf 0xD on the host. + */ + __u32 extra[0]; }; =20 #define KVM_MAX_XCRS 16 diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 02c5e7b7bb..97d5b6d81d 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1130,6 +1130,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_BINARY_STATS_FD 203 #define KVM_CAP_EXIT_ON_EMULATION_FAILURE 204 #define KVM_CAP_ARM_MTE 205 +#define KVM_CAP_XSAVE2 207 =20 #ifdef KVM_CAP_IRQ_ROUTING =20 @@ -1550,6 +1551,7 @@ struct kvm_s390_ucas_mapping { /* Available with KVM_CAP_XSAVE */ #define KVM_GET_XSAVE _IOR(KVMIO, 0xa4, struct kvm_xsave) #define KVM_SET_XSAVE _IOW(KVMIO, 0xa5, struct kvm_xsave) +#define KVM_GET_XSAVE2 _IOR(KVMIO, 0xcf, struct kvm_xsave) /* Available with KVM_CAP_XCRS */ #define KVM_GET_XCRS _IOR(KVMIO, 0xa6, struct kvm_xcrs) #define KVM_SET_XCRS _IOW(KVMIO, 0xa7, struct kvm_xcrs) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 245e8b5a1a..6153c4ab1a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1519,6 +1519,11 @@ typedef struct CPUX86State { YMMReg zmmh_regs[CPU_NB_REGS]; ZMMReg hi16_zmm_regs[CPU_NB_REGS]; =20 +#ifdef TARGET_X86_64 + uint8_t xtilecfg[64]; + uint8_t xtiledata[8192]; +#endif + /* sysenter registers */ uint32_t sysenter_cs; target_ulong sysenter_esp; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 3fb3ddbe2b..97520e9dff 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1983,7 +1983,12 @@ int kvm_arch_init_vcpu(CPUState *cs) } =20 if (has_xsave) { - env->xsave_buf_len =3D sizeof(struct kvm_xsave); + uint32_t size =3D kvm_vm_check_extension(cs->kvm_state, KVM_CAP_XS= AVE2); + if (!size) { + size =3D sizeof(struct kvm_xsave); + } + + env->xsave_buf_len =3D QEMU_ALIGN_UP(size, 4096); env->xsave_buf =3D qemu_memalign(4096, env->xsave_buf_len); memset(env->xsave_buf, 0, env->xsave_buf_len); =20 @@ -2580,6 +2585,7 @@ static int kvm_put_xsave(X86CPU *cpu) if (!has_xsave) { return kvm_put_fpu(cpu); } + x86_cpu_xsave_all_areas(cpu, xsave, env->xsave_buf_len); =20 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave); @@ -3247,10 +3253,16 @@ static int kvm_get_xsave(X86CPU *cpu) return kvm_get_fpu(cpu); } =20 - ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave); + if (env->xsave_buf_len <=3D sizeof(struct kvm_xsave)) { + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave); + } else { + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE2, xsave); + } + if (ret < 0) { return ret; } + x86_cpu_xrstor_all_areas(cpu, xsave, env->xsave_buf_len); =20 return 0; diff --git a/target/i386/xsave_helper.c b/target/i386/xsave_helper.c index ac61a96344..090424e820 100644 --- a/target/i386/xsave_helper.c +++ b/target/i386/xsave_helper.c @@ -5,6 +5,7 @@ #include "qemu/osdep.h" =20 #include "cpu.h" +#include =20 void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen) { @@ -126,6 +127,23 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, u= int32_t buflen) =20 memcpy(pkru, &env->pkru, sizeof(env->pkru)); } + + e =3D &x86_ext_save_areas[XSTATE_XTILE_CFG_BIT]; + if (e->size && e->offset) { + XSaveXTILE_CFG *tilecfg =3D buf + e->offset; + + memcpy(tilecfg, &env->xtilecfg, sizeof(env->xtilecfg)); + } + + if (buflen > sizeof(struct kvm_xsave)) { + e =3D &x86_ext_save_areas[XSTATE_XTILE_DATA_BIT]; + + if (e->size && e->offset) { + XSaveXTILE_DATA *tiledata =3D buf + e->offset; + + memcpy(tiledata, &env->xtiledata, sizeof(env->xtiledata)); + } + } #endif } =20 @@ -247,5 +265,22 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void = *buf, uint32_t buflen) pkru =3D buf + e->offset; memcpy(&env->pkru, pkru, sizeof(env->pkru)); } + + e =3D &x86_ext_save_areas[XSTATE_XTILE_CFG_BIT]; + if (e->size && e->offset) { + const XSaveXTILE_CFG *tilecfg =3D buf + e->offset; + + memcpy(&env->xtilecfg, tilecfg, sizeof(env->xtilecfg)); + } + + if (buflen > sizeof(struct kvm_xsave)) { + e =3D &x86_ext_save_areas[XSTATE_XTILE_DATA_BIT]; + + if (e->size && e->offset) { + const XSaveXTILE_DATA *tiledata =3D buf + e->offset; + + memcpy(&env->xtiledata, tiledata, sizeof(env->xtiledata)); + } + } #endif } From nobody Mon Apr 29 17:32:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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d="scan'208";a="329184206" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,269,1635231600"; d="scan'208";a="527239126" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [RFC PATCH 7/7] x86: Support XFD and AMX xsave data migration Date: Fri, 7 Jan 2022 01:31:34 -0800 Message-Id: <20220107093134.136441-8-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220107093134.136441-1-yang.zhong@intel.com> References: <20220107093134.136441-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.43; envelope-from=yang.zhong@intel.com; helo=mga05.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.372, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641548657228100001 Content-Type: text/plain; charset="utf-8" From: Zeng Guang XFD(eXtended Feature Disable) allows to enable a feature on xsave state while preventing specific user threads from using the feature. Support save and restore XFD MSRs if CPUID.D.1.EAX[4] enumerate to be valid. Likewise migrate the MSRs and related xsave state necessarily. Signed-off-by: Zeng Guang Signed-off-by: Wei Wang Signed-off-by: Yang Zhong --- target/i386/cpu.h | 9 +++++++++ target/i386/kvm/kvm.c | 18 ++++++++++++++++++ target/i386/machine.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 69 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6153c4ab1a..1627988790 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -505,6 +505,9 @@ typedef enum X86Seg { =20 #define MSR_VM_HSAVE_PA 0xc0010117 =20 +#define MSR_IA32_XFD 0x000001c4 +#define MSR_IA32_XFD_ERR 0x000001c5 + #define MSR_IA32_BNDCFGS 0x00000d90 #define MSR_IA32_XSS 0x00000da0 #define MSR_IA32_UMWAIT_CONTROL 0xe1 @@ -866,6 +869,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) /* AVX512 BFloat16 Instruction */ #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) +/* XFD Extend Feature Disabled */ +#define CPUID_D_1_EAX_XFD (1U << 4) =20 /* Packets which contain IP payload have LIP values */ #define CPUID_14_0_ECX_LIP (1U << 31) @@ -1608,6 +1613,10 @@ typedef struct CPUX86State { uint64_t msr_rtit_cr3_match; uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; =20 + /* Per-VCPU XFD MSRs */ + uint64_t msr_xfd; + uint64_t msr_xfd_err; + /* exception/interrupt handling */ int error_code; int exception_is_int; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 97520e9dff..02d5cf1063 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -3192,6 +3192,13 @@ static int kvm_put_msrs(X86CPU *cpu, int level) env->msr_ia32_sgxlepubkeyhash[3]); } =20 + if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) { + kvm_msr_entry_add(cpu, MSR_IA32_XFD, + env->msr_xfd); + kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, + env->msr_xfd_err); + } + /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see * kvm_put_msr_feature_control. */ } @@ -3548,6 +3555,11 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0); } =20 + if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) { + kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0); + kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0); + } + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); if (ret < 0) { return ret; @@ -3844,6 +3856,12 @@ static int kvm_get_msrs(X86CPU *cpu) env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH= 0] =3D msrs[i].data; break; + case MSR_IA32_XFD: + env->msr_xfd =3D msrs[i].data; + break; + case MSR_IA32_XFD_ERR: + env->msr_xfd_err =3D msrs[i].data; + break; } } =20 diff --git a/target/i386/machine.c b/target/i386/machine.c index 83c2b91529..fdeb5bab50 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1455,6 +1455,46 @@ static const VMStateDescription vmstate_msr_intel_sg= x =3D { } }; =20 +static bool xfd_msrs_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return !!(env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD); +} + +static const VMStateDescription vmstate_msr_xfd =3D { + .name =3D "cpu/msr_xfd", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D xfd_msrs_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.msr_xfd, X86CPU), + VMSTATE_UINT64(env.msr_xfd_err, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool amx_xtile_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return !!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE); +} + +static const VMStateDescription vmstate_amx_xtile =3D { + .name =3D "cpu/intel_amx_xtile", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D amx_xtile_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8_ARRAY(env.xtilecfg, X86CPU, 64), + VMSTATE_UINT8_ARRAY(env.xtiledata, X86CPU, 8192), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_x86_cpu =3D { .name =3D "cpu", .version_id =3D 12, @@ -1593,6 +1633,8 @@ const VMStateDescription vmstate_x86_cpu =3D { #endif &vmstate_msr_tsx_ctrl, &vmstate_msr_intel_sgx, + &vmstate_msr_xfd, + &vmstate_amx_xtile, NULL } };