From nobody Mon Apr 29 19:45:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641522352597600.3166212956156; Thu, 6 Jan 2022 18:25:52 -0800 (PST) Received: from localhost ([::1]:33164 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5ewx-0007Jq-Iy for importer@patchew.org; Thu, 06 Jan 2022 21:25:51 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52774) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5dZ9-0001A7-Vg for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:57:12 -0500 Received: from [2607:f8b0:4864:20::334] (port=41928 helo=mail-ot1-x334.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n5dZ8-0005Bc-Dc for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:57:11 -0500 Received: by mail-ot1-x334.google.com with SMTP id n17-20020a9d64d1000000b00579cf677301so4975913otl.8 for ; Thu, 06 Jan 2022 16:57:10 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id e4sm678441oiy.12.2022.01.06.16.49.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 16:49:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jpFlMaPtAV8PGNPWTK3CGyRMHE5OZo4qgrPLCNS5aSY=; b=Bd3Id2FTZmvNrhQKKsOv3iKGi0M0u0uzkvPDrsjCFwBmtfMB7IIx58EECoWruYn02H 80N8IMDIpm2OUWWt9PVPnrS/TwARNg21OEx9sdb1Rs1soO0/rgu1yCnEx7Bq5+Xv5Fva 6BAmGGNjE/ZjauBEkZ8yYlBQdgAHeegWm9mqN/Qk9x1Yf7nOvP1dITxKWKrzgMPm0nhv ZsZv0aUipUbp873f0+tgHT9n1WuioyMaYhbBGjYzidvzgoFDSUzvB2mzeZwc2F9Lps5l Rw4EXQbcXOClJEyz8TPwMmxF/A9BwXZb5COYMPV03Bp/Ub8s3ShHIul1K2c1BY228jw5 3A2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jpFlMaPtAV8PGNPWTK3CGyRMHE5OZo4qgrPLCNS5aSY=; b=Nav8h9jmwhFfbF8/78OzZZRxohWnjdc3uFEWb18sDfIgN918neDT2RqtHx93wHXvKM 2INiYxkfBv+PdD9MQxRu/SZA5kdkCSKP7rDyWRqhPbBB/ytqltX/ZoIkSea4NKCB0P9M ZqbgG0ASpf6ULE1xzpKZJOE0uomsGm5SPx6FEzjhyopjQ/rKwvljoAw30O/N/YqwHPBj a+iRqNlKkW6hr53SrZVJEx27RCwdUWLlQySlZMaabuJFfZo95fDjSyq1GWubweqb2ycp qKVPgpeLjpAXboIUuC9NBUGUSqfyxn5HaddoaJKz41RQ353LjLiGj3D4AgbWzbmeljSm W99Q== X-Gm-Message-State: AOAM531iEUScxKZdFxDhzi2i5ri8hh6I+QZGXBdIBRtq1cvnJIzzuOca viBOwDx7Job25cVmRS/8hP/g5IpneXny18D2 X-Google-Smtp-Source: ABdhPJxQJzdCzdsV4dCZO7PMRU7PzbgFtVdv4sSlejLbx1qOlWtQ6ME09XS3bRpJQvfc70omFuC63A== X-Received: by 2002:a05:6820:556:: with SMTP id n22mr37704ooj.60.1641516567871; Thu, 06 Jan 2022 16:49:27 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 01/11] target/riscv: Fix PMU CSR predicate function Date: Thu, 6 Jan 2022 16:48:36 -0800 Message-Id: <20220107004846.378859-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com> References: <20220107004846.378859-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::334 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=atishp@rivosinc.com; helo=mail-ot1-x334.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 06 Jan 2022 21:14:01 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Bin Meng , Atish Patra , Alistair Francis , Palmer Dabbelt , Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641522353498100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra The predicate function calculates the counter index incorrectly for hpmcounterx. Fix the counter index to reflect correct CSR number. Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault") Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/csr.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 146447eac5d5..53a621fdbaef 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -90,8 +90,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)= ) && - get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))= ) { + ctr_index =3D csrno - CSR_CYCLE; + if (!get_field(env->hcounteren, 1 << ctr_index) && + get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; @@ -117,8 +118,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNT= ER3H)) && - get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTE= R3H))) { + ctr_index =3D csrno - CSR_CYCLEH; + if (!get_field(env->hcounteren, 1 << ctr_index) && + get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; --=20 2.30.2 From nobody Mon Apr 29 19:45:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641521840355312.3511483742084; Thu, 6 Jan 2022 18:17:20 -0800 (PST) Received: from localhost ([::1]:47014 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5eoh-0005AQ-8q for importer@patchew.org; Thu, 06 Jan 2022 21:17:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51032) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5dRl-0001aQ-7Y for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:49:34 -0500 Received: from [2607:f8b0:4864:20::234] (port=38491 helo=mail-oi1-x234.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n5dRi-0003XR-7v for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:49:32 -0500 Received: by mail-oi1-x234.google.com with SMTP id s73so6159037oie.5 for ; Thu, 06 Jan 2022 16:49:29 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id e4sm678441oiy.12.2022.01.06.16.49.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 16:49:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ySDY8m1tY6oV6HqE3QA/CH+8RjjTJfuo39P2Fzqq1cA=; b=PVe5RHJJxOmr6vFmeghn0oe9lBC8ephomBQm5Kb9PMZufWFyIvrISdXuYCAOT/BXGU LGwz7o2vHYknywqoaptEf0sUB4AC2TWIAT0gSjJjsG+x5iCuZDQTDD5ycJ49V8KVwBFy I15Bd4E8x7iZfE+As8QjtBTetOuE2pndUB9zBZNiaI5Nrlo5tOSLFfNy08MFds+DzwqH itVzMrkyyK18dsg8q0I5QIsbyZkW4HzJp8gCJL4TCG5mioDCEaF65cHt/qj+xDcC9ohH QXF1DMf2fRNDXqejAis54qylSIAx2KHK3wZL/94wPFrf/2oZFjqABYWTFopbbKkDNjaz GeHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ySDY8m1tY6oV6HqE3QA/CH+8RjjTJfuo39P2Fzqq1cA=; b=zqB0sgVF4YThKlORO7kvPBx/uZDKmefnzpKnCMuKZkGPCIF/ceVjd+ePd1bBUDTylt 82MRi+zlmBwAG9PQc4YyWO9hige+/z0S2caJrUQy/8QjUyU5+j1Dv8t39wWD/bkiH6yg QS9UMdYy5Izn+wga9QOGUgZSdblYmjI8PIDgucoskOA2TTzp3xAZSj9BBf31goPHcBIc XiJKJjjBDXDssV6e9K6SnIv1+MPD+Gp+O7N5aD0lgoMHh3eXrRQP5UkleWVqiG3Ptt/6 aOwyVXNOovLe32R/AtS8Vz5+2V0uIJD9Dl866en1Y8AdQVrQPrMkpsTmSZo+xYAKUJAT NSeQ== X-Gm-Message-State: AOAM531kYiBQbMUOLb2qfds/YC3ogihqniFSzqW2ZdovZlZTlOCrjhEf E8zldjvn9rm/aE35kjSSM4JGCCeMpKPE7bdA X-Google-Smtp-Source: ABdhPJyA1Kg9rvjmi4KyPz1Cuy+gQHDDUddOqoqIfgNQROyBsRpY70g4MtymMbTw1G+9vbLA8ewIbw== X-Received: by 2002:aca:44c1:: with SMTP id r184mr7944044oia.15.1641516569056; Thu, 06 Jan 2022 16:49:29 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 02/11] target/riscv: Implement PMU CSR predicate function for S-mode Date: Thu, 6 Jan 2022 16:48:37 -0800 Message-Id: <20220107004846.378859-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com> References: <20220107004846.378859-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::234 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=atishp@rivosinc.com; helo=mail-oi1-x234.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 06 Jan 2022 21:14:01 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Bin Meng , Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641521841448100003 Content-Type: text/plain; charset="utf-8" From: Atish Patra Currently, the predicate function for PMU related CSRs only works if virtualization is enabled. It also does not check mcounteren bits before before cycle/minstret/hpmcounterx access. Support supervisor mode access in the predicate function as well. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra Reviewed-by: Bin Meng --- target/riscv/csr.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 53a621fdbaef..823cc306d74b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -63,12 +63,64 @@ static RISCVException ctr(CPURISCVState *env, int csrno) #if !defined(CONFIG_USER_ONLY) CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); + int ctr_index; =20 if (!cpu->cfg.ext_counters) { /* The Counters extensions is not enabled */ return RISCV_EXCP_ILLEGAL_INST; } =20 + if (env->priv =3D=3D PRV_S) { + switch (csrno) { + case CSR_CYCLE: + if (!get_field(env->mcounteren, COUNTEREN_CY)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_TIME: + if (!get_field(env->mcounteren, COUNTEREN_TM)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_INSTRET: + if (!get_field(env->mcounteren, COUNTEREN_IR)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: + ctr_index =3D csrno - CSR_CYCLE; + if (!get_field(env->mcounteren, 1 << ctr_index)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + } + if (riscv_cpu_is_32bit(env)) { + switch (csrno) { + case CSR_CYCLEH: + if (!get_field(env->mcounteren, COUNTEREN_CY)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_TIMEH: + if (!get_field(env->mcounteren, COUNTEREN_TM)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_INSTRETH: + if (!get_field(env->mcounteren, COUNTEREN_IR)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: + ctr_index =3D csrno - CSR_CYCLEH; + if (!get_field(env->mcounteren, 1 << ctr_index)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + } + } + } + if (riscv_cpu_virt_enabled(env)) { switch (csrno) { case CSR_CYCLE: --=20 2.30.2 From nobody Mon Apr 29 19:45:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641521842368837.867933609639; Thu, 6 Jan 2022 18:17:22 -0800 (PST) Received: from localhost ([::1]:47170 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5eoi-0005Ig-VA for importer@patchew.org; Thu, 06 Jan 2022 21:17:21 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51034) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5dRl-0001aR-5o for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:49:34 -0500 Received: from [2607:f8b0:4864:20::232] (port=42545 helo=mail-oi1-x232.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n5dRj-0003Xd-Bq for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:49:32 -0500 Received: by mail-oi1-x232.google.com with SMTP id w80so6116908oie.9 for ; Thu, 06 Jan 2022 16:49:31 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id e4sm678441oiy.12.2022.01.06.16.49.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 16:49:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=37u6j7pc0R3Ygux+uuwwnDcDeg6VENiH2FLX5eNaeJ0=; b=aOpphZnUZQvIRBdNbmO9otrKfE1Ld0zAQ6ESPynRxxbYc34+AD400hYaYLFwnVjWXV 5Wvi2DeDxfU5umSfIUuUj7y9m6SN1hfKbDrswVVx/utZ1kdXpWkHVYUxBBiZCwWDOWsl 33yLgkWc0cLQDa1fUYJF18v7VG3mBTeMedU+c6phLt2jjnroBnc9kc7hstfrTqCrUike vjX/4UqRs0l6tc3f5YF5XnHRXAMDdCj7i1/++4ue/OMj+rM5rIp4ns634As6CiBBjxYx graVWH9jkp0F+4GUhgyTiJ6VmtTfryTxx+N2KjHhCSTvOnGp0cNWLxtauxsq8rq+X90j Mbow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=37u6j7pc0R3Ygux+uuwwnDcDeg6VENiH2FLX5eNaeJ0=; b=OJeGMkpiSuaJwzCJdqDRrB7dM5req2HT2nO3L8V6b6ctRuHDWrDJYGdbZHJ/+sQ4TB JYq2lzrdia1EmCQbruf8n0U5G3qyRpSy7nUMC3S9Yy63XWWeYOM92t8L5QWLQ845lUDK Aznlbf2gdEe+FBaa9+ZiJAwYx1n/0Jc5yu7QpELKwgi0qlrBLI9BAqX3b8G57+wVg6eX wdsAcrKfr68zA57jAqnOcS5NiSnr5g0tnx3AP8kzXmEb6PI6FsGeLJGU0wEkhY8LReFa 89M06ZP63zhXmcFzq/IlvpBpN/UnhzmTx2P4UzbMxmvs/Nou82EsKtZ83ctFkfbG4k3m 0GGw== X-Gm-Message-State: AOAM533FEO7IdpTwonAJcyhNCyqISx/LOVd2ZXSi7Sa7MdeXjaTpOYh2 sxwY6hEiXU3f1968lZvoD6pU2Nzn1RoBRjq2 X-Google-Smtp-Source: ABdhPJz7bnSiQYBr4DgwoXkdJq+4p2z6B6vRzqDHr1GceRJDFNtm0vj/myUM1s9JhHb4ddEcdhNHww== X-Received: by 2002:aca:d704:: with SMTP id o4mr8393070oig.99.1641516570209; Thu, 06 Jan 2022 16:49:30 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 03/11] target/riscv: pmu: Rename the counters extension to pmu Date: Thu, 6 Jan 2022 16:48:38 -0800 Message-Id: <20220107004846.378859-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com> References: <20220107004846.378859-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::232 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=atishp@rivosinc.com; helo=mail-oi1-x232.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 06 Jan 2022 21:14:01 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Bin Meng , Atish Patra , Alistair Francis , Palmer Dabbelt , Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641521843483100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra The PMU counters are supported via cpu config "Counters" which doesn't indicate the correct purpose of those counters. Rename the config property to pmu to indicate that these counters are performance monitoring counters. This aligns with cpu options for ARM architecture as well. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ef3314bced8..df87489f6d87 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -627,7 +627,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), + DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index dc10f27093b0..16d0b4f139ee 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -312,7 +312,7 @@ struct RISCVCPU { bool ext_zbb; bool ext_zbc; bool ext_zbs; - bool ext_counters; + bool ext_pmu; bool ext_ifencei; bool ext_icsr; bool ext_zfh; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 823cc306d74b..a6e856b896a9 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -65,8 +65,8 @@ static RISCVException ctr(CPURISCVState *env, int csrno) RISCVCPU *cpu =3D RISCV_CPU(cs); int ctr_index; =20 - if (!cpu->cfg.ext_counters) { - /* The Counters extensions is not enabled */ + if (!cpu->cfg.ext_pmu) { + /* The PMU extension is not enabled */ return RISCV_EXCP_ILLEGAL_INST; } =20 --=20 2.30.2 From nobody Mon Apr 29 19:45:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641522054368210.58223983232665; Thu, 6 Jan 2022 18:20:54 -0800 (PST) Received: from localhost ([::1]:53846 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5es9-0001cp-0L for importer@patchew.org; Thu, 06 Jan 2022 21:20:53 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51076) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5dRm-0001b9-Hm for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:49:34 -0500 Received: from [2607:f8b0:4864:20::233] (port=36759 helo=mail-oi1-x233.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n5dRk-0003YJ-JT for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:49:34 -0500 Received: by mail-oi1-x233.google.com with SMTP id t23so6164156oiw.3 for ; Thu, 06 Jan 2022 16:49:32 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id e4sm678441oiy.12.2022.01.06.16.49.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 16:49:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VHh5VmpUjejHmdx0j03/5wIQLuHBrxmcEwgGbMS7xBw=; b=JeKDQ5GWKZaP8w6ZR43RDjZPBVvSOFTp2B6xP6lxSQMEtrSyjxZZwxGmGb6OTDudt3 d0aGZh5xM8BRC5e46RS/S+fT7AujZseoaGEuR5B7ZrOO3cxplPHE6uL6fh2giLROPPEb yahToJASstptymkfyha5d/Jj1WEF7rvQ//fkqhiexowr5I8BWS7DZXmc97opQm3a/wV6 dmmQrkcDL3GZ2svP+k1UoAcpYUWH2C/Tim+RV66G8Mxu+jcMFnhhiAiD6L1hB2fhL96r 17l2JEyYGwOAvtqTPxL5FdgH86pOPsqyJav6s+fvxXVTe39shRwLGW/RxqDJ3xLy6Pmw m20A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VHh5VmpUjejHmdx0j03/5wIQLuHBrxmcEwgGbMS7xBw=; b=Y67crZu8N8iQ/pQHrmbMO8kocvdKQGngyJ4JUNpRfDgARLdBN2ryjR9ma8BIYpZJIa QUvRsSEN1Sg2IuOeSopv1odKwAYBkPBVjDd4OVXJ6yi1/TEInQYqGs2jWshNv82Qn6yA 9SNBR4UAkChrFOvP0JTQv5ueJ/ylGI+H0yRr7E8jNC++aRDgDhJlDdOkQbW8DSVGLytB vZkVKZhSt/EIIJKsk8ItkJRoILseTv5NTjOumJk/NlEqknkgzNXnmPbHL2JjJGmWHf8L jgy6QWhTMU2ZOUAJFJIhlnwN5kwhGZ8CpkZbfNavMJ8j2UgQ6q18nLHnY9zklTrZxdE1 ip/g== X-Gm-Message-State: AOAM533DToKX0+mFxuhb8Pf1S9bbERMhgt/Z0IQLJ7f58EHBq+xK4xGj flGgxEy9qYQAOMICr6hV22nRZV2G6k0EEEWe X-Google-Smtp-Source: ABdhPJz5W9X9R4z7XYNeDtR+2ga2DatdmEZqsTixDP3i6EimIPh5zaTscRg/OQXom6MM20tFMTYUtQ== X-Received: by 2002:a05:6808:1b25:: with SMTP id bx37mr6147477oib.166.1641516571295; Thu, 06 Jan 2022 16:49:31 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 04/11] target/riscv: pmu: Make number of counters configurable Date: Thu, 6 Jan 2022 16:48:39 -0800 Message-Id: <20220107004846.378859-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com> References: <20220107004846.378859-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::233 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=atishp@rivosinc.com; helo=mail-oi1-x233.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 06 Jan 2022 21:14:01 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641522055381100002 Content-Type: text/plain; charset="utf-8" The RISC-V privilege specification provides flexibility to implement any number of counters from 29 programmable counters. However, the QEMU implements all the counters. Make it configurable through pmu config parameter which now will indicate how many programmable counters should be implemented by the cpu. Signed-off-by: Atish Patra Signed-off-by: Atish Patra Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 96 ++++++++++++++++++++++++++++++---------------- 3 files changed, 65 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index df87489f6d87..9448c4335347 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -627,7 +627,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true), + DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 16d0b4f139ee..b353770596e8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -312,12 +312,12 @@ struct RISCVCPU { bool ext_zbb; bool ext_zbc; bool ext_zbs; - bool ext_pmu; bool ext_ifencei; bool ext_icsr; bool ext_zfh; bool ext_zfhmin; =20 + uint8_t pmu_num; char *priv_spec; char *user_spec; char *bext_spec; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a6e856b896a9..e31c27e270a2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -58,15 +58,45 @@ static RISCVException vs(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } =20 +static RISCVException mctr(CPURISCVState *env, int csrno) +{ +#if !defined(CONFIG_USER_ONLY) + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + int ctr_index; + int base_csrno =3D CSR_MHPMCOUNTER3; + + if ((riscv_cpu_mxl(env) =3D=3D MXL_RV32) && csrno >=3D CSR_MCYCLEH) { + /* Offset for RV32 mhpmcounternh counters */ + base_csrno +=3D 0x80; + } + ctr_index =3D csrno - base_csrno; + if (!cpu->cfg.pmu_num || ctr_index >=3D cpu->cfg.pmu_num) { + /* The PMU is not enabled or counter is out of range*/ + return RISCV_EXCP_ILLEGAL_INST; + } + +#endif + return RISCV_EXCP_NONE; +} + static RISCVException ctr(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); int ctr_index; + int base_csrno =3D CSR_HPMCOUNTER3; + bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32 ? true : false; + + if (rv32 && csrno >=3D CSR_CYCLEH) { + /* Offset for RV32 hpmcounternh counters */ + base_csrno +=3D 0x80; + } + ctr_index =3D csrno - base_csrno; =20 - if (!cpu->cfg.ext_pmu) { - /* The PMU extension is not enabled */ + if (!cpu->cfg.pmu_num || ctr_index >=3D (cpu->cfg.pmu_num)) { + /* No counter is enabled in PMU or the counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -94,7 +124,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; } - if (riscv_cpu_is_32bit(env)) { + if (rv32) { switch (csrno) { case CSR_CYCLEH: if (!get_field(env->mcounteren, COUNTEREN_CY)) { @@ -149,7 +179,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; } - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + if (rv32) { switch (csrno) { case CSR_CYCLEH: if (!get_field(env->hcounteren, COUNTEREN_CY) && @@ -2060,35 +2090,35 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HPMCOUNTER30] =3D { "hpmcounter30", ctr, read_zero }, [CSR_HPMCOUNTER31] =3D { "hpmcounter31", ctr, read_zero }, =20 - [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", any, read_zero }, - [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", any, read_zero }, - [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", any, read_zero }, - [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", any, read_zero }, - [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", any, read_zero }, - [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", any, read_zero }, - [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", any, read_zero }, - [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", any, read_zero }, - [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", any, read_zero }, - [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", any, read_zero }, - [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", any, read_zero }, - [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", any, read_zero }, - [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", any, read_zero }, - [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", any, read_zero }, - [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", any, read_zero }, - [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", any, read_zero }, - [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", any, read_zero }, - [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", any, read_zero }, - [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", any, read_zero }, - [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", any, read_zero }, - [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", any, read_zero }, - [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", any, read_zero }, - [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", any, read_zero }, - [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", any, read_zero }, - [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", any, read_zero }, - [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", any, read_zero }, - [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", any, read_zero }, - [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", any, read_zero }, - [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", any, read_zero }, + [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", mctr, read_zero }, + [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", mctr, read_zero }, + [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", mctr, read_zero }, + [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", mctr, read_zero }, + [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", mctr, read_zero }, + [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", mctr, read_zero }, + [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", mctr, read_zero }, + [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", mctr, read_zero }, + [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", mctr, read_zero }, + [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", mctr, read_zero }, + [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", mctr, read_zero }, + [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", mctr, read_zero }, + [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", mctr, read_zero }, + [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", mctr, read_zero }, + [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", mctr, read_zero }, + [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", mctr, read_zero }, + [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", mctr, read_zero }, + [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", mctr, read_zero }, + [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", mctr, read_zero }, + [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", mctr, read_zero }, + [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", mctr, read_zero }, + [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", mctr, read_zero }, + [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", mctr, read_zero }, + [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", mctr, read_zero }, + [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", mctr, read_zero }, + [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", mctr, read_zero }, + [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", mctr, read_zero }, + [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", mctr, read_zero }, + [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", mctr, read_zero }, =20 [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_zero }, [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_zero }, --=20 2.30.2 From nobody Mon Apr 29 19:45:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641522061415213.41455208705622; Thu, 6 Jan 2022 18:21:01 -0800 (PST) Received: from localhost ([::1]:54208 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5esG-0001rj-D2 for importer@patchew.org; Thu, 06 Jan 2022 21:21:00 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51084) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5dRn-0001c8-7c for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:49:35 -0500 Received: from [2607:f8b0:4864:20::229] (port=35833 helo=mail-oi1-x229.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n5dRl-0003Yk-JC for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:49:34 -0500 Received: by mail-oi1-x229.google.com with SMTP id s127so6171777oig.2 for ; Thu, 06 Jan 2022 16:49:33 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id e4sm678441oiy.12.2022.01.06.16.49.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 16:49:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OHcEqbEMZFsECN3bk5bVRgpiQ6HgzLUfEvGG9C9v8II=; b=4DdaBQx3cmOaXCeKV9DV/OYwkRfoVJCDoJYGaJg2bmArs2D5xkLzXHAfM481OFWgGp hWLYpJo1wJV6DCow7XXDzp0sNjg9zTFjGlULKh3qvVveIzp+ID6jwIQRte7C9UM6O1TE KvRev61onqFKOQhRltpptZK7lpSgu85P2Nt4/s6/bXk0BQW6fLQ+oK6TCSQKSyozhr0l XQYxxpzXq0AR8HyZktV17vQjusbfZw8rZDw2dUnbqFgt0DKMv/Q1dPXeBKndmVLMgruX qqKO4pIkJs333nZBZWA8NDtEmJ3hG3lTeJ3CrFZ4LEIFK+8Shn41JqQvXp19N5XqAqqD qieg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OHcEqbEMZFsECN3bk5bVRgpiQ6HgzLUfEvGG9C9v8II=; b=rqouCNZdsQSqe1YnZq4G3E8IGsRaJ0Xhbie8lVT7rOTNsmBPMODMBwKbBf7SwW2zop ZFVzAzq1rLL3zAfWXjVyVbl2y6nWN883AVxfVqAqc5xMFux5RHHZNAoOin809Qh/TX+r wXPICIdknbcNBna9mSVIVjpQuLqmPF6OvlimeinzTvaKt3tM4rRsXesAyWTFWsRMYpZh l1ZTdeVkwOf2RKGhRPlJf9xJJxFcAs7uaGMZ2KU4wjmvLleYtzLyUKAdGQRm9CBNATlh ysMJI6m0g2vG2StMZ7V1sTIb7J2SSBllPuAulPHV1kPpuzneJdAYR9WMLZc9rHl/aL9a yGmw== X-Gm-Message-State: AOAM530hMpvP/FZPvA027fmIPx3T1pKRiD8cyHtXPO/ov3J4Zb0lzfkQ VwANu7PKdFZCN96WrokDxodVsE47r8G6/y8w X-Google-Smtp-Source: ABdhPJynhM1YzcWKGE9GD8f3VQtYFHekeYx4wCtEvllZ1rrqQthI1vX565h21ccemVsJ5WwrD8yp8w== X-Received: by 2002:a05:6808:2201:: with SMTP id bd1mr8165418oib.56.1641516572447; Thu, 06 Jan 2022 16:49:32 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 05/11] target/riscv: Implement mcountinhibit CSR Date: Thu, 6 Jan 2022 16:48:40 -0800 Message-Id: <20220107004846.378859-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com> References: <20220107004846.378859-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::229 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=atishp@rivosinc.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 06 Jan 2022 21:14:01 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Bin Meng , Atish Patra , Alistair Francis , Palmer Dabbelt , Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641522063302100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 4 ++++ target/riscv/csr.c | 25 +++++++++++++++++++++++++ target/riscv/machine.c | 1 + 4 files changed, 32 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b353770596e8..6f2875fd9acd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -222,6 +222,8 @@ struct CPURISCVState { target_ulong scounteren; target_ulong mcounteren; =20 + target_ulong mcountinhibit; + target_ulong sscratch; target_ulong mscratch; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 1e31f4d35f5b..dbd9ce9a85a3 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -283,6 +283,10 @@ #define CSR_MHPMCOUNTER29 0xb1d #define CSR_MHPMCOUNTER30 0xb1e #define CSR_MHPMCOUNTER31 0xb1f + +/* Machine counter-inhibit register */ +#define CSR_MCOUNTINHIBIT 0x320 + #define CSR_MHPMEVENT3 0x323 #define CSR_MHPMEVENT4 0x324 #define CSR_MHPMEVENT5 0x325 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e31c27e270a2..89d15b38be7c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -834,6 +834,28 @@ static RISCVException write_mtvec(CPURISCVState *env, = int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno, + target_ulong *val) +{ + if (env->priv_ver < PRIV_VERSION_1_11_0) { + return RISCV_EXCP_ILLEGAL_INST; + } + + *val =3D env->mcountinhibit; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno, + target_ulong val) +{ + if (env->priv_ver < PRIV_VERSION_1_11_0) { + return RISCV_EXCP_ILLEGAL_INST; + } + + env->mcountinhibit =3D val; + return RISCV_EXCP_NONE; +} + static RISCVException read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) { @@ -2120,6 +2142,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", mctr, read_zero }, [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", mctr, read_zero }, =20 + [CSR_MCOUNTINHIBIT] =3D { "mcountinhibit", any, read_mcountinhib= it, + write_mcountinhibit= }, + [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_zero }, [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_zero }, [CSR_MHPMEVENT5] =3D { "mhpmevent5", any, read_zero }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ad8248ebfda8..ea4a382c140a 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -205,6 +205,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.mtval, RISCVCPU), VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINTTL(env.mcounteren, RISCVCPU), + VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), --=20 2.30.2 From nobody Mon Apr 29 19:45:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641522347832304.1054279294407; Thu, 6 Jan 2022 18:25:47 -0800 (PST) Received: from localhost ([::1]:33024 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5ewn-0007Ds-IO for importer@patchew.org; Thu, 06 Jan 2022 21:25:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51138) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5dRr-0001fd-3D for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:49:39 -0500 Received: from [2607:f8b0:4864:20::32e] (port=37806 helo=mail-ot1-x32e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n5dRn-0003ZB-Ht for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:49:38 -0500 Received: by mail-ot1-x32e.google.com with SMTP id 45-20020a9d0a30000000b0058f1a6df088so4994189otg.4 for ; Thu, 06 Jan 2022 16:49:34 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id e4sm678441oiy.12.2022.01.06.16.49.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 16:49:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9bkNGQ/87l6M4ezmnR+u01Tu9akCZ2+j4xRNNiRSDrM=; b=3B62486LCUD4UHXfJixe2gzlTBtYsg7igGTnWDUrG+hzCbTnP03ZYVo3hGIpHCjBcn OmfxXaLblC5E48kuhh6Dyayb/QwvHzLr3Hk5bpDavb0lAYSLCab2GAGPjxkvvxQQE8+v C6BeW/7GMgJI1Zh0O6bRlRshp5ztu1TLK0coZSeFaYSg9QhLo/4x0W7j8WK2MIO7bs8L heZd5PfbEDnhzoapaNnWFAl6+YkgfT7Lt6ZyAn7s0FhSu2mtoRpJoctxk1fahcdeRS0+ Gna1C3Jk/g8+bWLh3xl7h+cVGfQ5SNVPkCCBOepkCEDQhc7ECA84Cl7x43IcFhLr3bU6 znIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9bkNGQ/87l6M4ezmnR+u01Tu9akCZ2+j4xRNNiRSDrM=; b=7or+AkS9Lr5xZkC0HK2ucAf+Ijgv4yqCY1D9XZbpylyfX6+gfLwXnPYPalveKlvc5B owSBWzTjJ4NbxYy3aVUjYYUo2bY7y/fXxq71KNeA47hdYUN6SGg3ShP1xPJB/ZvC8efH zAlUJk4d0r3K5CbHjZFDDfGvdQCNhKILUFym031UAsb3Ng6ORfOaPsmmBUIi/BVtfoK5 E5dxVFd+RFSNBuXbaLd9K6XfAvjHTpyP4rwkIHhPqvmlsT165mR8lDi1PE43vGHkZFHN AMRlYdCOuhb1xW8SoDXfMhbM191LG51p4nBDv2wT2aCpB5pxmO3INlb9PCmvXxBl6fn7 ix2A== X-Gm-Message-State: AOAM533FDdjZQtJHWdpOp7nWdbyVx4dVIKpXB0FzGSM0N3F33KdznWQ8 kb3D9NQ++w76F/zTYS4ubBGKyN518ti+6tzs X-Google-Smtp-Source: ABdhPJzWVZtOm+FFd79fNgLoMj2COJIYRKgN0PeUjdyc+jyZNlRtE1bD0Wn0UsFXN9DxZ1CWPhPrlw== X-Received: by 2002:a05:6830:1d97:: with SMTP id y23mr7282509oti.67.1641516573633; Thu, 06 Jan 2022 16:49:33 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 06/11] target/riscv: Add support for hpmcounters/hpmevents Date: Thu, 6 Jan 2022 16:48:41 -0800 Message-Id: <20220107004846.378859-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com> References: <20220107004846.378859-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::32e (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=atishp@rivosinc.com; helo=mail-ot1-x32e.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 06 Jan 2022 21:14:01 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641522349335100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra With SBI PMU extension, user can use any of the available hpmcounters to track any perf events based on the value written to mhpmevent csr. Add read/write functionality for these csrs. Signed-off-by: Atish Patra Signed-off-by: Atish Patra Reviewed-by: Bin Meng --- target/riscv/cpu.h | 11 + target/riscv/csr.c | 468 ++++++++++++++++++++++++++++------------- target/riscv/machine.c | 3 + 3 files changed, 330 insertions(+), 152 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6f2875fd9acd..39edc948d703 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -101,6 +101,8 @@ typedef struct CPURISCVState CPURISCVState; #endif =20 #define RV_VLEN_MAX 1024 +#define RV_MAX_MHPMEVENTS 29 +#define RV_MAX_MHPMCOUNTERS 32 =20 FIELD(VTYPE, VLMUL, 0, 3) FIELD(VTYPE, VSEW, 3, 3) @@ -224,6 +226,15 @@ struct CPURISCVState { =20 target_ulong mcountinhibit; =20 + /* PMU counter configured values */ + target_ulong mhpmcounter_val[RV_MAX_MHPMCOUNTERS]; + + /* for RV32 */ + target_ulong mhpmcounterh_val[RV_MAX_MHPMCOUNTERS]; + + /* PMU event selector configured values */ + target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; + target_ulong sscratch; target_ulong mscratch; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 89d15b38be7c..58a9550bd898 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -80,6 +80,15 @@ static RISCVException mctr(CPURISCVState *env, int csrno) return RISCV_EXCP_NONE; } =20 +static RISCVException mctr32(CPURISCVState *env, int csrno) +{ + if (riscv_cpu_mxl(env) !=3D MXL_RV32) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return mctr(env, csrno); +} + static RISCVException ctr(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) @@ -464,6 +473,7 @@ static RISCVException read_instret(CPURISCVState *env, = int csrno, #else *val =3D cpu_get_host_ticks(); #endif + return RISCV_EXCP_NONE; } =20 @@ -479,9 +489,76 @@ static RISCVException read_instreth(CPURISCVState *env= , int csrno, #else *val =3D cpu_get_host_ticks() >> 32; #endif + + return RISCV_EXCP_NONE; +} + +static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) +{ + int evt_index =3D csrno - CSR_MHPMEVENT3; + + *val =3D env->mhpmevent_val[evt_index]; + + return RISCV_EXCP_NONE; +} + +static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val) +{ + int evt_index =3D csrno - CSR_MHPMEVENT3; + + env->mhpmevent_val[evt_index] =3D val; + + return RISCV_EXCP_NONE; +} + +static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong v= al) +{ + int ctr_index =3D csrno - CSR_MHPMCOUNTER3 + 3; + + env->mhpmcounter_val[ctr_index] =3D val; + return RISCV_EXCP_NONE; } =20 +static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong = val) +{ + int ctr_index =3D csrno - CSR_MHPMCOUNTER3H + 3; + + env->mhpmcounterh_val[ctr_index] =3D val; + + return RISCV_EXCP_NONE; +} + +static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *va= l) +{ + int ctr_index; + + if (env->priv =3D=3D PRV_M) { + ctr_index =3D csrno - CSR_MHPMCOUNTER3 + 3; + } else { + ctr_index =3D csrno - CSR_HPMCOUNTER3 + 3; + } + *val =3D env->mhpmcounter_val[ctr_index]; + + return RISCV_EXCP_NONE; +} + +static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *v= al) +{ + int ctr_index; + + if (env->priv =3D=3D PRV_M) { + ctr_index =3D csrno - CSR_MHPMCOUNTER3H + 3; + } else { + ctr_index =3D csrno - CSR_HPMCOUNTER3H + 3; + } + + *val =3D env->mhpmcounterh_val[ctr_index]; + + return RISCV_EXCP_NONE; +} + + #if defined(CONFIG_USER_ONLY) static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) @@ -2082,157 +2159,244 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_SPMBASE] =3D { "spmbase", pointer_masking, read_spmbase, write= _spmbase }, =20 /* Performance Counters */ - [CSR_HPMCOUNTER3] =3D { "hpmcounter3", ctr, read_zero }, - [CSR_HPMCOUNTER4] =3D { "hpmcounter4", ctr, read_zero }, - [CSR_HPMCOUNTER5] =3D { "hpmcounter5", ctr, read_zero }, - [CSR_HPMCOUNTER6] =3D { "hpmcounter6", ctr, read_zero }, - [CSR_HPMCOUNTER7] =3D { "hpmcounter7", ctr, read_zero }, - [CSR_HPMCOUNTER8] =3D { "hpmcounter8", ctr, read_zero }, - [CSR_HPMCOUNTER9] =3D { "hpmcounter9", ctr, read_zero }, - [CSR_HPMCOUNTER10] =3D { "hpmcounter10", ctr, read_zero }, - [CSR_HPMCOUNTER11] =3D { "hpmcounter11", ctr, read_zero }, - [CSR_HPMCOUNTER12] =3D { "hpmcounter12", ctr, read_zero }, - [CSR_HPMCOUNTER13] =3D { "hpmcounter13", ctr, read_zero }, - [CSR_HPMCOUNTER14] =3D { "hpmcounter14", ctr, read_zero }, - [CSR_HPMCOUNTER15] =3D { "hpmcounter15", ctr, read_zero }, - [CSR_HPMCOUNTER16] =3D { "hpmcounter16", ctr, read_zero }, - [CSR_HPMCOUNTER17] =3D { "hpmcounter17", ctr, read_zero }, - [CSR_HPMCOUNTER18] =3D { "hpmcounter18", ctr, read_zero }, - [CSR_HPMCOUNTER19] =3D { "hpmcounter19", ctr, read_zero }, - [CSR_HPMCOUNTER20] =3D { "hpmcounter20", ctr, read_zero }, - [CSR_HPMCOUNTER21] =3D { "hpmcounter21", ctr, read_zero }, - [CSR_HPMCOUNTER22] =3D { "hpmcounter22", ctr, read_zero }, - [CSR_HPMCOUNTER23] =3D { "hpmcounter23", ctr, read_zero }, - [CSR_HPMCOUNTER24] =3D { "hpmcounter24", ctr, read_zero }, - [CSR_HPMCOUNTER25] =3D { "hpmcounter25", ctr, read_zero }, - [CSR_HPMCOUNTER26] =3D { "hpmcounter26", ctr, read_zero }, - [CSR_HPMCOUNTER27] =3D { "hpmcounter27", ctr, read_zero }, - [CSR_HPMCOUNTER28] =3D { "hpmcounter28", ctr, read_zero }, - [CSR_HPMCOUNTER29] =3D { "hpmcounter29", ctr, read_zero }, - [CSR_HPMCOUNTER30] =3D { "hpmcounter30", ctr, read_zero }, - [CSR_HPMCOUNTER31] =3D { "hpmcounter31", ctr, read_zero }, - - [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", mctr, read_zero }, - [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", mctr, read_zero }, - [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", mctr, read_zero }, - [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", mctr, read_zero }, - [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", mctr, read_zero }, - [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", mctr, read_zero }, - [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", mctr, read_zero }, - [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", mctr, read_zero }, - [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", mctr, read_zero }, - [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", mctr, read_zero }, - [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", mctr, read_zero }, - [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", mctr, read_zero }, - [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", mctr, read_zero }, - [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", mctr, read_zero }, - [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", mctr, read_zero }, - [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", mctr, read_zero }, - [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", mctr, read_zero }, - [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", mctr, read_zero }, - [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", mctr, read_zero }, - [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", mctr, read_zero }, - [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", mctr, read_zero }, - [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", mctr, read_zero }, - [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", mctr, read_zero }, - [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", mctr, read_zero }, - [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", mctr, read_zero }, - [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", mctr, read_zero }, - [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", mctr, read_zero }, - [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", mctr, read_zero }, - [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", mctr, read_zero }, - - [CSR_MCOUNTINHIBIT] =3D { "mcountinhibit", any, read_mcountinhib= it, - write_mcountinhibit= }, - - [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_zero }, - [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_zero }, - [CSR_MHPMEVENT5] =3D { "mhpmevent5", any, read_zero }, - [CSR_MHPMEVENT6] =3D { "mhpmevent6", any, read_zero }, - [CSR_MHPMEVENT7] =3D { "mhpmevent7", any, read_zero }, - [CSR_MHPMEVENT8] =3D { "mhpmevent8", any, read_zero }, - [CSR_MHPMEVENT9] =3D { "mhpmevent9", any, read_zero }, - [CSR_MHPMEVENT10] =3D { "mhpmevent10", any, read_zero }, - [CSR_MHPMEVENT11] =3D { "mhpmevent11", any, read_zero }, - [CSR_MHPMEVENT12] =3D { "mhpmevent12", any, read_zero }, - [CSR_MHPMEVENT13] =3D { "mhpmevent13", any, read_zero }, - [CSR_MHPMEVENT14] =3D { "mhpmevent14", any, read_zero }, - [CSR_MHPMEVENT15] =3D { "mhpmevent15", any, read_zero }, - [CSR_MHPMEVENT16] =3D { "mhpmevent16", any, read_zero }, - [CSR_MHPMEVENT17] =3D { "mhpmevent17", any, read_zero }, - [CSR_MHPMEVENT18] =3D { "mhpmevent18", any, read_zero }, - [CSR_MHPMEVENT19] =3D { "mhpmevent19", any, read_zero }, - [CSR_MHPMEVENT20] =3D { "mhpmevent20", any, read_zero }, - [CSR_MHPMEVENT21] =3D { "mhpmevent21", any, read_zero }, - [CSR_MHPMEVENT22] =3D { "mhpmevent22", any, read_zero }, - [CSR_MHPMEVENT23] =3D { "mhpmevent23", any, read_zero }, - [CSR_MHPMEVENT24] =3D { "mhpmevent24", any, read_zero }, - [CSR_MHPMEVENT25] =3D { "mhpmevent25", any, read_zero }, - [CSR_MHPMEVENT26] =3D { "mhpmevent26", any, read_zero }, - [CSR_MHPMEVENT27] =3D { "mhpmevent27", any, read_zero }, - [CSR_MHPMEVENT28] =3D { "mhpmevent28", any, read_zero }, - [CSR_MHPMEVENT29] =3D { "mhpmevent29", any, read_zero }, - [CSR_MHPMEVENT30] =3D { "mhpmevent30", any, read_zero }, - [CSR_MHPMEVENT31] =3D { "mhpmevent31", any, read_zero }, - - [CSR_HPMCOUNTER3H] =3D { "hpmcounter3h", ctr32, read_zero }, - [CSR_HPMCOUNTER4H] =3D { "hpmcounter4h", ctr32, read_zero }, - [CSR_HPMCOUNTER5H] =3D { "hpmcounter5h", ctr32, read_zero }, - [CSR_HPMCOUNTER6H] =3D { "hpmcounter6h", ctr32, read_zero }, - [CSR_HPMCOUNTER7H] =3D { "hpmcounter7h", ctr32, read_zero }, - [CSR_HPMCOUNTER8H] =3D { "hpmcounter8h", ctr32, read_zero }, - [CSR_HPMCOUNTER9H] =3D { "hpmcounter9h", ctr32, read_zero }, - [CSR_HPMCOUNTER10H] =3D { "hpmcounter10h", ctr32, read_zero }, - [CSR_HPMCOUNTER11H] =3D { "hpmcounter11h", ctr32, read_zero }, - [CSR_HPMCOUNTER12H] =3D { "hpmcounter12h", ctr32, read_zero }, - [CSR_HPMCOUNTER13H] =3D { "hpmcounter13h", ctr32, read_zero }, - [CSR_HPMCOUNTER14H] =3D { "hpmcounter14h", ctr32, read_zero }, - [CSR_HPMCOUNTER15H] =3D { "hpmcounter15h", ctr32, read_zero }, - [CSR_HPMCOUNTER16H] =3D { "hpmcounter16h", ctr32, read_zero }, - [CSR_HPMCOUNTER17H] =3D { "hpmcounter17h", ctr32, read_zero }, - [CSR_HPMCOUNTER18H] =3D { "hpmcounter18h", ctr32, read_zero }, - [CSR_HPMCOUNTER19H] =3D { "hpmcounter19h", ctr32, read_zero }, - [CSR_HPMCOUNTER20H] =3D { "hpmcounter20h", ctr32, read_zero }, - [CSR_HPMCOUNTER21H] =3D { "hpmcounter21h", ctr32, read_zero }, - [CSR_HPMCOUNTER22H] =3D { "hpmcounter22h", ctr32, read_zero }, - [CSR_HPMCOUNTER23H] =3D { "hpmcounter23h", ctr32, read_zero }, - [CSR_HPMCOUNTER24H] =3D { "hpmcounter24h", ctr32, read_zero }, - [CSR_HPMCOUNTER25H] =3D { "hpmcounter25h", ctr32, read_zero }, - [CSR_HPMCOUNTER26H] =3D { "hpmcounter26h", ctr32, read_zero }, - [CSR_HPMCOUNTER27H] =3D { "hpmcounter27h", ctr32, read_zero }, - [CSR_HPMCOUNTER28H] =3D { "hpmcounter28h", ctr32, read_zero }, - [CSR_HPMCOUNTER29H] =3D { "hpmcounter29h", ctr32, read_zero }, - [CSR_HPMCOUNTER30H] =3D { "hpmcounter30h", ctr32, read_zero }, - [CSR_HPMCOUNTER31H] =3D { "hpmcounter31h", ctr32, read_zero }, - - [CSR_MHPMCOUNTER3H] =3D { "mhpmcounter3h", any32, read_zero }, - [CSR_MHPMCOUNTER4H] =3D { "mhpmcounter4h", any32, read_zero }, - [CSR_MHPMCOUNTER5H] =3D { "mhpmcounter5h", any32, read_zero }, - [CSR_MHPMCOUNTER6H] =3D { "mhpmcounter6h", any32, read_zero }, - [CSR_MHPMCOUNTER7H] =3D { "mhpmcounter7h", any32, read_zero }, - [CSR_MHPMCOUNTER8H] =3D { "mhpmcounter8h", any32, read_zero }, - [CSR_MHPMCOUNTER9H] =3D { "mhpmcounter9h", any32, read_zero }, - [CSR_MHPMCOUNTER10H] =3D { "mhpmcounter10h", any32, read_zero }, - [CSR_MHPMCOUNTER11H] =3D { "mhpmcounter11h", any32, read_zero }, - [CSR_MHPMCOUNTER12H] =3D { "mhpmcounter12h", any32, read_zero }, - [CSR_MHPMCOUNTER13H] =3D { "mhpmcounter13h", any32, read_zero }, - [CSR_MHPMCOUNTER14H] =3D { "mhpmcounter14h", any32, read_zero }, - [CSR_MHPMCOUNTER15H] =3D { "mhpmcounter15h", any32, read_zero }, - [CSR_MHPMCOUNTER16H] =3D { "mhpmcounter16h", any32, read_zero }, - [CSR_MHPMCOUNTER17H] =3D { "mhpmcounter17h", any32, read_zero }, - [CSR_MHPMCOUNTER18H] =3D { "mhpmcounter18h", any32, read_zero }, - [CSR_MHPMCOUNTER19H] =3D { "mhpmcounter19h", any32, read_zero }, - [CSR_MHPMCOUNTER20H] =3D { "mhpmcounter20h", any32, read_zero }, - [CSR_MHPMCOUNTER21H] =3D { "mhpmcounter21h", any32, read_zero }, - [CSR_MHPMCOUNTER22H] =3D { "mhpmcounter22h", any32, read_zero }, - [CSR_MHPMCOUNTER23H] =3D { "mhpmcounter23h", any32, read_zero }, - [CSR_MHPMCOUNTER24H] =3D { "mhpmcounter24h", any32, read_zero }, - [CSR_MHPMCOUNTER25H] =3D { "mhpmcounter25h", any32, read_zero }, - [CSR_MHPMCOUNTER26H] =3D { "mhpmcounter26h", any32, read_zero }, - [CSR_MHPMCOUNTER27H] =3D { "mhpmcounter27h", any32, read_zero }, - [CSR_MHPMCOUNTER28H] =3D { "mhpmcounter28h", any32, read_zero }, - [CSR_MHPMCOUNTER29H] =3D { "mhpmcounter29h", any32, read_zero }, - [CSR_MHPMCOUNTER30H] =3D { "mhpmcounter30h", any32, read_zero }, - [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", any32, read_zero }, + [CSR_HPMCOUNTER3] =3D { "hpmcounter3", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER4] =3D { "hpmcounter4", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER5] =3D { "hpmcounter5", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER6] =3D { "hpmcounter6", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER7] =3D { "hpmcounter7", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER8] =3D { "hpmcounter8", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER9] =3D { "hpmcounter9", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER10] =3D { "hpmcounter10", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER11] =3D { "hpmcounter11", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER12] =3D { "hpmcounter12", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER13] =3D { "hpmcounter13", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER14] =3D { "hpmcounter14", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER15] =3D { "hpmcounter15", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER16] =3D { "hpmcounter16", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER17] =3D { "hpmcounter17", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER18] =3D { "hpmcounter18", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER19] =3D { "hpmcounter19", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER20] =3D { "hpmcounter20", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER21] =3D { "hpmcounter21", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER22] =3D { "hpmcounter22", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER23] =3D { "hpmcounter23", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER24] =3D { "hpmcounter24", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER25] =3D { "hpmcounter25", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER26] =3D { "hpmcounter26", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER27] =3D { "hpmcounter27", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER28] =3D { "hpmcounter28", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER29] =3D { "hpmcounter29", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER30] =3D { "hpmcounter30", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER31] =3D { "hpmcounter31", ctr, read_hpmcounter }, + + [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", mctr, read_hpmcounter, + write_mhpmcounter }, + + [CSR_MCOUNTINHIBIT] =3D { "mcountinhibit", any, read_mcountinhibit, + write_mcountinhibit }, + + [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT5] =3D { "mhpmevent5", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT6] =3D { "mhpmevent6", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT7] =3D { "mhpmevent7", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT8] =3D { "mhpmevent8", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT9] =3D { "mhpmevent9", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT10] =3D { "mhpmevent10", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT11] =3D { "mhpmevent11", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT12] =3D { "mhpmevent12", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT13] =3D { "mhpmevent13", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT14] =3D { "mhpmevent14", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT15] =3D { "mhpmevent15", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT16] =3D { "mhpmevent16", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT17] =3D { "mhpmevent17", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT18] =3D { "mhpmevent18", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT19] =3D { "mhpmevent19", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT20] =3D { "mhpmevent20", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT21] =3D { "mhpmevent21", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT22] =3D { "mhpmevent22", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT23] =3D { "mhpmevent23", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT24] =3D { "mhpmevent24", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT25] =3D { "mhpmevent25", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT26] =3D { "mhpmevent26", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT27] =3D { "mhpmevent27", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT28] =3D { "mhpmevent28", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT29] =3D { "mhpmevent29", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT30] =3D { "mhpmevent30", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT31] =3D { "mhpmevent31", any, read_mhpmevent, + write_mhpmevent }, + + [CSR_HPMCOUNTER3H] =3D { "hpmcounter3h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER4H] =3D { "hpmcounter4h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER5H] =3D { "hpmcounter5h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER6H] =3D { "hpmcounter6h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER7H] =3D { "hpmcounter7h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER8H] =3D { "hpmcounter8h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER9H] =3D { "hpmcounter9h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER10H] =3D { "hpmcounter10h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER11H] =3D { "hpmcounter11h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER12H] =3D { "hpmcounter12h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER13H] =3D { "hpmcounter13h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER14H] =3D { "hpmcounter14h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER15H] =3D { "hpmcounter15h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER16H] =3D { "hpmcounter16h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER17H] =3D { "hpmcounter17h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER18H] =3D { "hpmcounter18h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER19H] =3D { "hpmcounter19h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER20H] =3D { "hpmcounter20h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER21H] =3D { "hpmcounter21h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER22H] =3D { "hpmcounter22h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER23H] =3D { "hpmcounter23h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER24H] =3D { "hpmcounter24h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER25H] =3D { "hpmcounter25h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER26H] =3D { "hpmcounter26h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER27H] =3D { "hpmcounter27h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER28H] =3D { "hpmcounter28h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER29H] =3D { "hpmcounter29h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER30H] =3D { "hpmcounter30h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER31H] =3D { "hpmcounter31h", ctr32, read_hpmcounterh = }, + + [CSR_MHPMCOUNTER3H] =3D { "mhpmcounter3h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER4H] =3D { "mhpmcounter4h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER5H] =3D { "mhpmcounter5h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER6H] =3D { "mhpmcounter6h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER7H] =3D { "mhpmcounter7h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER8H] =3D { "mhpmcounter8h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER9H] =3D { "mhpmcounter9h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER10H] =3D { "mhpmcounter10h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER11H] =3D { "mhpmcounter11h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER12H] =3D { "mhpmcounter12h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER13H] =3D { "mhpmcounter13h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER14H] =3D { "mhpmcounter14h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER15H] =3D { "mhpmcounter15h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER16H] =3D { "mhpmcounter16h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER17H] =3D { "mhpmcounter17h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER18H] =3D { "mhpmcounter18h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER19H] =3D { "mhpmcounter19h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER20H] =3D { "mhpmcounter20h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER21H] =3D { "mhpmcounter21h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER22H] =3D { "mhpmcounter22h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER23H] =3D { "mhpmcounter23h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER24H] =3D { "mhpmcounter24h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER25H] =3D { "mhpmcounter25h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER26H] =3D { "mhpmcounter26h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER27H] =3D { "mhpmcounter27h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER28H] =3D { "mhpmcounter28h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER29H] =3D { "mhpmcounter29h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER30H] =3D { "mhpmcounter30h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ea4a382c140a..d10a3d7472cb 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -206,6 +206,9 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINTTL(env.mcounteren, RISCVCPU), VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), + VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU, RV_MAX_MHPMCOU= NTERS), + VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU, RV_MAX_MHPMCO= UNTERS), + VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENT= S), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), --=20 2.30.2 From nobody Mon Apr 29 19:45:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id e4sm678441oiy.12.2022.01.06.16.49.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 16:49:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aENQJPFve3ajjRyTC43mXBVmqufNDSa0/KRNKBk+P+4=; b=Kabt54z+mS4+BuLDphc68eSeXFAk0KCdZU6Svv7/HYRjGuwDTtWOWkPNRl8PCT8ksO 9/d6rM50vVxOzANa2IU2HySsCInOgWoiUa00NIszynr5TLSLMVCDwEzywpv+veDCMc+L ZVHuTugoz4ncTEGZf0zM4OSV0Pt2zDLsIZWwIyLzPkBmfOguv1RqbmoB5/J7hJCbmndV d/GvtRo5N2MkCN+k01Vcch+yY5G7FV1pynRb0awBiHgmafktju/DAhlg9pN/QuqtUU7x XFM9Bu+sKWeusFm/FGRAACDbayqo9eLxMSzr5imfvnqDrdmmEk8H8ZziUTV5YDWZCyFN MGyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aENQJPFve3ajjRyTC43mXBVmqufNDSa0/KRNKBk+P+4=; b=Mzn+PK6iZ24OTlPtOihGC/S0ooS3r+bWtNQsLBWZCu2hg4S2MtgSFyvIieAtgBYr/y gfVleA5yvGcXXdQgYcRnXPvXlUWQtnZVw56Nhr7V95Q4oI3cezWFce1L2/x6OMqBVKIR +tiZDB8jeuI6SFEV0o+7tpUdQUWGJ1wfjjh3uzVMWufDCqJvmBb3T0HCnuUuuvfkFauf ZSaEFNLHWyWQUoBn347h2a32Bnmesj4aLrASKJ/8oN5/VohUrnAk2Z9T0n+i0XvbcK45 Y7L7URjuzrSM6wnJDjb3ae7ycezO+kbBvYi/X9uvnwtxTJgZfPTe02ZGuKPHH+TUNd8w bJ3A== X-Gm-Message-State: AOAM530xax4NcNam5RnZCBv3cTZ/R+39R/xyEMckqZNtbDJDCd1Lgxx1 uNec6kxT2jApciaWWxsIigyOuu6vQHRe8QAz X-Google-Smtp-Source: ABdhPJzhMsMBi1CRMuoEIqKzbTWatG0DoLdTi2sEtR+NgYLJpE6w4u3GjnPjpItk/7VgH4515FWtgQ== X-Received: by 2002:a05:6808:b16:: with SMTP id s22mr8115074oij.52.1641516574819; Thu, 06 Jan 2022 16:49:34 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation Date: Thu, 6 Jan 2022 16:48:42 -0800 Message-Id: <20220107004846.378859-8-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com> References: <20220107004846.378859-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::22e (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=atishp@rivosinc.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 06 Jan 2022 21:14:01 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641521839653100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Support mcycle/minstret through generic counter infrastructure. Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.h | 24 +++++-- target/riscv/csr.c | 144 ++++++++++++++++++++++++++------------- target/riscv/machine.c | 26 ++++++- target/riscv/meson.build | 1 + target/riscv/pmu.c | 32 +++++++++ target/riscv/pmu.h | 28 ++++++++ 6 files changed, 200 insertions(+), 55 deletions(-) create mode 100644 target/riscv/pmu.c create mode 100644 target/riscv/pmu.h diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 39edc948d703..5fe9c51b38c7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -101,7 +101,7 @@ typedef struct CPURISCVState CPURISCVState; #endif =20 #define RV_VLEN_MAX 1024 -#define RV_MAX_MHPMEVENTS 29 +#define RV_MAX_MHPMEVENTS 32 #define RV_MAX_MHPMCOUNTERS 32 =20 FIELD(VTYPE, VLMUL, 0, 3) @@ -112,6 +112,19 @@ FIELD(VTYPE, VEDIV, 8, 2) FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) =20 +typedef struct PMUCTRState PMUCTRState; +struct PMUCTRState { + /* Current value of a counter */ + target_ulong mhpmcounter_val; + /* Current value of a counter in RV32*/ + target_ulong mhpmcounterh_val; + /* Snapshot values of counter */ + target_ulong mhpmcounter_prev; + /* Snapshort value of a counter in RV32 */ + target_ulong mhpmcounterh_prev; + bool started; +}; + struct CPURISCVState { target_ulong gpr[32]; uint64_t fpr[32]; /* assume both F and D extensions */ @@ -226,13 +239,10 @@ struct CPURISCVState { =20 target_ulong mcountinhibit; =20 - /* PMU counter configured values */ - target_ulong mhpmcounter_val[RV_MAX_MHPMCOUNTERS]; - - /* for RV32 */ - target_ulong mhpmcounterh_val[RV_MAX_MHPMCOUNTERS]; + /* PMU counter state */ + PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; =20 - /* PMU event selector configured values */ + /* PMU event selector configured values. First three are unused*/ target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; =20 target_ulong sscratch; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 58a9550bd898..d4449ada557c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" +#include "pmu.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" =20 @@ -461,41 +462,33 @@ static int write_vcsr(CPURISCVState *env, int csrno, = target_ulong val) } =20 /* User Timers and Counters */ -static RISCVException read_instret(CPURISCVState *env, int csrno, - target_ulong *val) +static target_ulong get_icount_ticks(bool brv32) { + int64_t val; + target_ulong result; + #if !defined(CONFIG_USER_ONLY) if (icount_enabled()) { - *val =3D icount_get(); + val =3D icount_get(); } else { - *val =3D cpu_get_host_ticks(); + val =3D cpu_get_host_ticks(); } #else - *val =3D cpu_get_host_ticks(); + val =3D cpu_get_host_ticks(); #endif =20 - return RISCV_EXCP_NONE; -} - -static RISCVException read_instreth(CPURISCVState *env, int csrno, - target_ulong *val) -{ -#if !defined(CONFIG_USER_ONLY) - if (icount_enabled()) { - *val =3D icount_get() >> 32; + if (brv32) { + result =3D val >> 32; } else { - *val =3D cpu_get_host_ticks() >> 32; + result =3D val; } -#else - *val =3D cpu_get_host_ticks() >> 32; -#endif =20 - return RISCV_EXCP_NONE; + return result; } =20 static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) { - int evt_index =3D csrno - CSR_MHPMEVENT3; + int evt_index =3D csrno - CSR_MCOUNTINHIBIT; =20 *val =3D env->mhpmevent_val[evt_index]; =20 @@ -504,7 +497,7 @@ static int read_mhpmevent(CPURISCVState *env, int csrno= , target_ulong *val) =20 static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val) { - int evt_index =3D csrno - CSR_MHPMEVENT3; + int evt_index =3D csrno - CSR_MCOUNTINHIBIT; =20 env->mhpmevent_val[evt_index] =3D val; =20 @@ -513,52 +506,99 @@ static int write_mhpmevent(CPURISCVState *env, int cs= rno, target_ulong val) =20 static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong v= al) { - int ctr_index =3D csrno - CSR_MHPMCOUNTER3 + 3; + int ctr_idx =3D csrno - CSR_MCYCLE; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; =20 - env->mhpmcounter_val[ctr_index] =3D val; + counter->mhpmcounter_val =3D val; + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + counter->mhpmcounter_prev =3D get_icount_ticks(false); + } else { + /* Other counters can keep incrementing from the given value */ + counter->mhpmcounter_prev =3D val; + } =20 - return RISCV_EXCP_NONE; + return RISCV_EXCP_NONE; } =20 static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong = val) { - int ctr_index =3D csrno - CSR_MHPMCOUNTER3H + 3; + int ctr_idx =3D csrno - CSR_MCYCLEH; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + + counter->mhpmcounterh_val =3D val; + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + counter->mhpmcounterh_prev =3D get_icount_ticks(false); + } else { + counter->mhpmcounterh_prev =3D val; + } + + return RISCV_EXCP_NONE; +} + +static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong = *val, + bool is_uh, uint32_t ctr_idx) +{ + PMUCTRState counter =3D env->pmu_ctrs[ctr_idx]; + target_ulong ctr_prev =3D is_uh ? counter.mhpmcounterh_prev : + counter.mhpmcounter_prev; + target_ulong ctr_val =3D is_uh ? counter.mhpmcounterh_val : + counter.mhpmcounter_val; =20 - env->mhpmcounterh_val[ctr_index] =3D val; + if (get_field(env->mcountinhibit, BIT(ctr_idx))) { + /** + * Counter should not increment if inhibit bit is set. We can't re= ally + * stop the icount counting. Just return the previous value to ind= icate + * that counter was not incremented. + */ + if (!counter.started) { + *val =3D ctr_val; + return RISCV_EXCP_NONE; + } else { + /* Mark that the counter has been stopped */ + counter.started =3D false; + } + } + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + *val =3D get_icount_ticks(is_uh); + } else { + *val =3D ctr_val; + } + + /* No need to handle the overflow here */ + *val =3D *val - ctr_prev + ctr_val; =20 return RISCV_EXCP_NONE; } =20 static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *va= l) { - int ctr_index; + uint16_t ctr_index; =20 if (env->priv =3D=3D PRV_M) { - ctr_index =3D csrno - CSR_MHPMCOUNTER3 + 3; + ctr_index =3D csrno - CSR_MCYCLE; } else { - ctr_index =3D csrno - CSR_HPMCOUNTER3 + 3; + ctr_index =3D csrno - CSR_CYCLE; } - *val =3D env->mhpmcounter_val[ctr_index]; =20 - return RISCV_EXCP_NONE; + return riscv_pmu_read_ctr(env, val, false, ctr_index); } =20 static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *v= al) { - int ctr_index; + uint16_t ctr_index; =20 if (env->priv =3D=3D PRV_M) { - ctr_index =3D csrno - CSR_MHPMCOUNTER3H + 3; + ctr_index =3D csrno - CSR_MCYCLEH; } else { - ctr_index =3D csrno - CSR_HPMCOUNTER3H + 3; + ctr_index =3D csrno - CSR_CYCLEH; } =20 - *val =3D env->mhpmcounterh_val[ctr_index]; - - return RISCV_EXCP_NONE; + return riscv_pmu_read_ctr(env, val, true, ctr_index); } =20 - #if defined(CONFIG_USER_ONLY) static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) @@ -925,11 +965,23 @@ static RISCVException read_mcountinhibit(CPURISCVStat= e *env, int csrno, static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno, target_ulong val) { + int cidx; + PMUCTRState *counter; + if (env->priv_ver < PRIV_VERSION_1_11_0) { return RISCV_EXCP_ILLEGAL_INST; } =20 env->mcountinhibit =3D val; + + /* Check if any other counter is also monitoring cycles/instructions */ + for (cidx =3D 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) { + if (!get_field(env->mcountinhibit, BIT(cidx))) { + counter =3D &env->pmu_ctrs[cidx]; + counter->started =3D true; + } + } + return RISCV_EXCP_NONE; } =20 @@ -2035,10 +2087,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_VTYPE] =3D { "vtype", vs, read_vtype }, [CSR_VLENB] =3D { "vlenb", vs, read_vlenb }, /* User Timers and Counters */ - [CSR_CYCLE] =3D { "cycle", ctr, read_instret }, - [CSR_INSTRET] =3D { "instret", ctr, read_instret }, - [CSR_CYCLEH] =3D { "cycleh", ctr32, read_instreth }, - [CSR_INSTRETH] =3D { "instreth", ctr32, read_instreth }, + [CSR_CYCLE] =3D { "cycle", ctr, read_hpmcounter }, + [CSR_INSTRET] =3D { "instret", ctr, read_hpmcounter }, + [CSR_CYCLEH] =3D { "cycleh", ctr32, read_hpmcounterh }, + [CSR_INSTRETH] =3D { "instreth", ctr32, read_hpmcounterh }, =20 /* * In privileged mode, the monitor will have to emulate TIME CSRs only= if @@ -2049,10 +2101,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 #if !defined(CONFIG_USER_ONLY) /* Machine Timers and Counters */ - [CSR_MCYCLE] =3D { "mcycle", any, read_instret }, - [CSR_MINSTRET] =3D { "minstret", any, read_instret }, - [CSR_MCYCLEH] =3D { "mcycleh", any32, read_instreth }, - [CSR_MINSTRETH] =3D { "minstreth", any32, read_instreth }, + [CSR_MCYCLE] =3D { "mcycle", any, read_hpmcounter, write_mhpmc= ounter}, + [CSR_MINSTRET] =3D { "minstret", any, read_hpmcounter, write_mhpmc= ounter}, + [CSR_MCYCLEH] =3D { "mcycleh", any32, read_hpmcounterh, write_mhpm= counterh}, + [CSR_MINSTRETH] =3D { "minstreth", any32, read_hpmcounterh, write_mhpm= counterh}, =20 /* Machine Information Registers */ [CSR_MVENDORID] =3D { "mvendorid", any, read_zero }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index d10a3d7472cb..829b9f2d1f46 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -164,6 +164,28 @@ static const VMStateDescription vmstate_pointermasking= =3D { } }; =20 +static bool pmu_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + + return cpu->cfg.pmu_num; +} + +static const VMStateDescription vmstate_pmu_ctr_state =3D { + .name =3D "cpu/pmu", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pmu_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState), + VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState), + VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState), + VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState), + VMSTATE_BOOL(started, PMUCTRState), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", .version_id =3D 3, @@ -206,8 +228,8 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINTTL(env.mcounteren, RISCVCPU), VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), - VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU, RV_MAX_MHPMCOU= NTERS), - VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU, RV_MAX_MHPMCO= UNTERS), + VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, = 0, + vmstate_pmu_ctr_state, PMUCTRState), VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENT= S), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), diff --git a/target/riscv/meson.build b/target/riscv/meson.build index d5e0bc93ea9c..992122c4d6f5 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -24,6 +24,7 @@ riscv_softmmu_ss =3D ss.source_set() riscv_softmmu_ss.add(files( 'arch_dump.c', 'pmp.c', + 'pmu.c', 'monitor.c', 'machine.c' )) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c new file mode 100644 index 000000000000..000fe8da45ef --- /dev/null +++ b/target/riscv/pmu.c @@ -0,0 +1,32 @@ +/* + * RISC-V PMU file. + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "pmu.h" + +bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, + uint32_t target_ctr) +{ + return (target_ctr =3D=3D 0) ? true : false; +} + +bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr) +{ + return (target_ctr =3D=3D 2) ? true : false; +} diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h new file mode 100644 index 000000000000..58a5bc3a4089 --- /dev/null +++ b/target/riscv/pmu.h @@ -0,0 +1,28 @@ +/* + * RISC-V PMU header file. + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "cpu.h" +#include "qemu/main-loop.h" +#include "exec/exec-all.h" + +bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, + uint32_t target_ctr); +bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, + uint32_t target_ctr); --=20 2.30.2 From nobody Mon Apr 29 19:45:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641522568473516.0720063413974; Thu, 6 Jan 2022 18:29:28 -0800 (PST) Received: from localhost ([::1]:40072 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5f0R-0003qK-7C for importer@patchew.org; Thu, 06 Jan 2022 21:29:27 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51232) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5dRu-0001gO-96 for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:49:42 -0500 Received: from [2607:f8b0:4864:20::329] (port=36838 helo=mail-ot1-x329.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n5dRq-0003b9-Qv for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:49:42 -0500 Received: by mail-ot1-x329.google.com with SMTP id s21-20020a05683004d500b0058f585672efso5001207otd.3 for ; Thu, 06 Jan 2022 16:49:37 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id e4sm678441oiy.12.2022.01.06.16.49.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 16:49:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xnmS5UT80Sjw3gxlY1wTO1cC5Kb/F+t+PW7Q+T62ErQ=; b=VjHtoUBJyEzhFClzJdQbZJxrNj+67ot4+YTF3Jibq0u+lI0Pd27ydtC4CHni1DWD4k y3r8l7juxEcMFvrolWnj9/hQmrglfQW1Y9eYOKL7w+oSCtvmr7RuSFP70uz6u6EyPnLp YjXpHneob1Eoswdjd8VABrUCZeK+ApBFnedhwxejnlOc5KC/RDBxO1igaHvy4IywzzTd bo9pFF4hCLxPcqTLMvtmIcoRcoGgZNeLON8w+Q5jIk96gFHV24ANzKCZt5STLMWfx4ZT rBzIWPD3TXCFHmt4rxYY/MMLCTSAHDYQNrK/N2cIN1TCanknOdmlYJqcG3QPckCamNni +nDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xnmS5UT80Sjw3gxlY1wTO1cC5Kb/F+t+PW7Q+T62ErQ=; b=qk3vItMAb5KJTzo6fIqn4vo5iYmQQvgW7y4ToAoiPJDNJxA0tQx1jW5oqSSqa9FxHr FjuymMGVCilnuQZKGYEHEibz8pgK0w5aK9BbV/Fz9E7PlOZO3ildQjer+0VeCb7HlvgJ Y95xXE74p79a67WLrNLQbio8V2bYqlt1cMXj/EA8Y1QnH6EgBi3ntelMHQJwFxg2gYCG hptmB4H60mas+PclzGtDvH6LC/9Rq0a7KuhvDvOpg6Ur3SxXIqhdwY0LhUjPMFPIFBYQ 4ayT3FYNnm5WgjrQ7GFs1vfiNzP7Ldg7q+/iehSAEFpsk/x4jzaqz3ZIgpV5cvl6J+E7 ZuDg== X-Gm-Message-State: AOAM531de+UeM590tzKSzKQixSjZyA1HtvVcTlo5nTjF6OGO9eV3DjMy FlFrYkTFPEpreVpS8fP4W4MmaM1JiPeiesgD X-Google-Smtp-Source: ABdhPJyj7JxLVZ5PdI4leqH2+zGQ+d99dNltU4dNiSJ4EwlGkNDllETxyHdkC362DXQ004++ZVqx5Q== X-Received: by 2002:a9d:7e83:: with SMTP id m3mr19565785otp.195.1641516576077; Thu, 06 Jan 2022 16:49:36 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 08/11] target/riscv: Add sscofpmf extension support Date: Thu, 6 Jan 2022 16:48:43 -0800 Message-Id: <20220107004846.378859-9-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com> References: <20220107004846.378859-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::329 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=atishp@rivosinc.com; helo=mail-ot1-x329.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 06 Jan 2022 21:14:01 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641522570792100001 Content-Type: text/plain; charset="utf-8" The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) extension allows the perf to handle overflow interrupts and filtering support. This patch provides a framework for programmable counters to leverage the extension. As the extension doesn't have any provision for the overflow bit for fixed counters, the fixed events can also be monitoring using programmable counters. The underlying counters for cycle and instruction counters are always running. Thus, a separate timer device is programmed to handle the overflow. Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 12 ++ target/riscv/cpu.h | 25 +++ target/riscv/cpu_bits.h | 55 +++++++ target/riscv/csr.c | 156 ++++++++++++++++-- target/riscv/pmu.c | 346 +++++++++++++++++++++++++++++++++++++++- target/riscv/pmu.h | 8 + 6 files changed, 591 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9448c4335347..2ca9f8480b9d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -22,6 +22,7 @@ #include "qemu/ctype.h" #include "qemu/log.h" #include "cpu.h" +#include "pmu.h" #include "internals.h" #include "exec/exec-all.h" #include "qapi/error.h" @@ -569,6 +570,16 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) set_misa(env, env->misa_mxl, ext); } =20 + if (cpu->cfg.pmu_num) { + if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscof) { + cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + riscv_pmu_timer_cb, cpu); + if (!cpu->pmu_timer) { + cpu->cfg.ext_sscof =3D false; + } + } + } + riscv_cpu_register_gdb_regs_for_features(cs); =20 qemu_init_vcpu(cs); @@ -628,6 +639,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), + DEFINE_PROP_BOOL("sscof", RISCVCPU, cfg.ext_sscof, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5fe9c51b38c7..1e5f307df919 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -123,6 +123,8 @@ struct PMUCTRState { /* Snapshort value of a counter in RV32 */ target_ulong mhpmcounterh_prev; bool started; + /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigge= r */ + target_ulong irq_overflow_left; }; =20 struct CPURISCVState { @@ -245,6 +247,9 @@ struct CPURISCVState { /* PMU event selector configured values. First three are unused*/ target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; =20 + /* PMU event selector configured values for RV32*/ + target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; + target_ulong sscratch; target_ulong mscratch; =20 @@ -339,6 +344,7 @@ struct RISCVCPU { bool ext_icsr; bool ext_zfh; bool ext_zfhmin; + bool ext_sscof; =20 uint8_t pmu_num; char *priv_spec; @@ -352,6 +358,12 @@ struct RISCVCPU { bool epmp; uint64_t resetvec; } cfg; + + QEMUTimer *pmu_timer; + /* A bitmask of Available programmable counters */ + uint32_t pmu_avail_ctrs; + /* Mapping of events to counters */ + GHashTable *pmu_event_ctr_map; }; =20 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) @@ -526,6 +538,19 @@ enum { CSR_TABLE_SIZE =3D 0x1000 }; =20 +/** + * The event id are encoded based on the encoding specified in the + * SBI specification v0.3 + */ + +enum riscv_pmu_event_idx { + RISCV_PMU_EVENT_HW_CPU_CYCLES =3D 0x01, + RISCV_PMU_EVENT_HW_INSTRUCTIONS =3D 0x02, + RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS =3D 0x10019, + RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS =3D 0x1001B, + RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS =3D 0x10021, +}; + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index dbd9ce9a85a3..559b60675132 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -316,6 +316,37 @@ #define CSR_MHPMEVENT29 0x33d #define CSR_MHPMEVENT30 0x33e #define CSR_MHPMEVENT31 0x33f + +#define CSR_MHPMEVENT3H 0x723 +#define CSR_MHPMEVENT4H 0x724 +#define CSR_MHPMEVENT5H 0x725 +#define CSR_MHPMEVENT6H 0x726 +#define CSR_MHPMEVENT7H 0x727 +#define CSR_MHPMEVENT8H 0x728 +#define CSR_MHPMEVENT9H 0x729 +#define CSR_MHPMEVENT10H 0x72a +#define CSR_MHPMEVENT11H 0x72b +#define CSR_MHPMEVENT12H 0x72c +#define CSR_MHPMEVENT13H 0x72d +#define CSR_MHPMEVENT14H 0x72e +#define CSR_MHPMEVENT15H 0x72f +#define CSR_MHPMEVENT16H 0x730 +#define CSR_MHPMEVENT17H 0x731 +#define CSR_MHPMEVENT18H 0x732 +#define CSR_MHPMEVENT19H 0x733 +#define CSR_MHPMEVENT20H 0x734 +#define CSR_MHPMEVENT21H 0x735 +#define CSR_MHPMEVENT22H 0x736 +#define CSR_MHPMEVENT23H 0x737 +#define CSR_MHPMEVENT24H 0x738 +#define CSR_MHPMEVENT25H 0x739 +#define CSR_MHPMEVENT26H 0x73a +#define CSR_MHPMEVENT27H 0x73b +#define CSR_MHPMEVENT28H 0x73c +#define CSR_MHPMEVENT29H 0x73d +#define CSR_MHPMEVENT30H 0x73e +#define CSR_MHPMEVENT31H 0x73f + #define CSR_MHPMCOUNTER3H 0xb83 #define CSR_MHPMCOUNTER4H 0xb84 #define CSR_MHPMCOUNTER5H 0xb85 @@ -377,6 +408,7 @@ #define CSR_VSMTE 0x2c0 #define CSR_VSPMMASK 0x2c1 #define CSR_VSPMBASE 0x2c2 +#define CSR_SCOUNTOVF 0xda0 =20 /* mstatus CSR bits */ #define MSTATUS_UIE 0x00000001 @@ -538,6 +570,7 @@ typedef enum RISCVException { #define IRQ_S_EXT 9 #define IRQ_VS_EXT 10 #define IRQ_M_EXT 11 +#define IRQ_PMU_OVF 13 =20 /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) @@ -552,11 +585,13 @@ typedef enum RISCVException { #define MIP_SEIP (1 << IRQ_S_EXT) #define MIP_VSEIP (1 << IRQ_VS_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) +#define MIP_LCOFIP (1 << IRQ_PMU_OVF) =20 /* sip masks */ #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP #define SIP_SEIP MIP_SEIP +#define SIP_LCOFIP MIP_LCOFIP =20 /* MIE masks */ #define MIE_SEIE (1 << IRQ_S_EXT) @@ -629,4 +664,24 @@ typedef enum RISCVException { #define UMTE_U_PM_INSN U_PM_INSN #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_IN= SN) =20 +/* PMU related bits */ +#define MIE_LCOFIE (1 << IRQ_PMU_OVF) + +#define MHPMEVENT_BIT_OF BIT(63) +#define MHPMEVENTH_BIT_OF BIT(31) +#define MHPMEVENT_BIT_MINH BIT(62) +#define MHPMEVENTH_BIT_MINH BIT(30) +#define MHPMEVENT_BIT_SINH BIT(61) +#define MHPMEVENTH_BIT_SINH BIT(29) +#define MHPMEVENT_BIT_UINH BIT(60) +#define MHPMEVENTH_BIT_UINH BIT(28) +#define MHPMEVENT_BIT_VSINH BIT(59) +#define MHPMEVENTH_BIT_VSINH BIT(27) +#define MHPMEVENT_BIT_VUINH BIT(58) +#define MHPMEVENTH_BIT_VUINH BIT(26) + +#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) +#define MHPMEVENT_IDX_MASK 0xFFFFF +#define MHPMEVENT_SSCOF_RESVD 16 + #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d4449ada557c..d3a8bba6a518 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -90,13 +90,26 @@ static RISCVException mctr32(CPURISCVState *env, int cs= rno) return mctr(env, csrno); } =20 +static RISCVException sscof(CPURISCVState *env, int csrno) +{ + #if !defined(CONFIG_USER_ONLY) + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_sscof) { + return RISCV_EXCP_ILLEGAL_INST; + } +#endif + return RISCV_EXCP_NONE; +} + static RISCVException ctr(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); int ctr_index; - int base_csrno =3D CSR_HPMCOUNTER3; + int base_csrno =3D CSR_CYCLE; bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32 ? true : false; =20 if (rv32 && csrno >=3D CSR_CYCLEH) { @@ -105,11 +118,18 @@ static RISCVException ctr(CPURISCVState *env, int csr= no) } ctr_index =3D csrno - base_csrno; =20 - if (!cpu->cfg.pmu_num || ctr_index >=3D (cpu->cfg.pmu_num)) { + if ((csrno >=3D CSR_CYCLE && csrno <=3D CSR_INSTRET) || + (csrno >=3D CSR_CYCLEH && csrno <=3D CSR_INSTRETH)) { + goto skip_ext_pmu_check; + } + + if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & BIT(ctr_index)))) { /* No counter is enabled in PMU or the counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } =20 +skip_ext_pmu_check: + if (env->priv =3D=3D PRV_S) { switch (csrno) { case CSR_CYCLE: @@ -128,7 +148,6 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - ctr_index =3D csrno - CSR_CYCLE; if (!get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_ILLEGAL_INST; } @@ -152,7 +171,6 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - ctr_index =3D csrno - CSR_CYCLEH; if (!get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_ILLEGAL_INST; } @@ -182,7 +200,6 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - ctr_index =3D csrno - CSR_CYCLE; if (!get_field(env->hcounteren, 1 << ctr_index) && get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -210,7 +227,6 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - ctr_index =3D csrno - CSR_CYCLEH; if (!get_field(env->hcounteren, 1 << ctr_index) && get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -462,7 +478,7 @@ static int write_vcsr(CPURISCVState *env, int csrno, ta= rget_ulong val) } =20 /* User Timers and Counters */ -static target_ulong get_icount_ticks(bool brv32) +target_ulong get_icount_ticks(bool brv32) { int64_t val; target_ulong result; @@ -499,11 +515,36 @@ static int write_mhpmevent(CPURISCVState *env, int cs= rno, target_ulong val) { int evt_index =3D csrno - CSR_MCOUNTINHIBIT; =20 + if (riscv_cpu_mxl(env) !=3D MXL_RV32) { + riscv_pmu_update_event_map(env, val, evt_index); + } env->mhpmevent_val[evt_index] =3D val; =20 return RISCV_EXCP_NONE; } =20 +static int read_mhpmeventh(CPURISCVState *env, int csrno, target_ulong *va= l) +{ + int evt_index =3D csrno - CSR_MHPMEVENT3H + 3; + + *val =3D env->mhpmevent_val[evt_index]; + + return RISCV_EXCP_NONE; +} + +static int write_mhpmeventh(CPURISCVState *env, int csrno, target_ulong va= l) +{ + int evt_index =3D csrno - CSR_MHPMEVENT3H + 3; + uint64_t mhpmevth_val =3D val; + uint64_t mhpmevt_val =3D env->mhpmevent_val[evt_index]; + + mhpmevt_val =3D mhpmevt_val | (mhpmevth_val << 32); + riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); + env->mhpmeventh_val[evt_index] =3D val; + + return RISCV_EXCP_NONE; +} + static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong v= al) { int ctr_idx =3D csrno - CSR_MCYCLE; @@ -513,6 +554,9 @@ static int write_mhpmcounter(CPURISCVState *env, int cs= rno, target_ulong val) if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { counter->mhpmcounter_prev =3D get_icount_ticks(false); + if (ctr_idx > 2) { + riscv_pmu_setup_timer(env, val, ctr_idx); + } } else { /* Other counters can keep incrementing from the given value */ counter->mhpmcounter_prev =3D val; @@ -525,11 +569,17 @@ static int write_mhpmcounterh(CPURISCVState *env, int= csrno, target_ulong val) { int ctr_idx =3D csrno - CSR_MCYCLEH; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + uint64_t mhpmctr_val =3D counter->mhpmcounter_val; + uint64_t mhpmctrh_val =3D val; =20 counter->mhpmcounterh_val =3D val; + mhpmctr_val =3D mhpmctr_val | (mhpmctrh_val << 32); if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { counter->mhpmcounterh_prev =3D get_icount_ticks(false); + if (ctr_idx > 2) { + riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); + } } else { counter->mhpmcounterh_prev =3D val; } @@ -599,6 +649,32 @@ static int read_hpmcounterh(CPURISCVState *env, int cs= rno, target_ulong *val) return riscv_pmu_read_ctr(env, val, true, ctr_index); } =20 +static int read_scountovf(CPURISCVState *env, int csrno, target_ulong *val) +{ + int mhpmevt_start =3D CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT; + int i; + *val =3D 0; + target_ulong *mhpm_evt_val; + uint64_t of_bit_mask; + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + mhpm_evt_val =3D env->mhpmeventh_val; + of_bit_mask =3D MHPMEVENTH_BIT_OF; + } else { + mhpm_evt_val =3D env->mhpmevent_val; + of_bit_mask =3D MHPMEVENT_BIT_OF; + } + + for (i =3D mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) { + if ((get_field(env->mcounteren, BIT(i))) && + (mhpm_evt_val[i] & of_bit_mask)) { + *val |=3D BIT(i); + } + } + + return RISCV_EXCP_NONE; +} + #if defined(CONFIG_USER_ONLY) static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) @@ -645,7 +721,7 @@ static RISCVException read_timeh(CPURISCVState *env, in= t csrno, /* Machine constants */ =20 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) -#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) +#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP | MIP_LCOFIP) #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) =20 static const target_ulong delegable_ints =3D S_MODE_INTERRUPTS | @@ -683,7 +759,8 @@ static const target_ulong vs_delegable_excps =3D DELEGA= BLE_EXCPS & static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; -static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP; +static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP | + SIP_LCOFIP; static const target_ulong hip_writable_mask =3D MIP_VSSIP; static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | M= IP_VSEIP; static const target_ulong vsip_writable_mask =3D MIP_VSSIP; @@ -2362,6 +2439,65 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MHPMEVENT31] =3D { "mhpmevent31", any, read_mhpmevent, write_mhpmevent }, =20 + [CSR_MHPMEVENT3H] =3D { "mhpmevent3h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT4H] =3D { "mhpmevent4h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT5H] =3D { "mhpmevent5h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT6H] =3D { "mhpmevent6h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT7H] =3D { "mhpmevent7h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT8H] =3D { "mhpmevent8h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT9H] =3D { "mhpmevent9h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT10H] =3D { "mhpmevent10h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT11H] =3D { "mhpmevent11h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT12H] =3D { "mhpmevent12h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT13H] =3D { "mhpmevent13h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT14H] =3D { "mhpmevent14h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT15H] =3D { "mhpmevent15h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT16H] =3D { "mhpmevent16h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT17H] =3D { "mhpmevent17h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT18H] =3D { "mhpmevent18h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT19H] =3D { "mhpmevent19h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT20H] =3D { "mhpmevent20h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT21H] =3D { "mhpmevent21h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT22H] =3D { "mhpmevent22h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT23H] =3D { "mhpmevent23h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT24H] =3D { "mhpmevent24h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT25H] =3D { "mhpmevent25h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT26H] =3D { "mhpmevent26h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT27H] =3D { "mhpmevent27h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT28H] =3D { "mhpmevent28h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT29H] =3D { "mhpmevent29h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT30H] =3D { "mhpmevent30h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT31H] =3D { "mhpmevent31h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_HPMCOUNTER3H] =3D { "hpmcounter3h", ctr32, read_hpmcounterh = }, [CSR_HPMCOUNTER4H] =3D { "hpmcounter4h", ctr32, read_hpmcounterh = }, [CSR_HPMCOUNTER5H] =3D { "hpmcounter5h", ctr32, read_hpmcounterh = }, @@ -2450,5 +2586,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_mhpmcounterh = }, [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", mctr32, read_hpmcounterh, write_mhpmcounterh = }, + [CSR_SCOUNTOVF] =3D { "scountovf", sscof, read_scountovf }, + #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 000fe8da45ef..15f161059fb7 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -20,13 +20,355 @@ #include "cpu.h" #include "pmu.h" =20 +#define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ +#define MAKE_32BIT_MASK(shift, length) \ + (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) + +static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) +{ + if (ctr_idx < 3 || ctr_idx >=3D RV_MAX_MHPMCOUNTERS || + !(cpu->pmu_avail_ctrs & BIT(ctr_idx))) { + return false; + } else { + return true; + } +} + +static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, uint32_t ctr_idx) +{ + CPURISCVState *env =3D &cpu->env; + + if (!riscv_pmu_counter_valid(cpu, ctr_idx) || + !get_field(env->mcounteren, BIT(ctr_idx))) { + return false; + } else { + return true; + } +} + +static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx) +{ + CPURISCVState *env =3D &cpu->env; + target_ulong max_val =3D UINT32_MAX; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + + /* Privilege mode filtering */ + if ((env->priv =3D=3D PRV_M && + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) || + (env->priv =3D=3D PRV_S && + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_SINH)) || + (env->priv =3D=3D PRV_U && + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_UINH))) { + return 0; + } + + /* Handle the overflow scenario */ + if (counter->mhpmcounter_val =3D=3D max_val) { + if (counter->mhpmcounterh_val =3D=3D max_val) { + counter->mhpmcounter_val =3D 0; + counter->mhpmcounterh_val =3D 0; + /* Generate interrupt only if OF bit is clear */ + if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) { + env->mhpmeventh_val[ctr_idx] |=3D MHPMEVENTH_BIT_OF; + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + } + } else { + counter->mhpmcounterh_val++; + } + } else { + counter->mhpmcounter_val++; + } + + return 0; +} + +static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx) +{ + CPURISCVState *env =3D &cpu->env; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + uint64_t max_val =3D UINT64_MAX; + + /* Privilege mode filtering */ + if ((env->priv =3D=3D PRV_M && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) || + (env->priv =3D=3D PRV_S && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) || + (env->priv =3D=3D PRV_U && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) { + return 0; + } + + /* Handle the overflow scenario */ + if (counter->mhpmcounter_val =3D=3D max_val) { + counter->mhpmcounter_val =3D 0; + /* Generate interrupt only if OF bit is clear */ + if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { + env->mhpmevent_val[ctr_idx] |=3D MHPMEVENT_BIT_OF; + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + } + } else { + counter->mhpmcounter_val++; + } + return 0; +} + +int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) +{ + uint32_t ctr_idx; + int ret; + CPURISCVState *env =3D &cpu->env; + gpointer value; + + value =3D g_hash_table_lookup(cpu->pmu_event_ctr_map, + GUINT_TO_POINTER(event_idx)); + if (!value) { + return -1; + } + + ctr_idx =3D GPOINTER_TO_UINT(value); + if (!riscv_pmu_counter_enabled(cpu, ctr_idx) || + get_field(env->mcountinhibit, BIT(ctr_idx))) { + return -1; + } + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + ret =3D riscv_pmu_incr_ctr_rv32(cpu, ctr_idx); + } else { + ret =3D riscv_pmu_incr_ctr_rv64(cpu, ctr_idx); + } + + return ret; +} + bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, uint32_t target_ctr) { - return (target_ctr =3D=3D 0) ? true : false; + RISCVCPU *cpu; + uint32_t event_idx; + uint32_t ctr_idx; + + /* Fixed instret counter */ + if (target_ctr =3D=3D 2) { + return true; + } + + cpu =3D RISCV_CPU(env_cpu(env)); + event_idx =3D RISCV_PMU_EVENT_HW_INSTRUCTIONS; + ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, + GUINT_TO_POINTER(event_idx))); + if (!ctr_idx) { + return false; + } + + return target_ctr =3D=3D ctr_idx ? true : false; } =20 bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr) { - return (target_ctr =3D=3D 2) ? true : false; + RISCVCPU *cpu; + uint32_t event_idx; + uint32_t ctr_idx; + + /* Fixed mcycle counter */ + if (target_ctr =3D=3D 0) { + return true; + } + + cpu =3D RISCV_CPU(env_cpu(env)); + event_idx =3D RISCV_PMU_EVENT_HW_CPU_CYCLES; + ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, + GUINT_TO_POINTER(event_idx))); + + /* Counter zero is not used for event_ctr_map */ + if (!ctr_idx) { + return false; + } + + return (target_ctr =3D=3D ctr_idx) ? true : false; +} + +static gboolean pmu_remove_event_map(gpointer key, gpointer value, + gpointer udata) +{ + return (GPOINTER_TO_UINT(value) =3D=3D GPOINTER_TO_UINT(udata)) ? true= : false; +} + +static int64_t pmu_icount_ticks_to_ns(int64_t value) +{ + int64_t ret =3D 0; + + if (icount_enabled()) { + ret =3D icount_to_ns(value); + } else { + ret =3D (NANOSECONDS_PER_SECOND / RISCV_TIMEBASE_FREQ) * value; + } + + return ret; +} + +int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, + uint32_t ctr_idx) +{ + uint32_t event_idx; + RISCVCPU *cpu =3D RISCV_CPU(env_cpu(env)); + + if (!riscv_pmu_counter_valid(cpu, ctr_idx)) { + return -1; + } + + /** + * Expected mhpmevent value is zero for reset case. Remove the current + * mapping. + */ + if (!value) { + g_hash_table_foreach_remove(cpu->pmu_event_ctr_map, + pmu_remove_event_map, + GUINT_TO_POINTER(ctr_idx)); + return 0; + } + + event_idx =3D value & MHPMEVENT_IDX_MASK; + if (g_hash_table_lookup(cpu->pmu_event_ctr_map, + GUINT_TO_POINTER(event_idx))) { + return 0; + } + + switch (event_idx) { + case RISCV_PMU_EVENT_HW_CPU_CYCLES: + case RISCV_PMU_EVENT_HW_INSTRUCTIONS: + case RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS: + case RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS: + case RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS: + break; + default: + /* We don't support any raw events right now */ + return -1; + } + g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx= ), + GUINT_TO_POINTER(ctr_idx)); + + return 0; +} + +static void pmu_timer_trigger_irq(RISCVCPU *cpu, + enum riscv_pmu_event_idx evt_idx) +{ + uint32_t ctr_idx; + CPURISCVState *env =3D &cpu->env; + PMUCTRState *counter; + target_ulong *mhpmevent_val; + uint64_t of_bit_mask; + int64_t irq_trigger_at; + + if (evt_idx !=3D RISCV_PMU_EVENT_HW_CPU_CYCLES && + evt_idx !=3D RISCV_PMU_EVENT_HW_INSTRUCTIONS) { + return; + } + + ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, + GUINT_TO_POINTER(evt_idx))); + if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) { + return; + } + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + mhpmevent_val =3D &env->mhpmeventh_val[ctr_idx]; + of_bit_mask =3D MHPMEVENTH_BIT_OF; + } else { + mhpmevent_val =3D &env->mhpmevent_val[ctr_idx]; + of_bit_mask =3D MHPMEVENT_BIT_OF; + } + + counter =3D &env->pmu_ctrs[ctr_idx]; + if (counter->irq_overflow_left > 0) { + irq_trigger_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + counter->irq_overflow_left; + timer_mod_anticipate_ns(cpu->pmu_timer, irq_trigger_at); + counter->irq_overflow_left =3D 0; + return; + } + + if (cpu->pmu_avail_ctrs & BIT(ctr_idx)) { + /* Generate interrupt only if OF bit is clear */ + if (!(*mhpmevent_val & of_bit_mask)) { + *mhpmevent_val |=3D of_bit_mask; + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + } + } +} + +/* Timer callback for instret and cycle counter overflow */ +void riscv_pmu_timer_cb(void *priv) +{ + RISCVCPU *cpu =3D priv; + + /* Timer event was triggered only for these events */ + pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES); + pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS); +} + +int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr= _idx) +{ + uint64_t overflow_delta, overflow_at; + int64_t overflow_ns, overflow_left =3D 0; + RISCVCPU *cpu =3D RISCV_CPU(env_cpu(env)); + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + + if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscof) { + return -1; + } + + if (value) { + overflow_delta =3D UINT64_MAX - value + 1; + } else { + overflow_delta =3D UINT64_MAX - value; + } + + /** + * QEMU supports only int64_t timers while RISC-V counters are uint64_= t. + * Compute the leftover and save it so that it can be reprogrammed aga= in + * when timer expires. + */ + if (overflow_delta > INT64_MAX) { + overflow_left =3D overflow_delta - INT64_MAX; + } + + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + overflow_ns =3D pmu_icount_ticks_to_ns((int64_t)overflow_delta); + overflow_left =3D pmu_icount_ticks_to_ns(overflow_left) ; + } else { + return -1; + } + overflow_at =3D (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + over= flow_ns; + + if (overflow_at > INT64_MAX) { + overflow_left +=3D overflow_at - INT64_MAX; + counter->irq_overflow_left =3D overflow_left; + overflow_at =3D INT64_MAX; + } + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + + return 0; +} + + +int riscv_pmu_init(RISCVCPU *cpu, int num_counters) +{ + if (num_counters > (RV_MAX_MHPMCOUNTERS - 3)) { + return -1; + } + + cpu->pmu_event_ctr_map =3D g_hash_table_new(g_direct_hash, g_direct_eq= ual); + if (!cpu->pmu_event_ctr_map) { + /* PMU support can not be enabled */ + qemu_log_mask(LOG_UNIMP, "PMU events can't be supported\n"); + cpu->cfg.pmu_num =3D 0; + return -1; + } + + /* Create a bitmask of available programmable counters */ + cpu->pmu_avail_ctrs =3D MAKE_32BIT_MASK(3, num_counters); + + return 0; } diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 58a5bc3a4089..9b400c3522f2 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -26,3 +26,11 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *e= nv, uint32_t target_ctr); bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr); +void riscv_pmu_timer_cb(void *priv); +int riscv_pmu_init(RISCVCPU *cpu, int num_counters); +int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, + uint32_t ctr_idx); +int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); +target_ulong get_icount_ticks(bool brv32); +int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, + uint32_t ctr_idx); --=20 2.30.2 From nobody Mon Apr 29 19:45:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641522308185263.8903872766431; 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id e4sm678441oiy.12.2022.01.06.16.49.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 16:49:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3fgFzCI3gythJlZEsU/Ay0AuUtj0QDTQYBmVeLzXkXw=; b=yCT2zxv99wE8i+PlHSkrccCgfBXQ7Ysmo40K4Xk7CIytQZUtzJj/Sfbm7enKSJXVCh y/2NfPdE+RzILi41wQHmxLkAuc3rBLb1LhoEUVgeIARrb41IpIm7olye848GxqF+tA2t TLZyKFavAbJdf5rYuJiGVMacbgQ3K60wikbpOCFN+sk09zzqas7LHoXvjXJ9IUY0xC/6 zK8deB6AoyFbe/RuKw5ZWnzHuGYtjFTMf82Aiwe9NmGpWaWf1qnh1ErJN0pOz1nHNqt+ USlo7tn16eJVeNVV5nBSjX/O1x+ugfof2cvqwtbjayEjSm75GTskPe2X9S+jcHY9ilqu uDpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3fgFzCI3gythJlZEsU/Ay0AuUtj0QDTQYBmVeLzXkXw=; b=F0WGsYe2xeWKPrrSfzPR1V+zlza3/RLOMDXPk4N/K1yOjgPHTuVv3GJglH7GBQP/UG ph4PpkOq1Vw1KP1UuX9BArbqBwhbOlDU0l5x/c2sA2hCs1EoCrRKLCEcbJoksC2rf26L G/NxBjoTNQjVnjKV18KkSOYLbHXlkcaZU9o7Pi/NCHqtG3s6K9Vs9mUJDFv1G7u2Txkf V1yEcTSLTB+AW/ZzVOGYShaSIIy2JKo+7oG6PzfzIul+KL9t3eETnZd/+95gb2sx6XLR iLxlWaFqyHIEQBjW3Azdk/6XGQBvZcqQ9xDPIaAXR1mHvEaK2/Ae43pqtWIrcyRwQzjk gP/g== X-Gm-Message-State: AOAM533zOuDys01qZh/kdb/IPQy9gCCD7qFxXyV/a60+YyfIgNWt63L2 VgF7qvp6mHflUW89Yj2qXInLOk9kTFdXv7ZC X-Google-Smtp-Source: ABdhPJxCvvgD3uy2A12bp/EaBt6Piq84YKxz21faRvR1BHzs4F5xCzYP/mkcHqvwnWOLq8vkicUdvw== X-Received: by 2002:a05:6808:1389:: with SMTP id c9mr8397311oiw.55.1641516577236; Thu, 06 Jan 2022 16:49:37 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 09/11] target/riscv: Simplify counter predicate function Date: Thu, 6 Jan 2022 16:48:44 -0800 Message-Id: <20220107004846.378859-10-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com> References: <20220107004846.378859-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::230 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=atishp@rivosinc.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 06 Jan 2022 21:14:01 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641522308980100003 Content-Type: text/plain; charset="utf-8" All the hpmcounters and the fixed counters (CY, IR, TM) can be represented as a unified counter. Thus, the predicate function doesn't need handle each case separately. Simplify the predicate function so that we just handle things differently between RV32/RV64 and S/HS mode. Signed-off-by: Atish Patra Reviewed-by: Bin Meng --- target/riscv/csr.c | 111 ++++----------------------------------------- 1 file changed, 10 insertions(+), 101 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d3a8bba6a518..feb053eb3f7b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -109,6 +109,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); int ctr_index; + uint64_t ctr_mask; int base_csrno =3D CSR_CYCLE; bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32 ? true : false; =20 @@ -117,122 +118,30 @@ static RISCVException ctr(CPURISCVState *env, int cs= rno) base_csrno +=3D 0x80; } ctr_index =3D csrno - base_csrno; + ctr_mask =3D BIT(ctr_index); =20 if ((csrno >=3D CSR_CYCLE && csrno <=3D CSR_INSTRET) || (csrno >=3D CSR_CYCLEH && csrno <=3D CSR_INSTRETH)) { goto skip_ext_pmu_check; } =20 - if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & BIT(ctr_index)))) { + if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & ctr_mask))) { /* No counter is enabled in PMU or the counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } =20 skip_ext_pmu_check: =20 - if (env->priv =3D=3D PRV_S) { - switch (csrno) { - case CSR_CYCLE: - if (!get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_TIME: - if (!get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_INSTRET: - if (!get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - } - if (rv32) { - switch (csrno) { - case CSR_CYCLEH: - if (!get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_TIMEH: - if (!get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_INSTRETH: - if (!get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - } - } + if ((env->priv =3D=3D PRV_S) && (!get_field(env->mcounteren, ctr_mask)= )) { + return RISCV_EXCP_ILLEGAL_INST; } =20 if (riscv_cpu_virt_enabled(env)) { - switch (csrno) { - case CSR_CYCLE: - if (!get_field(env->hcounteren, COUNTEREN_CY) && - get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_TIME: - if (!get_field(env->hcounteren, COUNTEREN_TM) && - get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_INSTRET: - if (!get_field(env->hcounteren, COUNTEREN_IR) && - get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->hcounteren, 1 << ctr_index) && - get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - } - if (rv32) { - switch (csrno) { - case CSR_CYCLEH: - if (!get_field(env->hcounteren, COUNTEREN_CY) && - get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_TIMEH: - if (!get_field(env->hcounteren, COUNTEREN_TM) && - get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_INSTRETH: - if (!get_field(env->hcounteren, COUNTEREN_IR) && - get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->hcounteren, 1 << ctr_index) && - get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - } + if (!get_field(env->mcounteren, ctr_mask)) { + /* The bit must be set in mcountern for HS mode access */ + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } else if (!get_field(env->hcounteren, ctr_mask)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } } #endif --=20 2.30.2 From nobody Mon Apr 29 19:45:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641522808869936.192790400926; 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id e4sm678441oiy.12.2022.01.06.16.49.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 16:49:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QO4W2orHMUIEGgVLqHlQDSztkcs6iInWNOtkvj8q0FM=; b=4+LmrWL77uGbhC3BQvrDflx1p1SNhrhuDJOyHF/ta3YtraUtHDIQ+qqAMuwUcKe51l iS3fUrVjRzf8ViiuqlaTD/Wxopi868Kg2j5z0Pz9RAj2+JXpQGWcyjphpU/l9SfkBkN3 GgxffZd3/JUpqiU8He6Dz8pt43Hmp1D+dFW7OVKTCm9AA0pCcT++OHtNrOcQOGSxYku5 cN4h1olAVJSjDk20ocePDLjgh6qKiaKMGaKhZ2886/584ZDPkvYNXc0R+royEyCaJ6aA E89gWwDdyEYw6ovFAEkA//uGeqOB/ZZqkkMvraZ5tBPhNNryg5d0avPjCRT+NHr4AnW9 eTog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QO4W2orHMUIEGgVLqHlQDSztkcs6iInWNOtkvj8q0FM=; b=aw0TJPb87H4vtVpl05aPdXR5uok+gAg6Sz9ztrmosGQjdc82n4g9UI/V2zyFJPypxW dCH+IG7DEwmFD2lmv8Nj65svBrWHhXw0rFBiAvgIAPyeGj89oJ1RTMxtQCxVA+1+Y6I9 bZs8qecK3kJtAcII6niVT0KETcJXc0fN9TSYXnY+2SPZHQcjh2GPIktz0xlaByUE3dZ+ Rb+Lxk8ZXfziR+Z1uD4Al4qLOq3yWk4lJhbsJa8atxg15wORAogk7UkCh7VVBOsKM7WT 42DsNhqn9BHGLysOCzuRYTOXKrnBNsaEuC9u9kckalgJRWzIzG5Y2W/PKY/pMScfchnl GQIg== X-Gm-Message-State: AOAM531WYsbdEfYRaSSulqgTxN++T6LA2oPftXrjGiymj2ahems1z4jF 4Jlj9wrCvJJfJkP9mnGXDx/eepRIxw6ljBxO X-Google-Smtp-Source: ABdhPJxIP9paxXMqxR5aZflz1lYEloykOFdfWC/kLnQEGA60Jm3upexpUPiIfwo42a6v8WdbP8/7PA== X-Received: by 2002:a05:6808:221c:: with SMTP id bd28mr8059822oib.27.1641516578379; Thu, 06 Jan 2022 16:49:38 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 10/11] target/riscv: Add few cache related PMU events Date: Thu, 6 Jan 2022 16:48:45 -0800 Message-Id: <20220107004846.378859-11-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com> References: <20220107004846.378859-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::22d (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=atishp@rivosinc.com; helo=mail-oi1-x22d.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 06 Jan 2022 21:14:01 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641522810704100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu_helper.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 10f3baba5339..bd7871f7b92f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -21,10 +21,13 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "cpu.h" +#include "pmu.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" +#include "cpu.h" +#include "cpu_bits.h" =20 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { @@ -846,6 +849,28 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr= addr, riscv_raise_exception(env, cs->exception_index, retaddr); } =20 + +static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) +{ + enum riscv_pmu_event_idx pmu_event_type; + + switch (access_type) { + case MMU_INST_FETCH: + pmu_event_type =3D RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; + break; + case MMU_DATA_LOAD: + pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; + break; + case MMU_DATA_STORE: + pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; + break; + default: + return; + } + + riscv_pmu_incr_ctr(cpu, pmu_event_type); +} + bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -942,6 +967,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, } } } else { + pmu_tlb_fill_incr_ctr(cpu, access_type); /* Single stage lookup */ ret =3D get_physical_address(env, &pa, &prot, address, NULL, access_type, mmu_idx, true, false, fals= e); --=20 2.30.2 From nobody Mon Apr 29 19:45:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641522637171957.5099330950894; Thu, 6 Jan 2022 18:30:37 -0800 (PST) Received: from localhost ([::1]:40960 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5f1Y-0004RX-3g for importer@patchew.org; Thu, 06 Jan 2022 21:30:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51236) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5dRu-0001gk-Hl for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:49:42 -0500 Received: from [2607:f8b0:4864:20::229] (port=36751 helo=mail-oi1-x229.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n5dRs-0003bx-MR for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:49:42 -0500 Received: by mail-oi1-x229.google.com with SMTP id t23so6164473oiw.3 for ; Thu, 06 Jan 2022 16:49:40 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id e4sm678441oiy.12.2022.01.06.16.49.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 16:49:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SrPx8stRbf0mRCGF+8v7KnYjjZhW/hptPZru7ByP4Qc=; b=cPICLvd4MYixQwPtNjKKWsa+AjUSdRqsLA0DYuO0xdkjhsYd3uPR8zRo7g5lMDpavo /zEv+Z0X2jgSrW+8FW1PVdSHW1rV3cDuyQdRMEzSXi2MG6m4JzbnEcdrFG/wllI+ppf+ Lm/CivA5+jdi2k9v6t4NEmvSDAjbs0Ywxe44R/dw6YiEfJ/eiKEkfXtXzIKHR6O7BpIo Mk2dsctGm5elK+LReX5zs45NZOow4b4dQgRxlkHwXDvWcG5AyKLcNy0DdNFGEXaby3qB sL+YJTq4wd5vh5b5zdLtUHCbV2Hiu1wswy0F8uY0fQMSWEjCNAdngtzqCn85ya0+53DB hZdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SrPx8stRbf0mRCGF+8v7KnYjjZhW/hptPZru7ByP4Qc=; b=KAz1U5Aio5y5eZA+3f4zVBIwAJvWtXAAlgzGJ5xUC+ngWREOq+opA2YdqK1ccWiayn thLN/yUJh06tjN5cJxi5uBJnH82R5VBUCO1nQUyy0fADQz8bzq6+EvZFeINvOZg7tVKH hYN3aWMaWHCYzxSMARCA3hhvY6qDJe9iyNVAFrBTSHWksjtO1WwJ7V3pKM9U8JuWsSFG XrteYcNSP2qTc6YI+2j6XrtqbUZMDWGadem+gXC9ZtykaIS7qZheDnU8w6W1HveIoWh1 NvGHBzL0aXtAp7MGeRzmGduV7hSZmhUwaq1rPlo2z9ZLnE/NmqhsNF3qA9nDKS/Nv6Yn 3qOA== X-Gm-Message-State: AOAM5310HvM88+0zrEUI8gbswEl/+xoZr8UA0KTjhhyAv044YcE6EVYW tlxCEOpHgtATj9B9cFoDFOCT6n1ai9zj9R/J X-Google-Smtp-Source: ABdhPJzXsebZD7W5yIlRf4WvZ7MEJjXRyDmONX4TWhg13q62r1Tk79R/ElJLB7axI663jQkUEBc72Q== X-Received: by 2002:a05:6808:1408:: with SMTP id w8mr8156043oiv.54.1641516579511; Thu, 06 Jan 2022 16:49:39 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 11/11] hw/riscv: virt: Add PMU DT node to the device tree Date: Thu, 6 Jan 2022 16:48:46 -0800 Message-Id: <20220107004846.378859-12-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com> References: <20220107004846.378859-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::229 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=atishp@rivosinc.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 06 Jan 2022 21:14:01 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641522639258100001 Content-Type: text/plain; charset="utf-8" Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. There are some dummy nodes added for testing as well. Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- hw/riscv/virt.c | 38 ++++++++++++++++++++++++++++++++++++++ target/riscv/pmu.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ target/riscv/pmu.h | 1 + 3 files changed, 84 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 3af074148ef4..99154199091c 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -28,6 +28,7 @@ #include "hw/qdev-properties.h" #include "hw/char/serial.h" #include "target/riscv/cpu.h" +#include "target/riscv/pmu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" @@ -406,6 +407,33 @@ static void create_fdt_socket_plic(RISCVVirtState *s, g_free(plic_cells); } =20 +static void create_fdt_socket_pmu(RISCVVirtState *s, + int socket, uint32_t *phandle, + uint32_t *intc_phandles) +{ + int cpu; + char *pmu_name; + uint32_t *pmu_cells; + MachineState *mc =3D MACHINE(s); + RISCVCPU hart =3D s->soc[socket].harts[0]; + + pmu_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 2); + + for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { + pmu_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); + pmu_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_PMU_OVF); + } + + pmu_name =3D g_strdup_printf("/soc/pmu"); + qemu_fdt_add_subnode(mc->fdt, pmu_name); + qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu"); + riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name); + + g_free(pmu_name); + g_free(pmu_cells); +} + + static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memma= p, bool is_32_bit, uint32_t *phandle, uint32_t *irq_mmio_phandle, @@ -417,12 +445,20 @@ static void create_fdt_sockets(RISCVVirtState *s, con= st MemMapEntry *memmap, uint32_t *intc_phandles; MachineState *mc =3D MACHINE(s); uint32_t xplic_phandles[MAX_NODES]; + RISCVCPU hart; =20 qemu_fdt_add_subnode(mc->fdt, "/cpus"); qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); + + /* Add the node for isa extensions discovery */ + qemu_fdt_add_subnode(mc->fdt, "/cpus/riscv,isa-ext"); + hart =3D s->soc[0].harts[0]; + if (hart.cfg.ext_sscof) { + qemu_fdt_setprop(mc->fdt, "/cpus/riscv,isa-ext", "sscofpmf", NULL,= 0); + } qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); =20 for (socket =3D (riscv_socket_count(mc) - 1); socket >=3D 0; socket--)= { @@ -445,6 +481,8 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, create_fdt_socket_plic(s, memmap, socket, phandle, intc_phandles, xplic_phandles); =20 + create_fdt_socket_pmu(s, socket, phandle, intc_phandles); + g_free(intc_phandles); g_free(clust_name); } diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 15f161059fb7..b58a09c85616 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -19,11 +19,56 @@ #include "qemu/osdep.h" #include "cpu.h" #include "pmu.h" +#include "sysemu/device_tree.h" =20 #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ #define MAKE_32BIT_MASK(shift, length) \ (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) =20 +/** + * To keep it simple, any event can be mapped to any programmable counters= in + * QEMU. The generic cycle & instruction count events can also be monitored + * using programmable counters. In that case, mcycle & minstret must conti= nue + * to provide the correct value as well. Hetergenous PMU per hart is not + * supported yet. Thus, number of counters are same across all harts. + */ +void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name) +{ + uint32_t fdt_event_ctr_map[20] =3D {}; + uint32_t cmask; + + /* All the programmable counters can map to any event */ + cmask =3D MAKE_32BIT_MASK(3, num_ctrs); + + /* SBI_PMU_HW_CPU_CYCLES */ + fdt_event_ctr_map[0] =3D cpu_to_be32(0x00000001); + fdt_event_ctr_map[1] =3D cpu_to_be32(0x00000001); + fdt_event_ctr_map[2] =3D cpu_to_be32(cmask | 1 << 0); + + /* SBI_PMU_HW_INSTRUCTIONS */ + fdt_event_ctr_map[3] =3D cpu_to_be32(0x00000002); + fdt_event_ctr_map[4] =3D cpu_to_be32(0x00000002); + fdt_event_ctr_map[5] =3D cpu_to_be32(cmask | 1 << 2); + + /* SBI_PMU_HW_CACHE_DTLB : READ : MISS */ + fdt_event_ctr_map[6] =3D cpu_to_be32(0x00010019); + fdt_event_ctr_map[7] =3D cpu_to_be32(0x00010019); + fdt_event_ctr_map[8] =3D cpu_to_be32(cmask); + + /* SBI_PMU_HW_CACHE_DTLB : WRITE : MISS */ + fdt_event_ctr_map[9] =3D cpu_to_be32(0x0001001B); + fdt_event_ctr_map[10] =3D cpu_to_be32(0x0001001B); + fdt_event_ctr_map[11] =3D cpu_to_be32(cmask); + + /* SBI_PMU_HW_CACHE_ITLB : READ : MISS */ + fdt_event_ctr_map[12] =3D cpu_to_be32(0x00010021); + fdt_event_ctr_map[13] =3D cpu_to_be32(0x00010021); + fdt_event_ctr_map[14] =3D cpu_to_be32(cmask); + + qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters", + fdt_event_ctr_map, sizeof(fdt_event_ctr_map)); +} + static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) { if (ctr_idx < 3 || ctr_idx >=3D RV_MAX_MHPMCOUNTERS || diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 9b400c3522f2..63c4b533b223 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -31,6 +31,7 @@ int riscv_pmu_init(RISCVCPU *cpu, int num_counters); int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); +void riscv_pmu_generate_fdt_node(void *fdt, int num_counters, char *pmu_na= me); target_ulong get_icount_ticks(bool brv32); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); --=20 2.30.2