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[147.11.176.192]) by smtp.gmail.com with ESMTPSA id t191sm36206889pgd.3.2022.01.04.19.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jan 2022 19:08:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9WqiQIt+cavYu/kgllAaaEN8WB4U9OE5aa5Z26l3cBs=; b=RdxmzlATFY0/RslVmEIiIbgPaGycGgtQ70dhge489mE+sR1qd4c+YNOg7CAQH0vW0b akNtiC8ffXgkC/svA+LMuVy9bIT6l956Ip7R9c6AAycYZ+mnxxKqi58BGmGpaIfZ6EQD hl/tCAuggAXgGzP7EUoukD0vfx5NA5Pw0hsFqilUhC+RXgrA+sZMuRJM23dn0M7T0U1p CQX8C/pQuVt4ckNFW4cHiMyZEdlt6Fiozh0jKMRzqPqud+5tRZVyv5PduubB5yiVMbYB t8fdElLXX0zhaW+1bxD2n++41C977q36VVn18omYCQXt2psGwEdGYYOvyNoMVPq7HpgI VHvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9WqiQIt+cavYu/kgllAaaEN8WB4U9OE5aa5Z26l3cBs=; b=gAK78wmlMYf9ErB188b/KFMRIX9yM+cWSImuCI0fUlFOu7gThmYY846K5ZKzfS8DRv I6ECCvkVcU9fuxII83ZM1I1ZXuWJa0FfEKop2Eifa6m5d4/Dgm7cdOhg4qOM+v//b8lw awCuHNH4QZhzo+m4RCXfJ428L4guHrae32VzfaxkPZQWLKpko0NrJTB9hPX7ac0+Pflc KhYJGvc1gEjPnNdNXty5XBm8DG1eFnPt3/0qJnyqFvsoNWOG3+FjvLxs65m7ssORe/g3 kCa8IDxFx3AL6vLz8ez8tsTD+Ug+YQv2SzeuoXa7ULcvzh6dW+NcQAnqMBmHuAojNtHS I7lQ== X-Gm-Message-State: AOAM532komBTN5Gj4Qa3AcQoqhruuqVH3ZfKedXYADLWIbqyIp85Knbk t5Tm5uolsxizn1OD2BwixVBcIrOpYjSbKA== X-Google-Smtp-Source: ABdhPJzkUq7bhWU9uT/zoJ87S8DLyb6tKNHGG13tgKHyC9jEfDxFZ7bJ3wRAtvqY+cgFchCkPZJZTQ== X-Received: by 2002:a17:90b:1d8f:: with SMTP id pf15mr1681881pjb.237.1641352132041; Tue, 04 Jan 2022 19:08:52 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RESEND PATCH v3 1/7] target/riscv: Add initial support for native debug Date: Wed, 5 Jan 2022 11:08:38 +0800 Message-Id: <20220105030844.780642-2-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105030844.780642-1-bmeng.cn@gmail.com> References: <20220105030844.780642-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1033 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1641352309809100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng This adds initial support for the native debug via the Trigger Module, as defined in the RISC-V Debug Specification [1]. Only "Address / Data Match" trigger (type 2) is implemented as of now, which is mainly used for hardware breakpoint and watchpoint. The number of type 2 triggers implemented is 2, which is the number that we can find in the SiFive U54/U74 cores. [1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable= .pdf Signed-off-by: Bin Meng --- Changes in v3: - drop riscv_trigger_init(), which will be moved to patch #5 target/riscv/cpu.h | 5 + target/riscv/debug.h | 108 +++++++++++++ target/riscv/debug.c | 339 +++++++++++++++++++++++++++++++++++++++ target/riscv/meson.build | 1 + 4 files changed, 453 insertions(+) create mode 100644 target/riscv/debug.h create mode 100644 target/riscv/debug.c diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index dc10f27093..0f3b3a4219 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -98,6 +98,7 @@ typedef struct CPURISCVState CPURISCVState; =20 #if !defined(CONFIG_USER_ONLY) #include "pmp.h" +#include "debug.h" #endif =20 #define RV_VLEN_MAX 1024 @@ -234,6 +235,10 @@ struct CPURISCVState { pmp_table_t pmp_state; target_ulong mseccfg; =20 + /* trigger module */ + target_ulong trigger_cur; + trigger_type2_t trigger_type2[TRIGGER_TYPE2_NUM]; + /* machine specific rdtime callback */ uint64_t (*rdtime_fn)(uint32_t); uint32_t rdtime_fn_arg; diff --git a/target/riscv/debug.h b/target/riscv/debug.h new file mode 100644 index 0000000000..0a3fda6c72 --- /dev/null +++ b/target/riscv/debug.h @@ -0,0 +1,108 @@ +/* + * QEMU RISC-V Native Debug Support + * + * Copyright (c) 2022 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef RISCV_DEBUG_H +#define RISCV_DEBUG_H + +/* trigger indexes implemented */ +enum { + TRIGGER_TYPE2_IDX_0 =3D 0, + TRIGGER_TYPE2_IDX_1, + TRIGGER_TYPE2_NUM, + TRIGGER_NUM =3D TRIGGER_TYPE2_NUM +}; + +/* register index of tdata CSRs */ +enum { + TDATA1 =3D 0, + TDATA2, + TDATA3, + TDATA_NUM +}; + +typedef enum { + TRIGGER_TYPE_NO_EXIST =3D 0, /* trigger does not exist */ + TRIGGER_TYPE_AD_MATCH =3D 2, /* address/data match trigger */ + TRIGGER_TYPE_INST_CNT =3D 3, /* instruction count trigger */ + TRIGGER_TYPE_INT =3D 4, /* interrupt trigger */ + TRIGGER_TYPE_EXCP =3D 5, /* exception trigger */ + TRIGGER_TYPE_AD_MATCH6 =3D 6, /* new address/data match trigger */ + TRIGGER_TYPE_EXT_SRC =3D 7, /* external source trigger */ + TRIGGER_TYPE_UNAVAIL =3D 15 /* trigger exists, but unavailable */ +} trigger_type_t; + +typedef struct { + target_ulong mcontrol; + target_ulong maddress; + struct CPUBreakpoint *bp; + struct CPUWatchpoint *wp; +} trigger_type2_t; + +/* tdata field masks */ + +#define RV32_TYPE(t) ((uint32_t)(t) << 28) +#define RV32_TYPE_MASK (0xf << 28) +#define RV32_DMODE BIT(27) +#define RV64_TYPE(t) ((uint64_t)(t) << 60) +#define RV64_TYPE_MASK (0xfULL << 60) +#define RV64_DMODE BIT_ULL(59) + +/* mcontrol field masks */ + +#define TYPE2_LOAD BIT(0) +#define TYPE2_STORE BIT(1) +#define TYPE2_EXEC BIT(2) +#define TYPE2_U BIT(3) +#define TYPE2_S BIT(4) +#define TYPE2_M BIT(6) +#define TYPE2_MATCH (0xf << 7) +#define TYPE2_CHAIN BIT(11) +#define TYPE2_ACTION (0xf << 12) +#define TYPE2_SIZELO (0x3 << 16) +#define TYPE2_TIMING BIT(18) +#define TYPE2_SELECT BIT(19) +#define TYPE2_HIT BIT(20) +#define TYPE2_SIZEHI (0x3 << 21) /* RV64 only */ + +/* access size */ +enum { + SIZE_ANY =3D 0, + SIZE_1B, + SIZE_2B, + SIZE_4B, + SIZE_6B, + SIZE_8B, + SIZE_10B, + SIZE_12B, + SIZE_14B, + SIZE_16B, + SIZE_NUM =3D 16 +}; + +bool tdata_available(CPURISCVState *env, int tdata_index); + +target_ulong tselect_csr_read(CPURISCVState *env); +void tselect_csr_write(CPURISCVState *env, target_ulong val); + +target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index); +void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val= ); + +#endif /* RISCV_DEBUG_H */ diff --git a/target/riscv/debug.c b/target/riscv/debug.c new file mode 100644 index 0000000000..530e030007 --- /dev/null +++ b/target/riscv/debug.c @@ -0,0 +1,339 @@ +/* + * QEMU RISC-V Native Debug Support + * + * Copyright (c) 2022 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This provides the native debug support via the Trigger Module, as defin= ed + * in the RISC-V Debug Specification: + * https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable= .pdf + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "cpu.h" +#include "trace.h" +#include "exec/exec-all.h" + +/* + * The following M-mode trigger CSRs are implemented: + * + * - tselect + * - tdata1 + * - tdata2 + * - tdata3 + * + * We don't support writable 'type' field in the tdata1 register, so there= is + * no need to implement the "tinfo" CSR. + * + * The following triggers are implemented: + * + * Index | Type | tdata mapping | Description + * ------+------+------------------------+------------ + * 0 | 2 | tdata1, tdata2 | Address / Data Match + * 1 | 2 | tdata1, tdata2 | Address / Data Match + */ + +/* tdata availability of a trigger */ +typedef bool tdata_avail[TDATA_NUM]; + +static tdata_avail tdata_mapping[TRIGGER_NUM] =3D { + [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] =3D { true, true, false = }, +}; + +/* only breakpoint size 1/2/4/8 supported */ +static int access_size[SIZE_NUM] =3D { + [SIZE_ANY] =3D 0, + [SIZE_1B] =3D 1, + [SIZE_2B] =3D 2, + [SIZE_4B] =3D 4, + [SIZE_6B] =3D -1, + [SIZE_8B] =3D 8, + [6 ... 15] =3D -1, +}; + +static inline target_ulong trigger_type(CPURISCVState *env, + trigger_type_t type) +{ + target_ulong tdata1; + + switch (riscv_cpu_mxl(env)) { + case MXL_RV32: + tdata1 =3D RV32_TYPE(type); + break; + case MXL_RV64: + tdata1 =3D RV64_TYPE(type); + break; + default: + g_assert_not_reached(); + } + + return tdata1; +} + +bool tdata_available(CPURISCVState *env, int tdata_index) +{ + if (unlikely(tdata_index >=3D TDATA_NUM)) { + return false; + } + + if (unlikely(env->trigger_cur >=3D TRIGGER_NUM)) { + return false; + } + + return tdata_mapping[env->trigger_cur][tdata_index]; +} + +target_ulong tselect_csr_read(CPURISCVState *env) +{ + return env->trigger_cur; +} + +void tselect_csr_write(CPURISCVState *env, target_ulong val) +{ + /* all target_ulong bits of tselect are implemented */ + env->trigger_cur =3D val; +} + +static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val, + trigger_type_t t) +{ + uint32_t type, dmode; + target_ulong tdata1; + + switch (riscv_cpu_mxl(env)) { + case MXL_RV32: + type =3D extract32(val, 28, 4); + dmode =3D extract32(val, 27, 1); + tdata1 =3D RV32_TYPE(t); + break; + case MXL_RV64: + type =3D extract64(val, 60, 4); + dmode =3D extract64(val, 59, 1); + tdata1 =3D RV64_TYPE(t); + break; + default: + g_assert_not_reached(); + } + + if (type !=3D t) { + qemu_log_mask(LOG_GUEST_ERROR, + "ignoring type write to tdata1 register\n"); + } + if (dmode !=3D 0) { + qemu_log_mask(LOG_UNIMP, "debug mode is not supported\n"); + } + + return tdata1; +} + +static inline void warn_always_zero_bit(target_ulong val, target_ulong mas= k, + const char *msg) +{ + if (val & mask) { + qemu_log_mask(LOG_UNIMP, "%s bit is always zero\n", msg); + } +} + +static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctr= l) +{ + uint32_t size, sizelo, sizehi =3D 0; + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { + sizehi =3D extract32(ctrl, 21, 2); + } + sizelo =3D extract32(ctrl, 16, 2); + size =3D (sizehi << 2) | sizelo; + + return size; +} + +static inline bool type2_breakpoint_enabled(target_ulong ctrl) +{ + bool mode =3D !!(ctrl & (TYPE2_U | TYPE2_S | TYPE2_M)); + bool rwx =3D !!(ctrl & (TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC)); + + return mode && rwx; +} + +static target_ulong type2_mcontrol_validate(CPURISCVState *env, + target_ulong ctrl) +{ + target_ulong val; + uint32_t size; + + /* validate the generic part first */ + val =3D tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH); + + /* validate unimplemented (always zero) bits */ + warn_always_zero_bit(ctrl, TYPE2_MATCH, "match"); + warn_always_zero_bit(ctrl, TYPE2_CHAIN, "chain"); + warn_always_zero_bit(ctrl, TYPE2_ACTION, "action"); + warn_always_zero_bit(ctrl, TYPE2_TIMING, "timing"); + warn_always_zero_bit(ctrl, TYPE2_SELECT, "select"); + warn_always_zero_bit(ctrl, TYPE2_HIT, "hit"); + + /* validate size encoding */ + size =3D type2_breakpoint_size(env, ctrl); + if (access_size[size] =3D=3D -1) { + qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using S= IZE_ANY\n", + size); + } else { + val |=3D (ctrl & TYPE2_SIZELO); + if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { + val |=3D (ctrl & TYPE2_SIZEHI); + } + } + + /* keep the mode and attribute bits */ + val |=3D (ctrl & (TYPE2_U | TYPE2_S | TYPE2_M | + TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC)); + + return val; +} + +static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index) +{ + target_ulong ctrl =3D env->trigger_type2[index].mcontrol; + target_ulong addr =3D env->trigger_type2[index].maddress; + bool enabled =3D type2_breakpoint_enabled(ctrl); + CPUState *cs =3D env_cpu(env); + int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; + uint32_t size; + + if (!enabled) { + return; + } + + if (ctrl & TYPE2_EXEC) { + cpu_breakpoint_insert(cs, addr, flags, &env->trigger_type2[index].= bp); + } + + if (ctrl & TYPE2_LOAD) { + flags |=3D BP_MEM_READ; + } + if (ctrl & TYPE2_STORE) { + flags |=3D BP_MEM_WRITE; + } + + if (flags & BP_MEM_ACCESS) { + size =3D type2_breakpoint_size(env, ctrl); + if (size !=3D 0) { + cpu_watchpoint_insert(cs, addr, size, flags, + &env->trigger_type2[index].wp); + } else { + cpu_watchpoint_insert(cs, addr, 8, flags, + &env->trigger_type2[index].wp); + } + } +} + +static void type2_breakpoint_remove(CPURISCVState *env, target_ulong index) +{ + CPUState *cs =3D env_cpu(env); + + if (env->trigger_type2[index].bp) { + cpu_breakpoint_remove_by_ref(cs, env->trigger_type2[index].bp); + env->trigger_type2[index].bp =3D NULL; + } + + if (env->trigger_type2[index].wp) { + cpu_watchpoint_remove_by_ref(cs, env->trigger_type2[index].wp); + env->trigger_type2[index].wp =3D NULL; + } +} + +static target_ulong type2_reg_read(CPURISCVState *env, + target_ulong trigger_index, int tdata_i= ndex) +{ + uint32_t index =3D trigger_index - TRIGGER_TYPE2_IDX_0; + target_ulong tdata; + + switch (tdata_index) { + case TDATA1: + tdata =3D env->trigger_type2[index].mcontrol; + break; + case TDATA2: + tdata =3D env->trigger_type2[index].maddress; + break; + default: + g_assert_not_reached(); + } + + return tdata; +} + +static void type2_reg_write(CPURISCVState *env, target_ulong trigger_index, + int tdata_index, target_ulong val) +{ + uint32_t index =3D trigger_index - TRIGGER_TYPE2_IDX_0; + target_ulong new_val; + + switch (tdata_index) { + case TDATA1: + new_val =3D type2_mcontrol_validate(env, val); + if (new_val !=3D env->trigger_type2[index].mcontrol) { + env->trigger_type2[index].mcontrol =3D new_val; + type2_breakpoint_remove(env, index); + type2_breakpoint_insert(env, index); + } + break; + case TDATA2: + if (val !=3D env->trigger_type2[index].maddress) { + env->trigger_type2[index].maddress =3D val; + type2_breakpoint_remove(env, index); + type2_breakpoint_insert(env, index); + } + break; + default: + g_assert_not_reached(); + } + + return; +} + +typedef target_ulong (*tdata_read_func)(CPURISCVState *env, + target_ulong trigger_index, + int tdata_index); + +static tdata_read_func trigger_read_funcs[TRIGGER_NUM] =3D { + [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] =3D type2_reg_read, +}; + +typedef void (*tdata_write_func)(CPURISCVState *env, + target_ulong trigger_index, + int tdata_index, + target_ulong val); + +static tdata_write_func trigger_write_funcs[TRIGGER_NUM] =3D { + [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] =3D type2_reg_write, +}; + +target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index) +{ + tdata_read_func read_func =3D trigger_read_funcs[env->trigger_cur]; + + return read_func(env, env->trigger_cur, tdata_index); +} + +void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) +{ + tdata_write_func write_func =3D trigger_write_funcs[env->trigger_cur]; + + return write_func(env, env->trigger_cur, tdata_index, val); +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index d5e0bc93ea..966d97237a 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -24,6 +24,7 @@ riscv_softmmu_ss =3D ss.source_set() riscv_softmmu_ss.add(files( 'arch_dump.c', 'pmp.c', + 'debug.c', 'monitor.c', 'machine.c' )) --=20 2.25.1 From nobody Thu May 2 12:41:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1641352679; cv=none; d=zohomail.com; s=zohoarc; b=dnhCg/nBpNvVUdMpvnH2TQJ3xBzJOZiE5rTJpVDENAgdDYn/oA7DscpLB/bd4dFfpkq/3bOJeoRvb0aFn/TRGv2Chz5Q4NXtR2bDHXmiQVWAplqGr9Eiy+98txYmy4ExtdcNhG2VKxqUmGX9BOfqy9OeYtYuYxZf7CmCotwI12s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1641352679; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9sdvt0SCvD2QSOMHtz/9igRF47GFOyS9Q4ZZZNZ/yIc=; b=FnVQ0AZNDdZdidzwfEfKlK9z+tCcKUciuKE9pcfrGYAmsJwZhcKjFLAPqkRPfxjDpwPClf5pghD1OGMNo3avmW8vSHgDryElbqs2W6zt50Qvg7de79x9Gr5aJBW5qgiGmHGAOy3eNc9CG0aULWpWc4BSJcQRaQy8OCJhuAx3i9M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641352679646273.00175927199496; Tue, 4 Jan 2022 19:17:59 -0800 (PST) Received: from localhost ([::1]:52698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4woI-0008I2-0D for importer@patchew.org; Tue, 04 Jan 2022 22:17:58 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60374) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4wfZ-00070d-O4; Tue, 04 Jan 2022 22:08:57 -0500 Received: from [2607:f8b0:4864:20::102a] (port=35575 helo=mail-pj1-x102a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n4wfY-0001we-6E; Tue, 04 Jan 2022 22:08:57 -0500 Received: by mail-pj1-x102a.google.com with SMTP id r16-20020a17090a0ad000b001b276aa3aabso2028722pje.0; Tue, 04 Jan 2022 19:08:55 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-176-192.windriver.com. [147.11.176.192]) by smtp.gmail.com with ESMTPSA id t191sm36206889pgd.3.2022.01.04.19.08.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jan 2022 19:08:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9sdvt0SCvD2QSOMHtz/9igRF47GFOyS9Q4ZZZNZ/yIc=; b=obB03EIcWsiKFsUdcQ1O8JyaigoZu5ZHQpBKINBnEnOGC9fksk47Lniz5OYoLpfenR oF8IrOQM18hYSzSqcIWt/+rarvuaEYrCdesSaDjIZgJrFa8pbX2hbbe0nnjEQeCskc/S qYMP9NLkc+nQ/WZ+4byE2wPPhhzfKXIhmrHtkd+StHbnNcFEqhqVI2LFEnuWThhn+gfF 4rN7KxfaQpKNx7d4SNfh/L1MU+ZNtRgp0v0X3Vu3doDGtg4ga2Q2U/wQ/Vmy7X1kDq2N Mhe/OfHHOh7PfRZ5Km1q160ek4hgJRQ17GWWtNh6JRQ0Mh2oFa+WAhpFZIYHpbmkQi52 ymQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9sdvt0SCvD2QSOMHtz/9igRF47GFOyS9Q4ZZZNZ/yIc=; b=B8RJLJ/jL8j4yQrjMAU0hJJYGkEcvo1JE1yBZiuz7Z0O3o7OCH4m67KI9nXUmj7MbB FW91eTz5YkH6Q+kLSxCFFvKSHHfXe7X079HhoGhANeayVMi18KX+iHIif4Wv7aYpkSSO e8Bw/bg9LWdKAWV+vGwMqz+m47RDuNzELeBIwXdgtOzToJUCo/kQWbQQhaHCGX0/lLsR 51nmWRpVP1HbHNS3RMVL6IE800zO9oAVFlSzfC20t1lI/RoMzy3Z9/EXWb+z+1rAJCLV rzlDzOjvXeB0Vm7LTvrlwCBQxl/XVQ7uN3bS3Q7pYYktPOAS2le9Ys9zGPYlxL6eLQpt XyuQ== X-Gm-Message-State: AOAM530+kGX4XhAip/IwuMLVKNPUbDXdzM+cfzs10jT0Op2FjggpcPMM Tp8z36TJkJm9wQ8lkluAy+E= X-Google-Smtp-Source: ABdhPJxoA/J60/Lo8PZcxUMLjVYU4ba3ALv5iSM4fySF7//Ep/pQkBSZFoDaUba4qeLgtO7iyB0JVQ== X-Received: by 2002:a17:902:eaca:b0:148:c78e:3064 with SMTP id p10-20020a170902eaca00b00148c78e3064mr52573116pld.53.1641352134727; Tue, 04 Jan 2022 19:08:54 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RESEND PATCH v3 2/7] target/riscv: machine: Add debug state description Date: Wed, 5 Jan 2022 11:08:39 +0800 Message-Id: <20220105030844.780642-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105030844.780642-1-bmeng.cn@gmail.com> References: <20220105030844.780642-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102a (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1641352680084100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng Add a subsection to machine.c to migrate debug CSR state. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v2) Changes in v2: - new patch: add debug state description target/riscv/machine.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ad8248ebfd..25aa3b38f7 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -164,6 +164,38 @@ static const VMStateDescription vmstate_pointermasking= =3D { } }; =20 +static bool debug_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + CPURISCVState *env =3D &cpu->env; + + return riscv_feature(env, RISCV_FEATURE_DEBUG); +} + +static const VMStateDescription vmstate_debug_type2 =3D { + .name =3D "cpu/debug/type2", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(mcontrol, trigger_type2_t), + VMSTATE_UINTTL(maddress, trigger_type2_t), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_debug =3D { + .name =3D "cpu/debug", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D debug_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), + VMSTATE_STRUCT_ARRAY(env.trigger_type2, RISCVCPU, TRIGGER_TYPE2_NU= M, + 0, vmstate_debug_type2, trigger_type2_t), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", .version_id =3D 3, @@ -218,6 +250,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_hyper, &vmstate_vector, &vmstate_pointermasking, + &vmstate_debug, NULL } }; --=20 2.25.1 From nobody Thu May 2 12:41:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1641352853; cv=none; d=zohomail.com; s=zohoarc; b=m33ASn5LRZeS1jOZ6Xpa8CqGPeqXeNtO+Cm2gQBofLwr+5+LbcNbQcG1ujBrkDVPT7HQelSjCuWqDGbLqvxAjAOq9sgjreAdzqmai7OzPO2NM6BNtAxQX249g7iPfAZTiHBeI7baDN+kJLN+MYXCXoaTRGaiPZGA5nrF3DUXOQU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1641352853; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eOAJlfpeviuZxpZ870fiG0a+l02uIRJcq4Xs27O408E=; b=cLWnF/F3BvTINQRwqBA3RfCkvVS1YZlBV79ipZEYPVUw7diXT+5q3Fme2DlGoEoovn7YRMkMDtrRZkj6nIz9nmX7OJTj+C4nuIB5UF7iM0hukGGo+l63bw1631g9+putFaHWhiQm0e3mIWpNFaQ3bKAEUOP2NiiJmb2UusTt4AY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641352853901517.7944945251508; Tue, 4 Jan 2022 19:20:53 -0800 (PST) Received: from localhost ([::1]:56946 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4wr6-0002jP-It for importer@patchew.org; Tue, 04 Jan 2022 22:20:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60506) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4wfr-0007Zg-Px; Tue, 04 Jan 2022 22:09:15 -0500 Received: from [2607:f8b0:4864:20::633] (port=46746 helo=mail-pl1-x633.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n4wfb-0001xL-4n; Tue, 04 Jan 2022 22:09:15 -0500 Received: by mail-pl1-x633.google.com with SMTP id w7so27833460plp.13; Tue, 04 Jan 2022 19:08:58 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-176-192.windriver.com. [147.11.176.192]) by smtp.gmail.com with ESMTPSA id t191sm36206889pgd.3.2022.01.04.19.08.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jan 2022 19:08:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eOAJlfpeviuZxpZ870fiG0a+l02uIRJcq4Xs27O408E=; b=XidnIAcDnn8cTOGGXL0/IJzkIh+umffhd618+yNwZxysB3sf6r0PRi3JlKdHFNawqT 6i8r7PTH/nTtVR9TFVur06C8Hmau9/I67v06XXjSJaIOIOIO+CSv+LbTY2rvegq0pz6d 6TYNjl/txy1vJ1hnSAlRON4U3vV9H3aAdaExMs38kBhv8eFCUZ+D2CZXgjYcZUZ4UUbe 1FZY6Xo9KbSEBXxJ+90+ZwVpWkvRB7lXqPnxEm4SHgLrYCSdvgfylOOV9U88hZMB+rXY 9Vm9VhU4D/SWjhpVHcl+iN9iT4XIzfHOlxeEh+bHivMi2fTiWhfUgj65CfABsQ5099vx zJBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eOAJlfpeviuZxpZ870fiG0a+l02uIRJcq4Xs27O408E=; b=22LR5O4QoXWpBH7gGNiHQ5j4K0UJjQcCYgTbF36d/FJMFwSoY7rmz+IC7lzGe871yN pccPON0xnIaLXI0mcRAINZTgTWwSdus7DYwyN4w8gx4fLBk2pCLWZ2ooAa1+7dhwvMms 4NvcpTZyj8AGMGEaES5hq4UP5EfkDcPoBEFjvm/NCR02Xu/YYdYstSeVLn5I0a4FdfVi ie0da7e7oVMZrfpPpeEvWi+WDG0dPRA9tiHvdXzBUL9kaWDmZGht9L3r4bhQV8xXJiSw Tq5m7uxDpam1TjKF5hZQzjv6QbG1GxNM+BMXBF/smj8wgU2GHCGqmoZ9WRCmrS9Iy3L4 Fu0g== X-Gm-Message-State: AOAM531hGgbzQnPy337HWM3auZLPobnGIfDQs2ebti43JmFDDwGpSK2t mDkdUKk5qocCZzJfkCqmg7I= X-Google-Smtp-Source: ABdhPJxPqIgeiyLs6eat/aVkPC7pFVGFAR3d6sIbdR3GvzY+iMwjb166L7A/QELLilZKo1Hvl6tr9A== X-Received: by 2002:a17:90b:3143:: with SMTP id ip3mr1730931pjb.58.1641352137580; Tue, 04 Jan 2022 19:08:57 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RESEND PATCH v3 3/7] target/riscv: debug: Implement debug related TCGCPUOps Date: Wed, 5 Jan 2022 11:08:40 +0800 Message-Id: <20220105030844.780642-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105030844.780642-1-bmeng.cn@gmail.com> References: <20220105030844.780642-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::633 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1641352855907100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint} TCGCPUOps and hook them into riscv_tcg_ops. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v2) Changes in v2: - use 0 instead of GETPC() target/riscv/debug.h | 4 +++ target/riscv/cpu.c | 3 ++ target/riscv/debug.c | 75 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 0a3fda6c72..d0f63e2414 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -105,4 +105,8 @@ void tselect_csr_write(CPURISCVState *env, target_ulong= val); target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index); void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val= ); =20 +void riscv_cpu_debug_excp_handler(CPUState *cs); +bool riscv_cpu_debug_check_breakpoint(CPUState *cs); +bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); + #endif /* RISCV_DEBUG_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ef3314bce..3aa07bc019 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -705,6 +705,9 @@ static const struct TCGCPUOps riscv_tcg_ops =3D { .do_interrupt =3D riscv_cpu_do_interrupt, .do_transaction_failed =3D riscv_cpu_do_transaction_failed, .do_unaligned_access =3D riscv_cpu_do_unaligned_access, + .debug_excp_handler =3D riscv_cpu_debug_excp_handler, + .debug_check_breakpoint =3D riscv_cpu_debug_check_breakpoint, + .debug_check_watchpoint =3D riscv_cpu_debug_check_watchpoint, #endif /* !CONFIG_USER_ONLY */ }; =20 diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 530e030007..7760c4611f 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -337,3 +337,78 @@ void tdata_csr_write(CPURISCVState *env, int tdata_ind= ex, target_ulong val) =20 return write_func(env, env->trigger_cur, tdata_index, val); } + +void riscv_cpu_debug_excp_handler(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + cs->watchpoint_hit =3D NULL; + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); + } + } else { + if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) { + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); + } + } +} + +bool riscv_cpu_debug_check_breakpoint(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + CPUBreakpoint *bp; + target_ulong ctrl; + target_ulong pc; + int i; + + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + for (i =3D 0; i < TRIGGER_TYPE2_NUM; i++) { + ctrl =3D env->trigger_type2[i].mcontrol; + pc =3D env->trigger_type2[i].maddress; + + if ((ctrl & TYPE2_EXEC) && (bp->pc =3D=3D pc)) { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + } + } + + return false; +} + +bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + target_ulong ctrl; + target_ulong addr; + int flags; + int i; + + for (i =3D 0; i < TRIGGER_TYPE2_NUM; i++) { + ctrl =3D env->trigger_type2[i].mcontrol; + addr =3D env->trigger_type2[i].maddress; + flags =3D 0; + + if (ctrl & TYPE2_LOAD) { + flags |=3D BP_MEM_READ; + } + if (ctrl & TYPE2_STORE) { + flags |=3D BP_MEM_WRITE; + } + + if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + } + + return false; +} --=20 2.25.1 From nobody Thu May 2 12:41:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[147.11.176.192]) by smtp.gmail.com with ESMTPSA id t191sm36206889pgd.3.2022.01.04.19.08.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jan 2022 19:09:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=geRTMoTOmniVdLxzEbf3bfCiKz4/5LuNyClrvi5S6Yo=; b=ecx5mDHQ//UaisXXoQKz5yR0PM+AOXilMdxplXKJ1x+I304FoKG1cGwDaXXOVBrZRg UC7erxFcA0r6t8WSlvVWinilIshQGZC+FpUhHW8IPBLaC/p0OpjF6+ZRrxX3NeRncIXp 4fx1gDEKyJ9xbzaTYqk7gDEX4Hf/p86KNWGuQ4AbWOFOmADj0z9D4AHMDnLA8DMI/v/8 +5Mgmbf9PUEzQrQFOB87iiGFOpecTKrYAmyhrArgarK7+yCLtkvt/qkbGj4EvK9Ypm8n nfgnzEOYkY6I7vWTI7mHNpLlzSiY8NJqPsww/ToKRMtp/+fjOIHHCAWwp7kT+H7ZVqBH U9Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=geRTMoTOmniVdLxzEbf3bfCiKz4/5LuNyClrvi5S6Yo=; b=5OIOTKh5QvvnGS2aVH1LcEHTW8EeApM52mDu9y2Q8RZRvkS1x6oJO9exM3ZtifTl0+ nX8PphTbGvkgKprrxdYTFbIzXYSAvl9GCdPFbRa9VhcpNJDKLvnJuey5HYKLmYkSygiP d0mtoDzPXwSyKpEh82GXRy86qqEvI4qd5tK+rhgg9KKpLujMFnlCexBuvuFL7y4ikExj SXpLeugD/6W3GJGw1PFVJkT8eqC7xKkIZ4Qd+aN5TKGWvlK55w5Ld0gabL/CuPxTs9D0 iXT+pmBdba3dso/BokFqPKiRh/7ZI3XNs56sOZmxbUKWA0VBymTw2VC/j1hdSSTjnjP8 G++A== X-Gm-Message-State: AOAM533kj9pZRlJ3zG9OaSZvf7gliZooEwRNloB6boNLwK6QoRP+NOvW SgVdKI4X07SepHu8pxqVopk= X-Google-Smtp-Source: ABdhPJx4H9Ep5W11GxtPNscT7hMrPWNbrDzWfuGLSjkyTwgE6n0x1uPd2A6fFJyBE9ISi/Nt53QdiA== X-Received: by 2002:a17:90a:520e:: with SMTP id v14mr1681886pjh.221.1641352140476; Tue, 04 Jan 2022 19:09:00 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RESEND PATCH v3 4/7] target/riscv: cpu: Add a config option for native debug Date: Wed, 5 Jan 2022 11:08:41 +0800 Message-Id: <20220105030844.780642-5-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105030844.780642-1-bmeng.cn@gmail.com> References: <20220105030844.780642-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1034 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1641353204927100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng Add a config option to enable support for native M-mode debug. This is disabled by default and can be enabled with 'debug=3Dtrue'. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v2) Changes in v2: - change the config option to 'disabled' by default target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0f3b3a4219..35445bbc86 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -75,6 +75,7 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, + RISCV_FEATURE_DEBUG, RISCV_FEATURE_MISA }; =20 @@ -332,6 +333,7 @@ struct RISCVCPU { bool mmu; bool pmp; bool epmp; + bool debug; uint64_t resetvec; } cfg; }; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3aa07bc019..d36c31ce9a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -448,6 +448,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) } } =20 + if (cpu->cfg.debug) { + set_feature(env, RISCV_FEATURE_DEBUG); + } + set_resetvec(env, cpu->cfg.resetvec); =20 /* Validate that MISA_MXL is set properly. */ @@ -634,6 +638,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false), =20 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), --=20 2.25.1 From nobody Thu May 2 12:41:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1641352577; cv=none; d=zohomail.com; s=zohoarc; b=D6oSchxxpWLdWcDOit4jb+N9VyCisqoEUfECfcrlpJhXQZBe92sIumj0xiLamZwXPv4vsBnVdhlBh5NTS61V4q/nLhgFQbevk915WcOxkQZCC//Gn/hgpgs2TI1oj2Dzr7wkeac4QJ0xb7u1KbcuYNUkSyUfwMglZeMgkCc8Mxo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1641352577; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fwTz88tSj2yC6sh3Uadzhxd84PIM0JrnBO97AFjz0So=; b=jcBZe2aQ5C/b1lLk4OV19OWNtQGgKHoGx6kyTLrq0tuyB7MAqLsLjHBVWFEU+j0D3MNPN0Vbf5a5w4P55croAnhhw32ZrKGuMgZ3q43i3JZvT0qs6omeLtqmhA1/j3Vkjwv153xegBmLHc0QYpd5AiR+mMdvoqAsWRJYpRnGVQA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641352577014345.97901536812026; Tue, 4 Jan 2022 19:16:17 -0800 (PST) Received: from localhost ([::1]:50442 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4wmd-0006ZQ-LZ for importer@patchew.org; Tue, 04 Jan 2022 22:16:15 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60456) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4wfj-0007Mb-BY; Tue, 04 Jan 2022 22:09:07 -0500 Received: from [2607:f8b0:4864:20::102e] (port=53820 helo=mail-pj1-x102e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n4wfg-0001yJ-Fv; Tue, 04 Jan 2022 22:09:05 -0500 Received: by mail-pj1-x102e.google.com with SMTP id m13so466754pji.3; Tue, 04 Jan 2022 19:09:03 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-176-192.windriver.com. [147.11.176.192]) by smtp.gmail.com with ESMTPSA id t191sm36206889pgd.3.2022.01.04.19.09.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jan 2022 19:09:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fwTz88tSj2yC6sh3Uadzhxd84PIM0JrnBO97AFjz0So=; b=iVx67tHs3ljy60HweEa/rtTxJen1Cs4z8G7U+9gnSrvUdReHd7ff3HmbvfkPZAa23z C0Svp6IVfIM9pf5WVajM5S03MAMOrso1OuvV+DKaRInompnTyrcYg6xCOZy4E+SxMfk7 fljK1ZwlrvJh/Yj2vgMEhYoN4CfTcOpxwllInTMZpqi6Nr/1/jL932RxqKbcdmPbVYJx cAGnSsQ1gYlU0H9FXzqMkH8Ld7jwYmlUUiL9slY+2ozgzeJLdaxvvrCVHtu8ed06ZIfZ +3Y5F6BQAX6IOL8AWDOZoNh1Cw6tG4sZOGiePXFwxSUS/yIcodlUl64lHHVvyQli3x2X X0Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fwTz88tSj2yC6sh3Uadzhxd84PIM0JrnBO97AFjz0So=; b=gWgWEaXQo9FKnD/0NrnWJ/M5ZCgJcfnaDuMdQbbPPtDkUioS5klTvg2C82N6QXkReP iwj4nONoniAAjaWmk6f+62w1XqDSSG/lSJ2lCrwIJ+Nhf98c/BQD6VM4Mxxd9knHICh1 hH+4FfZmkbliQPiKy7byMizw+dP9JAckJ/7gix8gmyVIwsS8eypSmvFgmA3NiaIMWUEK AyocucoGTioy6+Q7qSKg0eWyutF9zSd6E0Aw8VyFO6Hl1MZWehwTC4W6Aeyo9bzvkpO7 dFKwqpT0YHsrR25YcActqYRL6PVHNa3Ec595W7HLMMM47qWnbQfYgoRCNLidT4W2JxGh 6MDg== X-Gm-Message-State: AOAM533DP8sPhqikR1EXVzJGxai9QkzMizwKfGnIT6/QBfF+j6WFuFJg 27Hu69PzLWHluFAKblq5esQ= X-Google-Smtp-Source: ABdhPJwAgQrrlwKOkTkXw1hpYFlyTGKqOk3sKYnpC5mQl2dvd+F0zCw/O0egNbbDgmjKbz3ypoys0w== X-Received: by 2002:a17:90a:7e8a:: with SMTP id j10mr1720882pjl.13.1641352142956; Tue, 04 Jan 2022 19:09:02 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RESEND PATCH v3 5/7] target/riscv: csr: Hook debug CSR read/write Date: Wed, 5 Jan 2022 11:08:42 +0800 Message-Id: <20220105030844.780642-6-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105030844.780642-1-bmeng.cn@gmail.com> References: <20220105030844.780642-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102e (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1641352579450100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng This adds debug CSR read/write support to the RISC-V CSR RW table. Signed-off-by: Bin Meng --- Changes in v3: - add riscv_trigger_init(), moved from patch #1 to this patch target/riscv/debug.h | 2 ++ target/riscv/cpu.c | 6 +++++ target/riscv/csr.c | 57 ++++++++++++++++++++++++++++++++++++++++++++ target/riscv/debug.c | 27 +++++++++++++++++++++ 4 files changed, 92 insertions(+) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index d0f63e2414..f4da2db35d 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -109,4 +109,6 @@ void riscv_cpu_debug_excp_handler(CPUState *cs); bool riscv_cpu_debug_check_breakpoint(CPUState *cs); bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); =20 +void riscv_trigger_init(CPURISCVState *env); + #endif /* RISCV_DEBUG_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d36c31ce9a..17dcc3c14f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -575,6 +575,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) =20 riscv_cpu_register_gdb_regs_for_features(cs); =20 +#ifndef CONFIG_USER_ONLY + if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + riscv_trigger_init(env); + } +#endif + qemu_init_vcpu(cs); cpu_reset(cs); =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 146447eac5..189b9cc8c6 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -220,6 +220,15 @@ static RISCVException epmp(CPURISCVState *env, int csr= no) =20 return RISCV_EXCP_ILLEGAL_INST; } + +static RISCVException debug(CPURISCVState *env, int csrno) +{ + if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} #endif =20 /* User Floating-Point CSRs */ @@ -1464,6 +1473,48 @@ static RISCVException write_pmpaddr(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_tselect(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D tselect_csr_read(env); + return RISCV_EXCP_NONE; +} + +static RISCVException write_tselect(CPURISCVState *env, int csrno, + target_ulong val) +{ + tselect_csr_write(env, val); + return RISCV_EXCP_NONE; +} + +static RISCVException read_tdata(CPURISCVState *env, int csrno, + target_ulong *val) +{ + /* return 0 in tdata1 to end the trigger enumeration */ + if (env->trigger_cur >=3D TRIGGER_NUM && csrno =3D=3D CSR_TDATA1) { + *val =3D 0; + return RISCV_EXCP_NONE; + } + + if (!tdata_available(env, csrno - CSR_TDATA1)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + *val =3D tdata_csr_read(env, csrno - CSR_TDATA1); + return RISCV_EXCP_NONE; +} + +static RISCVException write_tdata(CPURISCVState *env, int csrno, + target_ulong val) +{ + if (!tdata_available(env, csrno - CSR_TDATA1)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + tdata_csr_write(env, csrno - CSR_TDATA1, val); + return RISCV_EXCP_NONE; +} + /* * Functions to access Pointer Masking feature registers * We have to check if current priv lvl could modify @@ -1962,6 +2013,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_PMPADDR14] =3D { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, [CSR_PMPADDR15] =3D { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, =20 + /* Debug CSRs */ + [CSR_TSELECT] =3D { "tselect", debug, read_tselect, write_tselect }, + [CSR_TDATA1] =3D { "tdata1", debug, read_tdata, write_tdata }, + [CSR_TDATA2] =3D { "tdata2", debug, read_tdata, write_tdata }, + [CSR_TDATA3] =3D { "tdata3", debug, read_tdata, write_tdata }, + /* User Pointer Masking */ [CSR_UMTE] =3D { "umte", pointer_masking, read_umte, write= _umte }, [CSR_UPMMASK] =3D { "upmmask", pointer_masking, read_upmmask, write= _upmmask }, diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 7760c4611f..041a0d3a89 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -412,3 +412,30 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CP= UWatchpoint *wp) =20 return false; } + +void riscv_trigger_init(CPURISCVState *env) +{ + target_ulong type2 =3D trigger_type(env, TRIGGER_TYPE_AD_MATCH); + int i; + + /* type 2 triggers */ + for (i =3D 0; i < TRIGGER_TYPE2_NUM; i++) { + /* + * type =3D TRIGGER_TYPE_AD_MATCH + * dmode =3D 0 (both debug and M-mode can write tdata) + * maskmax =3D 0 (unimplemented, always 0) + * sizehi =3D 0 (match against any size, RV64 only) + * hit =3D 0 (unimplemented, always 0) + * select =3D 0 (always 0, perform match on address) + * timing =3D 0 (always 0, trigger before instruction) + * sizelo =3D 0 (match against any size) + * action =3D 0 (always 0, raise a breakpoint exception) + * chain =3D 0 (unimplemented, always 0) + * match =3D 0 (always 0, when any compare value equals tdata2) + */ + env->trigger_type2[i].mcontrol =3D type2; + env->trigger_type2[i].maddress =3D 0; + env->trigger_type2[i].bp =3D NULL; + env->trigger_type2[i].wp =3D NULL; + } +} --=20 2.25.1 From nobody Thu May 2 12:41:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[147.11.176.192]) by smtp.gmail.com with ESMTPSA id t191sm36206889pgd.3.2022.01.04.19.09.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jan 2022 19:09:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N/ygyRMNJMWmW6pplUlmSEGaxLR4xXddaaBSAJ8IHoQ=; b=lAlXrvI6IMGsuuar9+ayPkm93nIyR8UwEPNO1yzVI+vbkB6iOi11phCjdJHt7x63w5 p659oRvusXA3SJ702M2Q75zbPRHjGgOj7Fd43qbQSO/jtCmaa1HdfrrKMZUAZ+Rz5ksg uv33Z8guToVNhJTyXKu3PBqSQ7qZ4o9fxJmMuFuKlgN1kuyml9a5YtVx9Ige92Iaxa0b 0oLsEWT6kZwRv40Nr33VbeZfflKcCRPnMwobJsHYEtBT4tGYogXRYPnkVrGTN5LV696V WB+m3Rz44icY0qbTN9J+iU1m8vNr5wYZNBHruU46j3hCWIt17/4p1CFX6gZSCsTtYOQj zoDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N/ygyRMNJMWmW6pplUlmSEGaxLR4xXddaaBSAJ8IHoQ=; b=J/5GHtGLBjU3oWfxcwFdCkK5KgEr/znYA2Lerbw92XqQ5VUxee2s7EMqKMQLwkKGz5 rBm+JYZE28GLKIpWV+YS/D+ygcy8vg39soODgrNeHhmMAuUL3RGIUegYpfHYTcJihx7i xHtITmPbGyG6q6RhUOW9l+eDs8AOAdKI+UeB9dVR/bWla2nqE+K4jmGyalfj953Y41yT 0ybAJF0ORpWHwg/YD73WVhGlEtYVRxdQe+TOmN+Uf2zkEgyBUOWZ1e1UAXpZm9G9LIGT 39OuS+Zf1oE+bbVGqBWBGrovBniE1DtXvFUomkVu8Z4Rz+rm40a2RGzjrBofli4jNSBD Xo8w== X-Gm-Message-State: AOAM532BL5bHG0hLXgI26M9RzwQclL0MOSrjXal/wFPhn5jf0y1//Rgz ULbZKrORk+rRwMKits0u/iHm+BLhbtyU3A== X-Google-Smtp-Source: ABdhPJxsWh1si0Dkg+eUY2pwgGi9coKiwYuWSOzU2OC51ut1K9SniCRH8tCILGAx6iZvYdhpKcGQ2Q== X-Received: by 2002:a17:90b:194b:: with SMTP id nk11mr1785896pjb.20.1641352145702; Tue, 04 Jan 2022 19:09:05 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RESEND PATCH v3 6/7] target/riscv: cpu: Enable native debug feature Date: Wed, 5 Jan 2022 11:08:43 +0800 Message-Id: <20220105030844.780642-7-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105030844.780642-1-bmeng.cn@gmail.com> References: <20220105030844.780642-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102d (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1641353382639100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng Turn on native debug feature by default for all CPUs. Signed-off-by: Bin Meng --- Changes in v3: - enable debug feature by default for all CPUs target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 17dcc3c14f..17444b458f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -644,7 +644,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), - DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false), + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), --=20 2.25.1 From nobody Thu May 2 12:41:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641353508885963.856643448269; Tue, 4 Jan 2022 19:31:48 -0800 (PST) Received: from localhost ([::1]:42028 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4x1f-0003re-Fy for importer@patchew.org; Tue, 04 Jan 2022 22:31:47 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60496) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4wfp-0007Xc-Tl; Tue, 04 Jan 2022 22:09:13 -0500 Received: from [2607:f8b0:4864:20::1031] (port=37735 helo=mail-pj1-x1031.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n4wfm-0001yr-IX; Tue, 04 Jan 2022 22:09:12 -0500 Received: by mail-pj1-x1031.google.com with SMTP id y16-20020a17090a6c9000b001b13ffaa625so1990196pjj.2; Tue, 04 Jan 2022 19:09:09 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-176-192.windriver.com. [147.11.176.192]) by smtp.gmail.com with ESMTPSA id t191sm36206889pgd.3.2022.01.04.19.09.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jan 2022 19:09:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=k03hqsrN3r2DAcpcEZo3Qmaha1XCoOaXcqqhAGM9cU0=; b=Tr9AjbeEaky53mDQSY0wD7+6h8s3i+xcQR7q9E3hepQL6Q7pL5tNXGKinC7KDbwgSI 0mKdLmmkpimmq84uOQwnbgjB43s0WLB26s6jyUZT0uCW/IGhVU78BHIATYbp2wxB1EaE jzHrZw8nS1zxg9dIdhLXsfFwV+nYxoPEdI7EjyNwkJObS76zDvr6LtqKNBtd0Sqy/QQo /hgrU4L2V75iaL9ueHy35RTTZC7Yd7ql6dM+pm2G7mdd8IpFzBSyFaqn+5l1krWba1t0 eKyeRVXGr6SrFoQ7E9XwvTyb1w825QdUpPi0ffYod94efzTxX2py4iF/ULxYJqL+LuuW biZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k03hqsrN3r2DAcpcEZo3Qmaha1XCoOaXcqqhAGM9cU0=; b=bRkcVEHlt5W+84u5a7jorcUxGmnaybNMAC0fdqHv7BP/n5tDCyE5k0aghupXFruRqN nncC7vMdcIDkbNlazsxloNlWlSPbZXMo8Mdlqk68rX4yTxfAS5BlK4bol5YG0DibWjjB J2bv4fdGvDP+ksIciiKRucAFJUg1sAiLoY5+iEFHQVtk79IMhTUT7NXXqeYgD/vrP262 QzYpetoYO7e/O/IhA+AVDcMHcxxZ0Nu/dzdwUqEfgaFljs+vpC2d+i22V7xjoPwKYfcO g8pjRSf+KL4u8ZN7f4KN8j/xX8r0u0DkbOt8bkZoFBWMJmhPNVirkRqR4/WoZAy12dpI fqgQ== X-Gm-Message-State: AOAM53069sYk69BbFnWevm/Q1uDB5fdZFj9pdY1N1EjHicXDuN8K7sFJ 3pByUI5Yxuo9ISe5BTfFe70= X-Google-Smtp-Source: ABdhPJwc3QNQFKCJX/Ztbmrulq67knl8h6bBIESHheRutsnwxXXBDjCGXdwjBU7Le1ciJjIvjVKxvg== X-Received: by 2002:a17:90b:4017:: with SMTP id ie23mr1702040pjb.109.1641352149224; Tue, 04 Jan 2022 19:09:09 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RESEND PATCH v3 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Date: Wed, 5 Jan 2022 11:08:44 +0800 Message-Id: <20220105030844.780642-8-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105030844.780642-1-bmeng.cn@gmail.com> References: <20220105030844.780642-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1031 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641353510833100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng This is now used by RISC-V as well. Update the comments. Signed-off-by: Bin Meng Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v1) include/hw/core/tcg-cpu-ops.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index e13898553a..f98671ff32 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -90,6 +90,7 @@ struct TCGCPUOps { /** * @debug_check_watchpoint: return true if the architectural * watchpoint whose address has matched should really fire, used by ARM + * and RISC-V */ bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); =20 --=20 2.25.1