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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id b65sm39371533pfg.209.2022.01.03.22.34.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jan 2022 22:34:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9QkAX41YPjiafULqwcCrPrnUTsqrpgoVb6FMBimVUQo=; b=HGgFE4gJ+Ce2PTk5ntpc6WJrMAUnDuVRmYcH2MSXFuyn/z6Qs7gDGLz2QKP8DVwpDc 7Nuk01IXGImpnTIjs2a8AaLHrbRvStAUiPeXJ6BJYuINEWZKOCGpgjOWBrGvXiYLnMhL W424ICqUImS6lsK392WdIuFacg0/dVRUUGUhyAaA+a9EvAtNSKoTtPOUCJ9/YAbZRuTr 6jmgbM99S8TtHOnDHVoVJvExlMDtIC8HaJ/EsH+9W7juwefRmuoAXpZa0Dxs33RtehfS SuFGwME+apbSJv6KmXevawiyqPV9eNpuaioBFVKM+k1rl2R8OK7ZHP85m0CHubeVi2L4 rTKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9QkAX41YPjiafULqwcCrPrnUTsqrpgoVb6FMBimVUQo=; b=twvn+j3PVDHdQX5xVbX3kJnSZXdxsFiB4d/wF++vO9wLFQeUqRqiznnTy0lRdTMZnI VxyzgNsjMKvo1mleOq1bLcmo/MkIz07SJO7rwlJCxcsvYKRqbP5mS0FbGvMC6Y1hhJTI sxBPHBfgD3IeQDUltlZAHAj++U0XWbxlOLbF522bSAxik7L1ydflCgtq6khnatPHXZxo ukUYsQjAtWyvFTwKhbJP2X2oyPiOKjz3CfhTuNKANCopLvVc2J8LJDvuwql835kPiYvp P2+NmEMBo9wza0mjl8waGoQo8+fbnbr1OmuWzCAJ8PFtav4cDQmw/QpMMdk59UdY+E69 FVKg== X-Gm-Message-State: AOAM532pKlE7YDkvyKxeSpc+3rDkqYhHyWlpWPBZnrjxG9TVy67hAgBP AVasLH/rbX30vdNMu/VJ8hG2VA== X-Google-Smtp-Source: ABdhPJxZ/HhcOQLolXgFraDLDSYTHlDHKUYUu+Wfu4mpgPcZhTz0eOq1KrTKuBX5dCnMcsHiJ6VU7A== X-Received: by 2002:a17:903:22c2:b0:148:fcc0:aae8 with SMTP id y2-20020a17090322c200b00148fcc0aae8mr48723131plg.148.1641278099495; Mon, 03 Jan 2022 22:34:59 -0800 (PST) From: Jim Shu To: Alistair.Francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com, frank.chang@sifive.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register Date: Tue, 4 Jan 2022 14:34:07 +0800 Message-Id: <20220104063408.658169-2-jim.shu@sifive.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104063408.658169-1-jim.shu@sifive.com> References: <20220104063408.658169-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=jim.shu@sifive.com; helo=mail-pj1-x102f.google.com X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis , Jim Shu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641278806582100001 Content-Type: text/plain; charset="utf-8" Real PDMA supports high 32-bit read/write memory access of 64-bit register. The following result is PDMA tested in U-Boot on Unmatched board: 1. Real PDMA allows high 32-bit read/write to 64-bit register. =3D> mw.l 0x3000000 0x0 <=3D Disclaim channel 0 =3D> mw.l 0x3000000 0x1 <=3D Claim channel 0 =3D> mw.l 0x3000010 0x80000000 <=3D Write low 32-bit NextDest= (NextDest =3D 0x280000000) =3D> mw.l 0x3000014 0x2 <=3D Write high 32-bit NextDest =3D> md.l 0x3000010 1 <=3D Dump low 32-bit NextDest 03000010: 80000000 =3D> md.l 0x3000014 1 <=3D Dump high 32-bit NextDest 03000014: 00000002 =3D> mw.l 0x3000018 0x80001000 <=3D Write low 32-bit NextSrc = (NextSrc =3D 0x280001000) =3D> mw.l 0x300001c 0x2 <=3D Write high 32-bit NextSrc =3D> md.l 0x3000018 1 <=3D Dump low 32-bit NextSrc 03000010: 80001000 =3D> md.l 0x300001c 1 <=3D Dump high 32-bit NextSrc 03000014: 00000002 2. PDMA transfer from 0x280001000 to 0x280000000 is OK. =3D> mw.q 0x3000008 0x4 <=3D NextBytes =3D 4 =3D> mw.l 0x3000004 0x22000000 <=3D wsize =3D rsize =3D 2 (2^= 2 =3D 4 bytes) =3D> mw.l 0x280000000 0x87654321 <=3D Fill test data to dst =3D> mw.l 0x280001000 0x12345678 <=3D Fill test data to src =3D> md.l 0x280000000 1; md.l 0x280001000 1 <=3D Dump src/dst memory conte= nts 280000000: 87654321 !Ce. 280001000: 12345678 xV4. =3D> md.l 0x3000000 8 <=3D Dump PDMA status 03000000: 00000001 22000000 00000004 00000000 ......."........ 03000010: 80000000 00000002 80001000 00000002 ................ =3D> mw.l 0x3000000 0x3 <=3D Set channel 0 run and cla= im bits =3D> md.l 0x3000000 8 <=3D Dump PDMA status 03000000: 40000001 22000000 00000004 00000000 ...@..."........ 03000010: 80000000 00000002 80001000 00000002 ................ =3D> md.l 0x280000000 1; md.l 0x280001000 1 <=3D Dump src/dst memory conte= nts 280000000: 12345678 xV4. 280001000: 12345678 xV4. Signed-off-by: Jim Shu Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/dma/sifive_pdma.c | 177 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 155 insertions(+), 22 deletions(-) diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c index 85fe34f5f3..f4df16449b 100644 --- a/hw/dma/sifive_pdma.c +++ b/hw/dma/sifive_pdma.c @@ -177,18 +177,44 @@ static inline void sifive_pdma_update_irq(SiFivePDMAS= tate *s, int ch) s->chan[ch].state =3D DMA_CHAN_STATE_IDLE; } =20 -static uint64_t sifive_pdma_read(void *opaque, hwaddr offset, unsigned siz= e) +static uint64_t sifive_pdma_readq(SiFivePDMAState *s, int ch, hwaddr offse= t) { - SiFivePDMAState *s =3D opaque; - int ch =3D SIFIVE_PDMA_CHAN_NO(offset); uint64_t val =3D 0; =20 - if (ch >=3D SIFIVE_PDMA_CHANS) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n", - __func__, ch); - return 0; + offset &=3D 0xfff; + switch (offset) { + case DMA_NEXT_BYTES: + val =3D s->chan[ch].next_bytes; + break; + case DMA_NEXT_DST: + val =3D s->chan[ch].next_dst; + break; + case DMA_NEXT_SRC: + val =3D s->chan[ch].next_src; + break; + case DMA_EXEC_BYTES: + val =3D s->chan[ch].exec_bytes; + break; + case DMA_EXEC_DST: + val =3D s->chan[ch].exec_dst; + break; + case DMA_EXEC_SRC: + val =3D s->chan[ch].exec_src; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unexpected 64-bit access to 0x%" HWADDR_PRIX "\= n", + __func__, offset); + break; } =20 + return val; +} + +static uint32_t sifive_pdma_readl(SiFivePDMAState *s, int ch, hwaddr offse= t) +{ + uint32_t val =3D 0; + offset &=3D 0xfff; switch (offset) { case DMA_CONTROL: @@ -198,28 +224,47 @@ static uint64_t sifive_pdma_read(void *opaque, hwaddr= offset, unsigned size) val =3D s->chan[ch].next_config; break; case DMA_NEXT_BYTES: - val =3D s->chan[ch].next_bytes; + val =3D extract64(s->chan[ch].next_bytes, 0, 32); + break; + case DMA_NEXT_BYTES + 4: + val =3D extract64(s->chan[ch].next_bytes, 32, 32); break; case DMA_NEXT_DST: - val =3D s->chan[ch].next_dst; + val =3D extract64(s->chan[ch].next_dst, 0, 32); + break; + case DMA_NEXT_DST + 4: + val =3D extract64(s->chan[ch].next_dst, 32, 32); break; case DMA_NEXT_SRC: - val =3D s->chan[ch].next_src; + val =3D extract64(s->chan[ch].next_src, 0, 32); + break; + case DMA_NEXT_SRC + 4: + val =3D extract64(s->chan[ch].next_src, 32, 32); break; case DMA_EXEC_CONFIG: val =3D s->chan[ch].exec_config; break; case DMA_EXEC_BYTES: - val =3D s->chan[ch].exec_bytes; + val =3D extract64(s->chan[ch].exec_bytes, 0, 32); + break; + case DMA_EXEC_BYTES + 4: + val =3D extract64(s->chan[ch].exec_bytes, 32, 32); break; case DMA_EXEC_DST: - val =3D s->chan[ch].exec_dst; + val =3D extract64(s->chan[ch].exec_dst, 0, 32); + break; + case DMA_EXEC_DST + 4: + val =3D extract64(s->chan[ch].exec_dst, 32, 32); break; case DMA_EXEC_SRC: - val =3D s->chan[ch].exec_src; + val =3D extract64(s->chan[ch].exec_src, 0, 32); + break; + case DMA_EXEC_SRC + 4: + val =3D extract64(s->chan[ch].exec_src, 32, 32); break; default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\= n", + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unexpected 32-bit access to 0x%" HWADDR_PRIX "\= n", __func__, offset); break; } @@ -227,19 +272,66 @@ static uint64_t sifive_pdma_read(void *opaque, hwaddr= offset, unsigned size) return val; } =20 -static void sifive_pdma_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) +static uint64_t sifive_pdma_read(void *opaque, hwaddr offset, unsigned siz= e) { SiFivePDMAState *s =3D opaque; int ch =3D SIFIVE_PDMA_CHAN_NO(offset); - bool claimed, run; + uint64_t val =3D 0; =20 if (ch >=3D SIFIVE_PDMA_CHANS) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n", __func__, ch); - return; + return 0; + } + + switch (size) { + case 8: + val =3D sifive_pdma_readq(s, ch, offset); + break; + case 4: + val =3D sifive_pdma_readl(s, ch, offset); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid read size %u to PDMA\n= ", + __func__, size); + return 0; } =20 + return val; +} + +static void sifive_pdma_writeq(SiFivePDMAState *s, int ch, + hwaddr offset, uint64_t value) +{ + offset &=3D 0xfff; + switch (offset) { + case DMA_NEXT_BYTES: + s->chan[ch].next_bytes =3D value; + break; + case DMA_NEXT_DST: + s->chan[ch].next_dst =3D value; + break; + case DMA_NEXT_SRC: + s->chan[ch].next_src =3D value; + break; + case DMA_EXEC_BYTES: + case DMA_EXEC_DST: + case DMA_EXEC_SRC: + /* these are read-only registers */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unexpected 64-bit access to 0x%" HWADDR_PRIX "\= n", + __func__, offset); + break; + } +} + +static void sifive_pdma_writel(SiFivePDMAState *s, int ch, + hwaddr offset, uint32_t value) +{ + bool claimed, run; + offset &=3D 0xfff; switch (offset) { case DMA_CONTROL: @@ -282,27 +374,68 @@ static void sifive_pdma_write(void *opaque, hwaddr of= fset, s->chan[ch].next_config =3D value; break; case DMA_NEXT_BYTES: - s->chan[ch].next_bytes =3D value; + s->chan[ch].next_bytes =3D + deposit64(s->chan[ch].next_bytes, 0, 32, value); + break; + case DMA_NEXT_BYTES + 4: + s->chan[ch].next_bytes =3D + deposit64(s->chan[ch].next_bytes, 32, 32, value); break; case DMA_NEXT_DST: - s->chan[ch].next_dst =3D value; + s->chan[ch].next_dst =3D deposit64(s->chan[ch].next_dst, 0, 32, va= lue); + break; + case DMA_NEXT_DST + 4: + s->chan[ch].next_dst =3D deposit64(s->chan[ch].next_dst, 32, 32, v= alue); break; case DMA_NEXT_SRC: - s->chan[ch].next_src =3D value; + s->chan[ch].next_src =3D deposit64(s->chan[ch].next_src, 0, 32, va= lue); + break; + case DMA_NEXT_SRC + 4: + s->chan[ch].next_src =3D deposit64(s->chan[ch].next_src, 32, 32, v= alue); break; case DMA_EXEC_CONFIG: case DMA_EXEC_BYTES: + case DMA_EXEC_BYTES + 4: case DMA_EXEC_DST: + case DMA_EXEC_DST + 4: case DMA_EXEC_SRC: + case DMA_EXEC_SRC + 4: /* these are read-only registers */ break; default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\= n", + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unexpected 32-bit access to 0x%" HWADDR_PRIX "\= n", __func__, offset); break; } } =20 +static void sifive_pdma_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + SiFivePDMAState *s =3D opaque; + int ch =3D SIFIVE_PDMA_CHAN_NO(offset); + + if (ch >=3D SIFIVE_PDMA_CHANS) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n", + __func__, ch); + return; + } + + switch (size) { + case 8: + sifive_pdma_writeq(s, ch, offset, value); + break; + case 4: + sifive_pdma_writel(s, ch, offset, (uint32_t) value); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid write size %u to PDMA\= n", + __func__, size); + break; + } +} + static const MemoryRegionOps sifive_pdma_ops =3D { .read =3D sifive_pdma_read, .write =3D sifive_pdma_write, --=20 2.25.1 From nobody Wed May 1 11:33:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641278779176598.5024351225526; Mon, 3 Jan 2022 22:46:19 -0800 (PST) Received: from localhost ([::1]:37304 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4daC-0002cY-OM for importer@patchew.org; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id b65sm39371533pfg.209.2022.01.03.22.35.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jan 2022 22:35:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gkygk7HFkDRQqBR7gPramWeqcVEw4UkCyEe2l45+d4s=; b=SnH5pxHJLncjnBkK3NfPVznNU4C+DEBPjgbHB+QzQunwAU/taKFwmHmyapddJfprF3 mifc6rUWkElhtQQwFFkB6cLQAoWsjUrFydTLP8h2jzVmMB6ijTpCz8Wu3t8dhkihvVGX jGI81w4qd+jHMv058V9JbQl1KzjJOpL9udWT0eciQ14qSn3uxXdvwS2fXX0FB5FuFx+E XslQcaV+5afg0rBXZVTHsWvpbLN3LPjNJ12obKwjYEA4aPOk6cVqORz8kmGWSfCrRKsu SKUzFlUj4Rba5wf2w+IyeK8gL2L9SmXC3zl4f+HTnpadhUxwgGQl5sWykpcAoBL9Vpio 35VA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gkygk7HFkDRQqBR7gPramWeqcVEw4UkCyEe2l45+d4s=; b=ldiFdXJR5XEpNsUOL+qchRLtuyXRL0LNgNlmDUX63bTBxro56dcCAtT6DPWF3u/UHo Pc4ub+Q1IFD+YkeDPPOUgbYCW9+bnOCOxlRqBkoOAwhsbMXmlsZjfNwlQ7oG1wVvKOTq cxuWddFQl9/6qkfosakGvZLeucAq5XcvBBXq6aU6bQ1Ram5kiwBdd9ZXTHPzfHjpr7H0 2ic1ufqgwEXor+oZwmjGb7SAxKqvICoE3VXhxj21udr4fPsmu9ft8vRQPM021SgzYlFV zFr6dpc81XXo60mEYsLfuCG3ouqImR2bEgQPdPoSKI4zN95xdwHU7aVlzMlG3rsg0Fdb x17Q== X-Gm-Message-State: AOAM5312/8hl08zrYlpy+7X99+4BqqbP1KILqS3bm0SSP1H7RgC0C192 tb1iGMBriDZOzD5PeVRX8qOMeg== X-Google-Smtp-Source: ABdhPJzmMGZPbbVIqmegnGuFfEtplZk88t1NsnxnAEqASyucQ+PWC0Z192QXm2HufXx3lgq6hHG6Ag== X-Received: by 2002:a17:902:a584:b0:143:c2e3:c4 with SMTP id az4-20020a170902a58400b00143c2e300c4mr48258648plb.69.1641278106711; Mon, 03 Jan 2022 22:35:06 -0800 (PST) From: Jim Shu To: Alistair.Francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com, frank.chang@sifive.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers Date: Tue, 4 Jan 2022 14:34:08 +0800 Message-Id: <20220104063408.658169-3-jim.shu@sifive.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104063408.658169-1-jim.shu@sifive.com> References: <20220104063408.658169-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62c (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=jim.shu@sifive.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jim Shu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641278780615100001 It's obvious that PDMA supports 64-bit access of 64-bit registers, and in previous commit, we confirm that PDMA supports 32-bit access of both 32/64-bit registers. Thus, we configure 32/64-bit memory access of PDMA registers as valid in general. Signed-off-by: Jim Shu Reviewed-by: Frank Chang Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/dma/sifive_pdma.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c index f4df16449b..1dd88f3479 100644 --- a/hw/dma/sifive_pdma.c +++ b/hw/dma/sifive_pdma.c @@ -444,6 +444,10 @@ static const MemoryRegionOps sifive_pdma_ops =3D { .impl =3D { .min_access_size =3D 4, .max_access_size =3D 8, + }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 8, } }; =20 --=20 2.25.1