From nobody Sun May 5 05:55:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1641262777; cv=none; d=zohomail.com; s=zohoarc; b=BRFw9XOg8Iu8MGHmcuXJtXIMa9qr5BgeSFhJUhIVO6TNSexdYJsrjh/NFYKIb2uk8P33QeZi4aMkO96HbbMAlFAFwhfTQ9pcH4JPlwrnQJFQ2zkeGMz66aaFREuJ5SFeZoMDlxfa47ZRaA+iWv7klVR8sXk4UxeWddBOvHX99qg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1641262777; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xDlNcMPX+4x4RTjp0DsPf/CfOh4YFwKmpEmxN1K7ZOw=; b=nMqnM5MvTeDakcozcIH3P4ysSIltQqZMA8ctMjW1USO8+Xd09nobQjI3Hp0WgsBSI/QEmMbIRA6YXMPtP3w9T5PbFeRquoneyjBwCFMVq/6O+Pm+g1xs6rLv3zt8pLUj4bRUyaVazRj4+nyN0/TX6oHw7fNC7WjulpIsY40w0r4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641262777515465.32763983446296; Mon, 3 Jan 2022 18:19:37 -0800 (PST) Received: from localhost ([::1]:54720 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4ZQG-0000Ui-G0 for importer@patchew.org; Mon, 03 Jan 2022 21:19:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51054) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4ZMa-0002fy-RQ for qemu-devel@nongnu.org; Mon, 03 Jan 2022 21:15:48 -0500 Received: from [2607:f8b0:4864:20::1031] (port=38699 helo=mail-pj1-x1031.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n4ZMY-00089j-3f for qemu-devel@nongnu.org; Mon, 03 Jan 2022 21:15:48 -0500 Received: by mail-pj1-x1031.google.com with SMTP id l10-20020a17090a384a00b001b22190e075so34035244pjf.3 for ; Mon, 03 Jan 2022 18:15:45 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id b4sm37395501pjm.17.2022.01.03.18.15.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jan 2022 18:15:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xDlNcMPX+4x4RTjp0DsPf/CfOh4YFwKmpEmxN1K7ZOw=; b=JoUYtQsgRQ3JBiB5gOVxbQjw4g6JhUDux5nyVYKsyi5G1n4kIgNL+ADtwL2ABf9GIf 7wh5Pjlsj1849q1RqrW+0pUuSaztaHYWnDNHIQGlRz+ZAhwL4doYcefAYhIbe4LbFwjx 2lN5XhZ1g+cKt6V+f7bImSQOFoeQlR1/doP0UwRPJ5DnYTJ1C/WfbyrDHUt4kD/wO67k YP+H4gvkTvQnI7hj/5vbP8+0C4sh64l6Ub3j3Iz2AN9E7vKm/PEL521MI7cxweBnlriQ 36p71sQUMwyU+HquWiILzzFDqyuwaFFNefNGmQAQoLKpM9SFkYEGE6sAFWfJ3pvkTkiZ EH+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xDlNcMPX+4x4RTjp0DsPf/CfOh4YFwKmpEmxN1K7ZOw=; b=CMDkZLaTuSrxo40NnNs9xRNVNjxR3FfS7lK65oEJdksgoJgacRyp0ipHUsoLXQPPOG OuAdSX9e5DUYozTcr8gRu1/KyOcbplmZ9av8gMaHqP6+KY7qK8qdaCSy3BzaybwR1dbC tqgqFrIYNJL+rte/9H4AHtyjvcbbaYh8QUvTNJayKk4AAYddJEIqdgMMJbMgz+MSV8ri zo5x96Kcm1JOCPZv1TUx18mrvKHs5ACJUCPjscgf6fPLAyh3A059nly0WpjX71oDHJfB oLtMKo1AsSxIlsHrJGQbdd/qXZQgpwozW53bG1uVS0nW6bJk+U8eWMOJ1h6HdSY5ipSe 4dog== X-Gm-Message-State: AOAM530Azp1wwn67UXrWxUqfuylHu68wA8hacj4bwM4IAR9RasUQ8m+y BZtXzDUqqSQhTxfVsTcwCYl5l98syXEMWQ== X-Google-Smtp-Source: ABdhPJwvgXKjTlCehK5g31WSog5JdPS1kGETTx3oEpcUjFCxeBSccPrLKRu9iCd3AKszwhOwNXphPw== X-Received: by 2002:a17:90a:bc92:: with SMTP id x18mr58761662pjr.130.1641262544815; Mon, 03 Jan 2022 18:15:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 1/7] tcg/i386: Support raising sigbus for user-only Date: Mon, 3 Jan 2022 18:15:37 -0800 Message-Id: <20220104021543.396571-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104021543.396571-1-richard.henderson@linaro.org> References: <20220104021543.396571-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1031 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1641262779810100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 - tcg/i386/tcg-target.c.inc | 103 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 98 insertions(+), 7 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b00a6da293..3b2c9437a0 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -232,9 +232,7 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, =20 #define TCG_TARGET_HAS_MEMORY_BSWAP have_movbe =20 -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS =20 #endif diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 84b109bb84..e073868d8f 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -22,6 +22,7 @@ * THE SOFTWARE. */ =20 +#include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" =20 #ifdef CONFIG_DEBUG_TCG @@ -421,8 +422,9 @@ static bool tcg_target_const_match(int64_t val, TCGType= type, int ct) #define OPC_VZEROUPPER (0x77 | P_EXT) #define OPC_XCHG_ax_r32 (0x90) =20 -#define OPC_GRP3_Ev (0xf7) -#define OPC_GRP5 (0xff) +#define OPC_GRP3_Eb (0xf6) +#define OPC_GRP3_Ev (0xf7) +#define OPC_GRP5 (0xff) #define OPC_GRP14 (0x73 | P_EXT | P_DATA16) =20 /* Group 1 opcode extensions for 0x80-0x83. @@ -444,6 +446,7 @@ static bool tcg_target_const_match(int64_t val, TCGType= type, int ct) #define SHIFT_SAR 7 =20 /* Group 3 opcode extensions for 0xf6, 0xf7. To be used with OPC_GRP3. */ +#define EXT3_TESTi 0 #define EXT3_NOT 2 #define EXT3_NEG 3 #define EXT3_MUL 4 @@ -1606,8 +1609,6 @@ static void tcg_out_nopn(TCGContext *s, int n) } =20 #if defined(CONFIG_SOFTMMU) -#include "../tcg-ldst.c.inc" - /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ @@ -1916,7 +1917,84 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); return true; } -#elif TCG_TARGET_REG_BITS =3D=3D 32 +#else + +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, + TCGReg addrhi, unsigned a_bits) +{ + unsigned a_mask =3D (1 << a_bits) - 1; + TCGLabelQemuLdst *label; + + /* + * We are expecting a_bits to max out at 7, so we can usually use test= b. + * For i686, we have to use testl for %esi/%edi. + */ + if (a_mask <=3D 0xff && (TCG_TARGET_REG_BITS =3D=3D 64 || addrlo < 4))= { + tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, addrlo); + tcg_out8(s, a_mask); + } else { + tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_TESTi, addrlo); + tcg_out32(s, a_mask); + } + + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + + label =3D new_ldst_label(s); + label->is_ld =3D is_ld; + label->addrlo_reg =3D addrlo; + label->addrhi_reg =3D addrhi; + label->raddr =3D tcg_splitwx_to_rx(s->code_ptr + 4); + label->label_ptr[0] =3D s->code_ptr; + + s->code_ptr +=3D 4; +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + /* resolve label address */ + tcg_patch32(l->label_ptr[0], s->code_ptr - l->label_ptr[0] - 4); + + if (TCG_TARGET_REG_BITS =3D=3D 32) { + int ofs =3D 0; + + tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); + ofs +=3D 4; + + tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); + ofs +=3D 4; + if (TARGET_LONG_BITS =3D=3D 64) { + tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); + ofs +=3D 4; + } + + tcg_out_pushi(s, (uintptr_t)l->raddr); + } else { + tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], + l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); + + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, (uintptr_t)l->raddr); + tcg_out_push(s, TCG_REG_RAX); + } + + /* "Tail call" to the helper, with the return address back inline. */ + tcg_out_jmp(s, (const void *)(l->is_ld ? helper_unaligned_ld + : helper_unaligned_st)); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +#if TCG_TARGET_REG_BITS =3D=3D 32 # define x86_guest_base_seg 0 # define x86_guest_base_index -1 # define x86_guest_base_offset guest_base @@ -1950,6 +2028,7 @@ static inline int setup_guest_base_seg(void) return 0; } # endif +#endif #endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, @@ -2059,6 +2138,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) #if defined(CONFIG_SOFTMMU) int mem_index; tcg_insn_unit *label_ptr[2]; +#else + unsigned a_bits; #endif =20 datalo =3D *args++; @@ -2081,6 +2162,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is64) add_qemu_ldst_label(s, true, is64, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else + a_bits =3D get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); + } + tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, x86_guest_base_offset, x86_guest_base_seg, is64, opc); @@ -2148,6 +2234,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) #if defined(CONFIG_SOFTMMU) int mem_index; tcg_insn_unit *label_ptr[2]; +#else + unsigned a_bits; #endif =20 datalo =3D *args++; @@ -2170,6 +2258,11 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is64) add_qemu_ldst_label(s, false, is64, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else + a_bits =3D get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); + } + tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index, x86_guest_base_offset, x86_guest_base_seg, opc); #endif --=20 2.25.1 From nobody Sun May 5 05:55:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1641262665; cv=none; d=zohomail.com; s=zohoarc; b=gqyTHoyKioccnmnmhHwis/roo37tLViCmC16xinwTijZXG4JhqGEq8vrOA4cPk53o5fXFZgeFlnZphLA3T7L2bC4CDefhiWnYPczGV3iQk072yANrqo47KLd3h68oGfbV4XGJXYtGLlRNT5IqQmLUXX5VsGdEme8g3u/gTlg4j0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1641262665; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AEDrLdND+QdiSTD7gFvQs8s8wQuCqaZx5PiFrbiHmIQ=; b=b3Dv3tC5eRdFHTq8yQ0COlxK2591p245Fl2LS5kWG7/daolyB+HNIsuhRKBTlPixCAT1xSoOilAe6tZrzowlqM/KXfbWZqIGVjndiIcqrRmZddwPDmUVrc/PmS4Kx91jNGJMnja5Z4hJ4bXZ1zz6c2daBjfV+yMAN0HTEJqMhnI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164126266574471.80830895095778; Mon, 3 Jan 2022 18:17:45 -0800 (PST) Received: from localhost ([::1]:49198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4ZOS-0005Fp-PY for importer@patchew.org; Mon, 03 Jan 2022 21:17:44 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51062) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4ZMa-0002gU-W3 for qemu-devel@nongnu.org; Mon, 03 Jan 2022 21:15:49 -0500 Received: from [2607:f8b0:4864:20::102c] (port=42679 helo=mail-pj1-x102c.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n4ZMY-00089q-TI for qemu-devel@nongnu.org; Mon, 03 Jan 2022 21:15:48 -0500 Received: by mail-pj1-x102c.google.com with SMTP id lr15-20020a17090b4b8f00b001b19671cbebso1549383pjb.1 for ; Mon, 03 Jan 2022 18:15:46 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id b4sm37395501pjm.17.2022.01.03.18.15.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jan 2022 18:15:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AEDrLdND+QdiSTD7gFvQs8s8wQuCqaZx5PiFrbiHmIQ=; b=jkaXVIemgua2U4FcaQTU71wOy47KplMqSsG/mkLymQCH83gQGxnef2e4FIMRzMioQn 249gvniOGC2HoZYC5vRNW/UlzBcBMHDNEZxWHguEwn2tlel74sQ+80AY6Obyvk7SU9+r nhsuPPIdQ9IO/Fdh5xrBeSrfoUYL05kEE1uF7Y7y7nJCSZhNwxi7oXsKQ20I7ffFB8N4 vWkzNmoQ4CV3mOfjPet7+MNpue0BZN/4tzgOzuaa/C+ioZnSQc1xkQKGk4o0U1kqWEnj lJsOPMkAccwuXdRF1sr9DQP/oWqyoaI4DfJtyfKogRQuHefCe10lAckiz7FJc6Xrffhr OiCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AEDrLdND+QdiSTD7gFvQs8s8wQuCqaZx5PiFrbiHmIQ=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1641262666791100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/aarch64/tcg-target.h | 2 - tcg/aarch64/tcg-target.c.inc | 91 +++++++++++++++++++++++++++++------- 2 files changed, 74 insertions(+), 19 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 7a93ac8023..876af589ce 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -151,9 +151,7 @@ typedef enum { =20 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS =20 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 5edca8d44d..1f205f90b2 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -10,6 +10,7 @@ * See the COPYING file in the top-level directory for details. */ =20 +#include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" #include "qemu/bitops.h" =20 @@ -443,6 +444,7 @@ typedef enum { I3404_ANDI =3D 0x12000000, I3404_ORRI =3D 0x32000000, I3404_EORI =3D 0x52000000, + I3404_ANDSI =3D 0x72000000, =20 /* Move wide immediate instructions. */ I3405_MOVN =3D 0x12800000, @@ -1328,8 +1330,9 @@ static void tcg_out_goto_long(TCGContext *s, const tc= g_insn_unit *target) if (offset =3D=3D sextract64(offset, 0, 26)) { tcg_out_insn(s, 3206, B, offset); } else { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target); - tcg_out_insn(s, 3207, BR, TCG_REG_TMP); + /* Choose X9 as a call-clobbered non-LR temporary. */ + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X9, (intptr_t)target); + tcg_out_insn(s, 3207, BR, TCG_REG_X9); } } =20 @@ -1541,9 +1544,14 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext,= TCGReg d, } } =20 -#ifdef CONFIG_SOFTMMU -#include "../tcg-ldst.c.inc" +static void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target) +{ + ptrdiff_t offset =3D tcg_pcrel_diff(s, target); + tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 21)); + tcg_out_insn(s, 3406, ADR, rd, offset); +} =20 +#ifdef CONFIG_SOFTMMU /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * MemOpIdx oi, uintptr_t ra) */ @@ -1577,13 +1585,6 @@ static void * const qemu_st_helpers[MO_SIZE + 1] =3D= { #endif }; =20 -static inline void tcg_out_adr(TCGContext *s, TCGReg rd, const void *targe= t) -{ - ptrdiff_t offset =3D tcg_pcrel_diff(s, target); - tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 21)); - tcg_out_insn(s, 3406, ADR, rd, offset); -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { MemOpIdx oi =3D lb->oi; @@ -1714,15 +1715,58 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg = addr_reg, MemOp opc, tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); } =20 +#else +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_= reg, + unsigned a_bits) +{ + unsigned a_mask =3D (1 << a_bits) - 1; + TCGLabelQemuLdst *label =3D new_ldst_label(s); + + label->is_ld =3D is_ld; + label->addrlo_reg =3D addr_reg; + + /* tst addr, #mask */ + tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask); + + label->label_ptr[0] =3D s->code_ptr; + + /* b.ne slow_path */ + tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); + + label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + if (!reloc_pc19(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { + return false; + } + + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_X1, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); + + /* "Tail call" to the helper, with the return address back inline. */ + tcg_out_adr(s, TCG_REG_LR, l->raddr); + tcg_out_goto_long(s, (const void *)(l->is_ld ? helper_unaligned_ld + : helper_unaligned_st)); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} #endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, TCGReg data_r, TCGReg addr_r, TCGType otype, TCGReg off_r) { - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); - switch (memop & MO_SSIZE) { case MO_UB: tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r); @@ -1756,9 +1800,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Mem= Op memop, TCGReg data_r, TCGReg addr_r, TCGType otype, TCGReg off_r) { - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); - switch (memop & MO_SIZE) { case MO_8: tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r); @@ -1782,6 +1823,10 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg da= ta_reg, TCGReg addr_reg, { MemOp memop =3D get_memop(oi); const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + + /* Byte swapping is left to middle-end expansion. */ + tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); + #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; @@ -1792,6 +1837,10 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg da= ta_reg, TCGReg addr_reg, add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ + unsigned a_bits =3D get_alignment_bits(memop); + if (a_bits) { + tcg_out_test_alignment(s, true, addr_reg, a_bits); + } if (USE_GUEST_BASE) { tcg_out_qemu_ld_direct(s, memop, ext, data_reg, TCG_REG_GUEST_BASE, otype, addr_reg); @@ -1807,6 +1856,10 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= ta_reg, TCGReg addr_reg, { MemOp memop =3D get_memop(oi); const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + + /* Byte swapping is left to middle-end expansion. */ + tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); + #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; @@ -1817,6 +1870,10 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= ta_reg, TCGReg addr_reg, add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)=3D=3D MO_64, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ + unsigned a_bits =3D get_alignment_bits(memop); + if (a_bits) { + tcg_out_test_alignment(s, false, addr_reg, a_bits); + } if (USE_GUEST_BASE) { tcg_out_qemu_st_direct(s, memop, data_reg, TCG_REG_GUEST_BASE, otype, addr_reg); --=20 2.25.1 From nobody Sun May 5 05:55:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1641262761; cv=none; d=zohomail.com; s=zohoarc; b=ATh1b+w5b90yVR9kL6AfY7aC1xuSg4PKJEpvQzcBKVxVb80HeEjGviRsFl24fryFlb0gURdloufE6Wr0CbFOKabtAR3aNKWv0j7z3/LYqUllj0HFYiVQ+s79T/5zjMgKECIVPxDIMzaJZoqVwfN7Zci7IBbj4L6eEGwQzU5yWtE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1641262761; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=z9ajubKXxmD3iBvNRXK8ngdOfUUHM9YOJvnd1B/bzEU=; b=mbh8uB3QpoCCWpKrS/c+Km+3+fzmQb2YaHYsk9Bs1Xk2mBJDpzr+XSDXOrdClh6cuTo9SSqiQzKu3lGXoHION7IWUE++9cg3EzNv/4b50x6fyfXz8QzLDRZtd2PtRVbaL13W3pT6rR6qKrRCIjlunxHNRKrZHVMz4CJNr7+rYic= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641262761556774.4125666031412; Mon, 3 Jan 2022 18:19:21 -0800 (PST) Received: from localhost ([::1]:53694 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4ZQ0-0008FE-Js for importer@patchew.org; Mon, 03 Jan 2022 21:19:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51070) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4ZMb-0002hA-93 for qemu-devel@nongnu.org; Mon, 03 Jan 2022 21:15:49 -0500 Received: from [2607:f8b0:4864:20::535] (port=37733 helo=mail-pg1-x535.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n4ZMZ-00089u-FA for qemu-devel@nongnu.org; Mon, 03 Jan 2022 21:15:48 -0500 Received: by mail-pg1-x535.google.com with SMTP id x194so8224532pgx.4 for ; Mon, 03 Jan 2022 18:15:47 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. [174.21.75.75]) by smtp.gmail.com with ESMTPSA id b4sm37395501pjm.17.2022.01.03.18.15.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jan 2022 18:15:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z9ajubKXxmD3iBvNRXK8ngdOfUUHM9YOJvnd1B/bzEU=; b=T3IbVifRixhABYpIPfroB06y6d95fuWbeX6kFejyyUxZUCrJ49DXyUunLaAyT/alr/ VBNgQM5vyZuSZYqwBF0xNBL2TcO/JOzBWROFwmjpIjH2+m3jkfvpS/WUlm61KOua0UxB Or6ILQVYlqi2JhrQ9jnLr69FH00rnVCXa/nsOHMJUbJK4jlmyUKL3wWNZe/h7M/UE6Lx tYiX/q47ZrHC3r7739J7dOQb1yHg1cfw+Us6z6B85xVtVkv6zWKfUD26c0nOvVSvynZ+ EA0YZ4fFyaSBgfajpO1AEwWLC+81NiPmjMcm2gxYKvLyn39GFIe2FSKp4Vnu1hzQTse7 moYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z9ajubKXxmD3iBvNRXK8ngdOfUUHM9YOJvnd1B/bzEU=; b=qq9kx0ItAm8BApmoTqMo+ensK5eNqFLCgTrk5LY/XTxt2jnD2SxGnxBAz3vD8m7X3/ Fp7GjYeIgOsMGoGnoTeCOZG9QdnH7f9I44aZrK+rTXp172Lqu/KKQQ8hmsf3cCrjHin2 ir39JIAOEko5uiykLIxIIodZn7g2WD5d6qScRFT2e4SJZHybt6vmK43829+/3gS5XlqT LNOMnHF8qk2GBbMMsxp3Vs/jS+notzuqyJXjBp4bFIZ8Pl1KOABxdsvpTaUqdfDdyOPz eVTk3nGbT0KUfVQXLjDIRwkjNG7zypKzCuYCSC21c6GsHxY23P3/JA0tRJ57EgsyXJCs ga/w== X-Gm-Message-State: AOAM532Vvsj6k8aAJm4MezyQxVc/cF4I9WybWh0xcrR/kzFbKKD4qGze t+jLhsyRPEJ5c+P8w8GICCE5tTxg7eQ+xg== X-Google-Smtp-Source: ABdhPJw35fYZihOkk0NzCLfgpA4yBiJTM7hMO7bQRcHHDxD3SJHi91fX61l+AMKc58D1veJAy05gfQ== X-Received: by 2002:a63:751b:: with SMTP id q27mr42547961pgc.184.1641262546092; Mon, 03 Jan 2022 18:15:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 3/7] tcg/ppc: Support raising sigbus for user-only Date: Mon, 3 Jan 2022 18:15:39 -0800 Message-Id: <20220104021543.396571-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104021543.396571-1-richard.henderson@linaro.org> References: <20220104021543.396571-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::535 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1641262762944100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 2 - tcg/ppc/tcg-target.c.inc | 98 ++++++++++++++++++++++++++++++++++++---- 2 files changed, 90 insertions(+), 10 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 0943192cde..c775c97b61 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -182,9 +182,7 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS =20 #endif diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 3e4ca2be88..8a117e0665 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -24,6 +24,7 @@ =20 #include "elf.h" #include "../tcg-pool.c.inc" +#include "../tcg-ldst.c.inc" =20 /* * Standardize on the _CALL_FOO symbols used by GCC: @@ -1881,7 +1882,8 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintp= tr_t jmp_rx, } } =20 -static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) +static void tcg_out_call_int(TCGContext *s, int lk, + const tcg_insn_unit *target) { #ifdef _CALL_AIX /* Look through the descriptor. If the branch is in range, and we @@ -1892,7 +1894,7 @@ static void tcg_out_call(TCGContext *s, const tcg_ins= n_unit *target) =20 if (in_range_b(diff) && toc =3D=3D (uint32_t)toc) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc); - tcg_out_b(s, LK, tgt); + tcg_out_b(s, lk, tgt); } else { /* Fold the low bits of the constant into the addresses below. */ intptr_t arg =3D (intptr_t)target; @@ -1907,7 +1909,7 @@ static void tcg_out_call(TCGContext *s, const tcg_ins= n_unit *target) tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs); tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP); - tcg_out32(s, BCCTR | BO_ALWAYS | LK); + tcg_out32(s, BCCTR | BO_ALWAYS | lk); } #elif defined(_CALL_ELF) && _CALL_ELF =3D=3D 2 intptr_t diff; @@ -1921,16 +1923,21 @@ static void tcg_out_call(TCGContext *s, const tcg_i= nsn_unit *target) =20 diff =3D tcg_pcrel_diff(s, target); if (in_range_b(diff)) { - tcg_out_b(s, LK, target); + tcg_out_b(s, lk, target); } else { tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR); - tcg_out32(s, BCCTR | BO_ALWAYS | LK); + tcg_out32(s, BCCTR | BO_ALWAYS | lk); } #else - tcg_out_b(s, LK, target); + tcg_out_b(s, lk, target); #endif } =20 +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) +{ + tcg_out_call_int(s, LK, target); +} + static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_BSWAP) + 1] =3D { [MO_UB] =3D LBZX, [MO_UW] =3D LHZX, @@ -1960,8 +1967,6 @@ static const uint32_t qemu_exts_opc[4] =3D { }; =20 #if defined (CONFIG_SOFTMMU) -#include "../tcg-ldst.c.inc" - /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ @@ -2227,6 +2232,71 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) tcg_out_b(s, 0, lb->raddr); return true; } +#else + +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, + TCGReg addrhi, unsigned a_bits) +{ + unsigned a_mask =3D (1 << a_bits) - 1; + TCGLabelQemuLdst *label =3D new_ldst_label(s); + + label->is_ld =3D is_ld; + label->addrlo_reg =3D addrlo; + label->addrhi_reg =3D addrhi; + + /* We are expecting a_bits to max out at 7, much lower than ANDI. */ + tcg_debug_assert(a_bits < 16); + tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, a_mask)); + + label->label_ptr[0] =3D s->code_ptr; + tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); + + label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + if (!reloc_pc14(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { + return false; + } + + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + TCGReg arg =3D TCG_REG_R4; +#ifdef TCG_TARGET_CALL_ALIGN_ARGS + arg |=3D 1; +#endif + if (l->addrlo_reg !=3D arg) { + tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg); + tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg); + } else if (l->addrhi_reg !=3D arg + 1) { + tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg); + } else { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R0, arg); + tcg_out_mov(s, TCG_TYPE_I32, arg, arg + 1); + tcg_out_mov(s, TCG_TYPE_I32, arg + 1, TCG_REG_R0); + } + } else { + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R4, l->addrlo_reg); + } + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, TCG_AREG0); + + /* "Tail call" to the helper, with the return address back inline. */ + tcg_out_call_int(s, 0, (const void *)(l->is_ld ? helper_unaligned_ld + : helper_unaligned_st)); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + #endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) @@ -2238,6 +2308,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) #ifdef CONFIG_SOFTMMU int mem_index; tcg_insn_unit *label_ptr; +#else + unsigned a_bits; #endif =20 datalo =3D *args++; @@ -2258,6 +2330,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is_64) =20 rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ + a_bits =3D get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); + } rbase =3D guest_base ? TCG_GUEST_BASE_REG : 0; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); @@ -2313,6 +2389,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) #ifdef CONFIG_SOFTMMU int mem_index; tcg_insn_unit *label_ptr; +#else + unsigned a_bits; #endif =20 datalo =3D *args++; @@ -2333,6 +2411,10 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is_64) =20 rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ + a_bits =3D get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); + } rbase =3D guest_base ? TCG_GUEST_BASE_REG : 0; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); --=20 2.25.1 From nobody Sun May 5 05:55:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1641262880; cv=none; d=zohomail.com; s=zohoarc; b=OweEeq5nLezytsZJ8UB1msDdqxJx7yPoTmpdTFebny2BqiFa/JWDlOZIIC3XY+LI9k/iQyqqcr30L5IXTiKdmrLWAFASyx8vmUtJajspmhELGit/52YxUa1QrnibfOBXgj35ALn9B5pwZJfPmRh8zjxXKczcY/IL5wlVKbP7Xj4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1641262880; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DLEdjZy+09uGaMjE1uPY2LFNBR2LKIkdI9ZG+WGq/kQ=; b=nNNXJC/MJsM7JM0PV6Vl6P/CXFITxxcV1UAKyiFEjH76eKwi7k5Zj92MrfiQMrkSTddjveqwov1tblhCKKko3AVtjqr52zWqysiKsOD252owIbHZDxkXNQwLJHy0o5ebqMfz0gQOZ07RzUdL1CACDvIo9x7FMn+b4OtNC1kTxzU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641262880340661.879645751412; Mon, 3 Jan 2022 18:21:20 -0800 (PST) Received: from localhost ([::1]:58070 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4ZRv-0002oW-Aa for importer@patchew.org; Mon, 03 Jan 2022 21:21:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4ZMd-0002mC-C6 for qemu-devel@nongnu.org; Mon, 03 Jan 2022 21:15:51 -0500 Received: from [2607:f8b0:4864:20::636] (port=38420 helo=mail-pl1-x636.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n4ZMZ-0008A1-SG for qemu-devel@nongnu.org; Mon, 03 Jan 2022 21:15:51 -0500 Received: by mail-pl1-x636.google.com with SMTP id c3so12824298pls.5 for ; Mon, 03 Jan 2022 18:15:47 -0800 (PST) Received: from localhost.localdomain (174-21-75-75.tukw.qwest.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1641262881462100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 2 -- tcg/riscv/tcg-target.c.inc | 63 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 61 insertions(+), 4 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index ef78b99e98..11c9b3e4f4 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -165,9 +165,7 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); =20 #define TCG_TARGET_DEFAULT_MO (0) =20 -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 0 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 9b13a46fb4..49e84cbe13 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -27,6 +27,7 @@ * THE SOFTWARE. */ =20 +#include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" =20 #ifdef CONFIG_DEBUG_TCG @@ -847,8 +848,6 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) */ =20 #if defined(CONFIG_SOFTMMU) -#include "../tcg-ldst.c.inc" - /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * MemOpIdx oi, uintptr_t ra) */ @@ -1053,6 +1052,54 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) tcg_out_goto(s, l->raddr); return true; } +#else + +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_= reg, + unsigned a_bits) +{ + unsigned a_mask =3D (1 << a_bits) - 1; + TCGLabelQemuLdst *l =3D new_ldst_label(s); + + l->is_ld =3D is_ld; + l->addrlo_reg =3D addr_reg; + + /* We are expecting a_bits to max out at 7, so we can always use andi.= */ + tcg_debug_assert(a_bits < 12); + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); + + l->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0); + + l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + /* resolve label address */ + if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { + return false; + } + + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); + + /* tail call, with the return address back inline. */ + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (uintptr_t)l->raddr); + tcg_out_call_int(s, (const void *)(l->is_ld ? helper_unaligned_ld + : helper_unaligned_st), true); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + #endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, @@ -1108,6 +1155,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[1]; +#else + unsigned a_bits; #endif TCGReg base =3D TCG_REG_TMP0; =20 @@ -1130,6 +1179,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is_64) tcg_out_ext32u(s, base, addr_regl); addr_regl =3D base; } + a_bits =3D get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, true, addr_regl, a_bits); + } if (guest_base !=3D 0) { tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); } @@ -1174,6 +1227,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[1]; +#else + unsigned a_bits; #endif TCGReg base =3D TCG_REG_TMP0; =20 @@ -1196,6 +1251,10 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is_64) tcg_out_ext32u(s, base, addr_regl); addr_regl =3D base; } + a_bits =3D get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, false, addr_regl, a_bits); + } if (guest_base !=3D 0) { tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); } --=20 2.25.1 From nobody Sun May 5 05:55:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1641262907; cv=none; d=zohomail.com; s=zohoarc; b=ML30G+APOKzwIMV6mMyQDMV2idgigKCxZ4qkoyL9xlez3TyUsqjBtfVaRw58SrBFbuJf7J4WxGykkIS9SjqQ9h0JtksdakbMLLpUo5HHGZ6bVhsZKi/64cKRMWifPN0sallkZ0QJUEFBjW1aF3EWB0FQtMozoqodSCihVWFGA8k= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1641262909146100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 -- tcg/s390x/tcg-target.c.inc | 59 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 57 insertions(+), 4 deletions(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 527ada0f63..69217d995b 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -178,9 +178,7 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, /* no need to flush icache explicitly */ } =20 -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS =20 #endif diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 57e803e339..d5ec770fb8 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -29,6 +29,7 @@ #error "unsupported code generation mode" #endif =20 +#include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" #include "elf.h" =20 @@ -136,6 +137,7 @@ typedef enum S390Opcode { RI_OIHL =3D 0xa509, RI_OILH =3D 0xa50a, RI_OILL =3D 0xa50b, + RI_TMLL =3D 0xa701, =20 RIE_CGIJ =3D 0xec7c, RIE_CGRJ =3D 0xec64, @@ -1804,8 +1806,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Mem= Op opc, TCGReg data, } =20 #if defined(CONFIG_SOFTMMU) -#include "../tcg-ldst.c.inc" - /* We're expecting to use a 20-bit negative offset on the tlb memory ops. = */ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); @@ -1942,6 +1942,53 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) return true; } #else +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, + TCGReg addrlo, unsigned a_bits) +{ + unsigned a_mask =3D (1 << a_bits) - 1; + TCGLabelQemuLdst *l =3D new_ldst_label(s); + + l->is_ld =3D is_ld; + l->addrlo_reg =3D addrlo; + + /* We are expecting a_bits to max out at 7, much lower than TMLL. */ + tcg_debug_assert(a_bits < 16); + tcg_out_insn(s, RI, TMLL, addrlo, a_mask); + + tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ + l->label_ptr[0] =3D s->code_ptr; + s->code_ptr +=3D 1; + + l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + if (!patch_reloc(l->label_ptr[0], R_390_PC16DBL, + (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { + return false; + } + + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); + + /* "Tail call" to the helper, with the return address back inline. */ + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R14, (uintptr_t)l->raddr); + tgen_gotoi(s, S390_CC_ALWAYS, (const void *)(l->is_ld ? helper_unalign= ed_ld + : helper_unaligned_st)); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg, TCGReg *index_reg, tcg_target_long *disp) { @@ -1980,7 +2027,11 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg da= ta_reg, TCGReg addr_reg, #else TCGReg index_reg; tcg_target_long disp; + unsigned a_bits =3D get_alignment_bits(opc); =20 + if (a_bits) { + tcg_out_test_alignment(s, true, addr_reg, a_bits); + } tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp); tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp); #endif @@ -2007,7 +2058,11 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg da= ta_reg, TCGReg addr_reg, #else TCGReg index_reg; tcg_target_long disp; + unsigned a_bits =3D get_alignment_bits(opc); =20 + if (a_bits) { + tcg_out_test_alignment(s, false, addr_reg, a_bits); + } tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp); tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp); #endif --=20 2.25.1 From nobody Sun May 5 05:55:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1641263044; cv=none; d=zohomail.com; s=zohoarc; b=j2vS7zKlIr0IwaiKXNySEYSuhvUnQ5VSm/BIVjBs0L+VEJnRI8n3Kl6typRTpvZ5UHvua5NgG2RXPSLLjrmkioAw8veb//a37mIEEDixYc3cPWlEMWKl1THlPempXRcLYNucevleGzel6C+okIbh6JE3HfQcxq+XHeiND4tLo9E= ARC-Message-Signature: i=1; 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[174.21.75.75]) by smtp.gmail.com with ESMTPSA id b4sm37395501pjm.17.2022.01.03.18.15.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jan 2022 18:15:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g06UIpFMVvSvANx+Qg+u743yK9fN9ISDaQhh0blxyhQ=; b=RayTa0ycU6LGpG5heatUGzR4CuZLKoUWs2ksQLp7YH7/q34wC7BooM048P624IGXS2 /yP5MuX3T6uJHmn+b6su923vWmYpBvo4KXlIP5+PtN2PB+2B8LS9EJ/9I/k3LhDeIuvg vEbGCUBIlzisQhs2D+YNB0yN4jBhFd4++QL/BOB248fWW7xCxYUKvuCpcRlTYukEbUfi oFxV4sShlG7bI8GpbChEJsPKxCb2uOLGFcCpa4Ds0UTuLxKia/59KOphyhffla4OMI1q bVcnSPxyMu5H2MX4k1HpOyFOBXnh2xrpqML4W4JtaRCCu0xSBaq8UvredsOcPSevliXm XeeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g06UIpFMVvSvANx+Qg+u743yK9fN9ISDaQhh0blxyhQ=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1641263046730100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index e76087ccac..92a7c81674 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -292,11 +292,11 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, T= CGCond condition) static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, MemOpIdx oi, const void *tb_ptr) { - MemOp mop =3D get_memop(oi) & (MO_BSWAP | MO_SSIZE); + MemOp mop =3D get_memop(oi); uintptr_t ra =3D (uintptr_t)tb_ptr; =20 #ifdef CONFIG_SOFTMMU - switch (mop) { + switch (mop & (MO_BSWAP | MO_SSIZE)) { case MO_UB: return helper_ret_ldub_mmu(env, taddr, oi, ra); case MO_SB: @@ -326,10 +326,14 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target= _ulong taddr, } #else void *haddr =3D g2h(env_cpu(env), taddr); + unsigned a_mask =3D (1u << get_alignment_bits(mop)) - 1; uint64_t ret; =20 set_helper_retaddr(ra); - switch (mop) { + if (taddr & a_mask) { + helper_unaligned_ld(env, taddr); + } + switch (mop & (MO_BSWAP | MO_SSIZE)) { case MO_UB: ret =3D ldub_p(haddr); break; @@ -377,11 +381,11 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target= _ulong taddr, static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t va= l, MemOpIdx oi, const void *tb_ptr) { - MemOp mop =3D get_memop(oi) & (MO_BSWAP | MO_SSIZE); + MemOp mop =3D get_memop(oi); uintptr_t ra =3D (uintptr_t)tb_ptr; =20 #ifdef CONFIG_SOFTMMU - switch (mop) { + switch (mop & (MO_BSWAP | MO_SIZE)) { case MO_UB: helper_ret_stb_mmu(env, taddr, val, oi, ra); break; @@ -408,9 +412,13 @@ static void tci_qemu_st(CPUArchState *env, target_ulon= g taddr, uint64_t val, } #else void *haddr =3D g2h(env_cpu(env), taddr); + unsigned a_mask =3D (1u << get_alignment_bits(mop)) - 1; =20 set_helper_retaddr(ra); - switch (mop) { + if (taddr & a_mask) { + helper_unaligned_st(env, taddr); + } + switch (mop & (MO_BSWAP | MO_SIZE)) { case MO_UB: stb_p(haddr, val); break; --=20 2.25.1 From nobody Sun May 5 05:55:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1641263012; cv=none; d=zohomail.com; s=zohoarc; b=AgOMOOgs3qtvDyL2jJI5IYAhVe/lRBJftNsoH5NEYWueJpZ27Lk8ySKbQNyIHEqnGGI4eHknLEYuUjolFwFMs8HjRUKtBNrBrEEW7ApVjyP98LH+RURGHgzNonn0/TgE5lk91mL4Lf0tGAgXxuggmieuVi6xPPfceyap9UBC7o8= ARC-Message-Signature: i=1; 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[174.21.75.75]) by smtp.gmail.com with ESMTPSA id b4sm37395501pjm.17.2022.01.03.18.15.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jan 2022 18:15:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E7JCU1a/pkRMOjn44wnlj8F4Wtu8gz5MK8RJjxKzysE=; b=LlnvOaleMsTHTr5F9hF2bNEryy2962/e1nWidwAX+7EafwpH8JbIQAYfKuGERIHI1u pMiGVZ+948Q7XoO+polkah2l6mRFRQAe7eSTlEGG4zqavB6FlNSYDH0FrbbT4fwCwXU8 8B/bTIKSCTIDlNKGnXri6eHq6MVpExzdur+ZGRe9uOWF5pHZWALx54Em2Fi/dn6cRaRG ZDKjTPSOMxnRJNkXgAfFgTJt37SQNcFNzuPJ+yIYjjEX7ZpafAfY+wlDpeQRzPyyhLNW BKaIRHhgqjC0JbU3Tw7V6fdTR16uRV2jphU7VWwfk1g8oX7VBigUK3X6rGSDjPIY0UTG 3oIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E7JCU1a/pkRMOjn44wnlj8F4Wtu8gz5MK8RJjxKzysE=; b=Cgh5iWMOiaBoxUXR11kqDBTzYhdF4NClSUaieWr1e9QahNvO6UbRLy5b9qk4neNwlg KnHntfI2MH1LsXMPXTCLZ6MAIFAUlhiofxN4/p6ZSVSAfvA5Xz+7nPJv2ZYitZDWpeql cBrhDNrsFUYXWjBvN48If0kU+vbM2McV3hsXfz3SRB6FnWThU/+MReg5TDqbPKNGJDxd 59Kh7ievMGRITlCGXO6Gx+v2MQj9sNSWAxvv0Ronw9ga9NJNYE0iRxG+ruWFd2LtmmK0 Td/WUrJzbtMtBYyc+N67djNPwlZuObPMqhK7VxTQtTi9QylMk4nw/hLfniKMTmuRh37q 3XuQ== X-Gm-Message-State: AOAM532OgunogVHaJ0cq7FuGIjO/L433ryWMAAUb5pAbeYxmZMzwEQaP Ls7ccKwnEGJUf7MPEmqe7NqAdNqqJzeYHg== X-Google-Smtp-Source: ABdhPJxW5qU7odljVwoSJIlfoR8UKdqHTRZJl+bAWduiRS4ypFs3dkkL+2UgAn2tREd7ogasfKpu1g== X-Received: by 2002:a63:9854:: with SMTP id l20mr42317871pgo.536.1641262548536; Mon, 03 Jan 2022 18:15:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 7/7] tests/tcg/multiarch: Add sigbus.c Date: Mon, 3 Jan 2022 18:15:43 -0800 Message-Id: <20220104021543.396571-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220104021543.396571-1-richard.henderson@linaro.org> References: <20220104021543.396571-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::533 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1641263014947100001 Content-Type: text/plain; charset="utf-8" A mostly generic test for unaligned access raising SIGBUS. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Acked-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tests/tcg/multiarch/sigbus.c | 68 ++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 tests/tcg/multiarch/sigbus.c diff --git a/tests/tcg/multiarch/sigbus.c b/tests/tcg/multiarch/sigbus.c new file mode 100644 index 0000000000..8134c5fd56 --- /dev/null +++ b/tests/tcg/multiarch/sigbus.c @@ -0,0 +1,68 @@ +#define _GNU_SOURCE 1 + +#include +#include +#include +#include + + +unsigned long long x =3D 0x8877665544332211ull; +void * volatile p =3D (void *)&x + 1; + +void sigbus(int sig, siginfo_t *info, void *uc) +{ + assert(sig =3D=3D SIGBUS); + assert(info->si_signo =3D=3D SIGBUS); +#ifdef BUS_ADRALN + assert(info->si_code =3D=3D BUS_ADRALN); +#endif + assert(info->si_addr =3D=3D p); + exit(EXIT_SUCCESS); +} + +int main() +{ + struct sigaction sa =3D { + .sa_sigaction =3D sigbus, + .sa_flags =3D SA_SIGINFO + }; + int allow_fail =3D 0; + int tmp; + + tmp =3D sigaction(SIGBUS, &sa, NULL); + assert(tmp =3D=3D 0); + + /* + * Select an operation that's likely to enforce alignment. + * On many guests that support unaligned accesses by default, + * this is often an atomic operation. + */ +#if defined(__aarch64__) + asm volatile("ldxr %w0,[%1]" : "=3Dr"(tmp) : "r"(p) : "memory"); +#elif defined(__alpha__) + asm volatile("ldl_l %0,0(%1)" : "=3Dr"(tmp) : "r"(p) : "memory"); +#elif defined(__arm__) + asm volatile("ldrex %0,[%1]" : "=3Dr"(tmp) : "r"(p) : "memory"); +#elif defined(__powerpc__) + asm volatile("lwarx %0,0,%1" : "=3Dr"(tmp) : "r"(p) : "memory"); +#elif defined(__riscv_atomic) + asm volatile("lr.w %0,(%1)" : "=3Dr"(tmp) : "r"(p) : "memory"); +#else + /* No insn known to fault unaligned -- try for a straight load. */ + allow_fail =3D 1; + tmp =3D *(volatile int *)p; +#endif + + assert(allow_fail); + + /* + * We didn't see a signal. + * We might as well validate the unaligned load worked. + */ + if (BYTE_ORDER =3D=3D LITTLE_ENDIAN) { + assert(tmp =3D=3D 0x55443322); + } else { + assert(tmp =3D=3D 0x77665544); + } + return EXIT_SUCCESS; +} --=20 2.25.1