From nobody Tue May 7 18:01:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641250322813818.6084239197072; Mon, 3 Jan 2022 14:52:02 -0800 (PST) Received: from localhost ([::1]:55040 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4WBN-0003Nh-LP for importer@patchew.org; Mon, 03 Jan 2022 17:52:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48402) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4W7W-0003yr-Kc; Mon, 03 Jan 2022 17:48:02 -0500 Received: from [2607:f8b0:4864:20::72d] (port=36463 helo=mail-qk1-x72d.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n4W7U-0001GS-Ps; Mon, 03 Jan 2022 17:48:02 -0500 Received: by mail-qk1-x72d.google.com with SMTP id i130so32157532qke.3; Mon, 03 Jan 2022 14:48:00 -0800 (PST) Received: from rekt.ibmuc.com ([2804:431:c7c7:f4d8:aa07:335f:99e0:a6e7]) by smtp.gmail.com with ESMTPSA id t123sm22917176qkb.135.2022.01.03.14.47.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jan 2022 14:47:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pG0za5U7/L3QI5M2aZfqaNqDe3G+0GpLA4spQ+tDwhQ=; b=HeCivLfP9/Rn462ON8Rv26phWZVIRO0QvrBNRqakN9VEGB3pcwCSr5jiVql3Zz54VS TIVdHNwiz+z/awoAFaHmahQ5SrVBOoOgGvWVOaFlMByd1xODtOX5HnX8Oi8R0jW1ahoY VLJAJkWCryh+oZMAYyrxDURSsU/4NbN4prCa9ZjLB1lJ78yNm2WnQemffdvdr7cFgcRi 5VfdTpb2yZOErQBZ8jOTAtYYK2Kd+XCoQ8YTUvKm7dIHj9XalGh8HaHVfYcGu1RUt0fD eC+9wBb+9vxQ/PGgk2MUdPT2noYy8sS9sySvmJEHbDKFmcpHvFILtkZ6LyJsZO2wtdyc 7OKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pG0za5U7/L3QI5M2aZfqaNqDe3G+0GpLA4spQ+tDwhQ=; b=GyRIgliwChxEr5gcBGui8lqOsw2NJlBZqknxSjpIzQyNqHoCUnL0U9xEl82i1H+K2z nr2ZIhKuQ0j5+cRtOBeTLENL2svdN6uPZr7wIVj3RMlLEg9E6caznlXnccLG0uXZgD3F 60SDSynkc+Clrw7iMMmKgAI78tqC3ir4HGj/862UZTNNVJ0w6n5Gc9mv39tvvYvmvDRR iZ+e3xoFeduEH6GMyWHOStSSDPc+E+qZ8Jw4B4FbClUDIt4iEEaU+b0VRRVKL+bIeaWH 0C1vbseZ6auOPSwmApb4faEgAK8AI9ao+j2mcH1fybFKZmd5ibXJvV+kwe2qWRGjd4vF 8UQw== X-Gm-Message-State: AOAM5325gZ7luXzHkwe8RZ4So6TgS9ileG9nw5bIIYZmlSY4xWhWchla CTJvjly48sFXemDWXIoGG4xT4mxbi+s= X-Google-Smtp-Source: ABdhPJw0FW1zmkQutxKxHe5bDn4w/PXYeOZhvNcPrqYU6Vw56QtrBgTcDOgxWpQsk9co9pIM8N+zkQ== X-Received: by 2002:a05:620a:4489:: with SMTP id x9mr33398470qkp.38.1641250079451; Mon, 03 Jan 2022 14:47:59 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v3 1/4] target/ppc: Cache per-pmc insn and cycle count settings Date: Mon, 3 Jan 2022 19:47:43 -0300 Message-Id: <20220103224746.167831-2-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220103224746.167831-1-danielhb413@gmail.com> References: <20220103224746.167831-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::72d (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72d; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x72d.google.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641250323849100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is the combination of frozen bit and counter type, on a per counter basis. So far this is only used by HFLAGS_INSN_CNT, but will be used more later. Signed-off-by: Richard Henderson [danielhb: fixed PMC4 cyc_cnt shift, insn run latch code, MMCR0_FC handling, "PMC[1-6]" comment] Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 3 +++ target/ppc/cpu_init.c | 1 + target/ppc/helper_regs.c | 2 +- target/ppc/machine.c | 2 ++ target/ppc/power8-pmu.c | 56 ++++++++++++++++++++++++++++++++-------- target/ppc/power8-pmu.h | 14 +++++----- 6 files changed, 58 insertions(+), 20 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index fc66c3561d..fd187fe3dd 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1144,6 +1144,9 @@ struct CPUPPCState { /* Other registers */ target_ulong spr[1024]; /* special purpose registers */ ppc_spr_t spr_cb[1024]; + /* Composite status for PMC[1-6] enabled and counting insns or cycles.= */ + uint8_t pmc_ins_cnt; + uint8_t pmc_cyc_cnt; /* Vector status and control register, minus VSCR_SAT */ uint32_t vscr; /* VSX registers (including FP and AVR) */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 06ef15cd9e..63f9babfee 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -8313,6 +8313,7 @@ static void ppc_cpu_reset(DeviceState *dev) #endif /* CONFIG_TCG */ #endif =20 + pmu_update_summaries(env); hreg_compute_hflags(env); env->reserve_addr =3D (target_ulong)-1ULL; /* Be sure no exception or interrupt is pending */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index b847928842..8671b7bb69 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -123,7 +123,7 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *= env) } =20 #if defined(TARGET_PPC64) - if (pmu_insn_cnt_enabled(env)) { + if (env->pmc_ins_cnt) { hflags |=3D 1 << HFLAGS_INSN_CNT; } #endif diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 93972df58e..756d8de5d8 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -8,6 +8,7 @@ #include "qapi/error.h" #include "qemu/main-loop.h" #include "kvm_ppc.h" +#include "power8-pmu.h" =20 static void post_load_update_msr(CPUPPCState *env) { @@ -19,6 +20,7 @@ static void post_load_update_msr(CPUPPCState *env) */ env->msr ^=3D env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); + pmu_update_summaries(env); } =20 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 08d1902cd5..1f4f611994 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -11,8 +11,6 @@ */ =20 #include "qemu/osdep.h" - -#include "power8-pmu.h" #include "cpu.h" #include "helper_regs.h" #include "exec/exec-all.h" @@ -20,6 +18,7 @@ #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "hw/ppc/ppc.h" +#include "power8-pmu.h" =20 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) =20 @@ -121,18 +120,52 @@ static PMUEventType pmc_get_event(CPUPPCState *env, i= nt sprn) return evt_type; } =20 -bool pmu_insn_cnt_enabled(CPUPPCState *env) +void pmu_update_summaries(CPUPPCState *env) { - int sprn; + target_ulong mmcr0 =3D env->spr[SPR_POWER_MMCR0]; + target_ulong mmcr1 =3D env->spr[SPR_POWER_MMCR1]; + int ins_cnt =3D 0; + int cyc_cnt =3D 0; =20 - for (sprn =3D SPR_POWER_PMC1; sprn <=3D SPR_POWER_PMC5; sprn++) { - if (pmc_get_event(env, sprn) =3D=3D PMU_EVENT_INSTRUCTIONS || - pmc_get_event(env, sprn) =3D=3D PMU_EVENT_INSN_RUN_LATCH) { - return true; + if (mmcr0 & MMCR0_FC) { + goto hflags_calc; + } + + if (!(mmcr0 & MMCR0_FC14) && mmcr1 !=3D 0) { + target_ulong sel; + + sel =3D extract64(mmcr1, MMCR1_PMC1EVT_EXTR, MMCR1_EVT_SIZE); + switch (sel) { + case 0x02: + case 0xfe: + ins_cnt |=3D 1 << 1; + break; + case 0x1e: + case 0xf0: + cyc_cnt |=3D 1 << 1; + break; } + + sel =3D extract64(mmcr1, MMCR1_PMC2EVT_EXTR, MMCR1_EVT_SIZE); + ins_cnt |=3D (sel =3D=3D 0x02) << 2; + cyc_cnt |=3D (sel =3D=3D 0x1e) << 2; + + sel =3D extract64(mmcr1, MMCR1_PMC3EVT_EXTR, MMCR1_EVT_SIZE); + ins_cnt |=3D (sel =3D=3D 0x02) << 3; + cyc_cnt |=3D (sel =3D=3D 0x1e) << 3; + + sel =3D extract64(mmcr1, MMCR1_PMC4EVT_EXTR, MMCR1_EVT_SIZE); + ins_cnt |=3D ((sel =3D=3D 0xfa) || (sel =3D=3D 0x2)) << 4; + cyc_cnt |=3D (sel =3D=3D 0x1e) << 4; } =20 - return false; + ins_cnt |=3D !(mmcr0 & MMCR0_FC56) << 5; + cyc_cnt |=3D !(mmcr0 & MMCR0_FC56) << 6; + + hflags_calc: + env->pmc_ins_cnt =3D ins_cnt; + env->pmc_cyc_cnt =3D cyc_cnt; + env->hflags =3D deposit32(env->hflags, HFLAGS_INSN_CNT, 1, ins_cnt != =3D 0); } =20 static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns) @@ -264,8 +297,9 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong = value) =20 env->spr[SPR_POWER_MMCR0] =3D value; =20 - /* MMCR0 writes can change HFLAGS_PMCCCLEAR and HFLAGS_INSN_CNT */ + /* MMCR0 writes can change HFLAGS_PMCC[01] and HFLAGS_INSN_CNT */ hreg_compute_hflags(env); + pmu_update_summaries(env); =20 /* Update cycle overflow timers with the current MMCR0 state */ pmu_update_overflow_timers(env); @@ -278,7 +312,7 @@ void helper_store_mmcr1(CPUPPCState *env, uint64_t valu= e) env->spr[SPR_POWER_MMCR1] =3D value; =20 /* MMCR1 writes can change HFLAGS_INSN_CNT */ - hreg_compute_hflags(env); + pmu_update_summaries(env); } =20 target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn) diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h index 3ee4b4cda5..a839199561 100644 --- a/target/ppc/power8-pmu.h +++ b/target/ppc/power8-pmu.h @@ -13,14 +13,12 @@ #ifndef POWER8_PMU #define POWER8_PMU =20 -#include "qemu/osdep.h" -#include "cpu.h" -#include "exec/exec-all.h" -#include "exec/helper-proto.h" -#include "qemu/error-report.h" -#include "qemu/main-loop.h" - void cpu_ppc_pmu_init(CPUPPCState *env); -bool pmu_insn_cnt_enabled(CPUPPCState *env); + +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +void pmu_update_summaries(CPUPPCState *env); +#else +static inline void pmu_update_summaries(CPUPPCState *env) { } +#endif =20 #endif --=20 2.33.1 From nobody Tue May 7 18:01:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641250163280451.9326361754688; Mon, 3 Jan 2022 14:49:23 -0800 (PST) Received: from localhost ([::1]:49226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4W8o-0007sK-7P for importer@patchew.org; Mon, 03 Jan 2022 17:49:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48416) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4W7Y-00045U-N6; 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charset="utf-8" From: Richard Henderson Use the cached pmc_ins_cnt value. Unroll the loop over the different PMC counters. Treat the PMC4 run-latch specially. Signed-off-by: Richard Henderson --- target/ppc/power8-pmu.c | 78 ++++++++++++++++++++++++++--------------- 1 file changed, 49 insertions(+), 29 deletions(-) diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 1f4f611994..27c4c7915b 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -170,45 +170,65 @@ void pmu_update_summaries(CPUPPCState *env) =20 static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns) { + target_ulong mmcr0 =3D env->spr[SPR_POWER_MMCR0]; + unsigned ins_cnt =3D env->pmc_ins_cnt; bool overflow_triggered =3D false; - int sprn; - - /* PMC6 never counts instructions */ - for (sprn =3D SPR_POWER_PMC1; sprn <=3D SPR_POWER_PMC5; sprn++) { - PMUEventType evt_type =3D pmc_get_event(env, sprn); - bool insn_event =3D evt_type =3D=3D PMU_EVENT_INSTRUCTIONS || - evt_type =3D=3D PMU_EVENT_INSN_RUN_LATCH; - - if (pmc_is_inactive(env, sprn) || !insn_event) { - continue; + target_ulong tmp; + + if (unlikely(ins_cnt & 0x1e)) { + if (ins_cnt & (1 << 1)) { + tmp =3D env->spr[SPR_POWER_PMC1]; + tmp +=3D num_insns; + if (tmp >=3D PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMC1CE= )) { + tmp =3D PMC_COUNTER_NEGATIVE_VAL; + overflow_triggered =3D true; + } + env->spr[SPR_POWER_PMC1] =3D tmp; } =20 - if (evt_type =3D=3D PMU_EVENT_INSTRUCTIONS) { - env->spr[sprn] +=3D num_insns; + if (ins_cnt & (1 << 2)) { + tmp =3D env->spr[SPR_POWER_PMC2]; + tmp +=3D num_insns; + if (tmp >=3D PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE= )) { + tmp =3D PMC_COUNTER_NEGATIVE_VAL; + overflow_triggered =3D true; + } + env->spr[SPR_POWER_PMC2] =3D tmp; } =20 - if (evt_type =3D=3D PMU_EVENT_INSN_RUN_LATCH && - env->spr[SPR_CTRL] & CTRL_RUN) { - env->spr[sprn] +=3D num_insns; + if (ins_cnt & (1 << 3)) { + tmp =3D env->spr[SPR_POWER_PMC3]; + tmp +=3D num_insns; + if (tmp >=3D PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE= )) { + tmp =3D PMC_COUNTER_NEGATIVE_VAL; + overflow_triggered =3D true; + } + env->spr[SPR_POWER_PMC3] =3D tmp; } =20 - if (env->spr[sprn] >=3D PMC_COUNTER_NEGATIVE_VAL && - pmc_has_overflow_enabled(env, sprn)) { + if (ins_cnt & (1 << 4)) { + target_ulong mmcr1 =3D env->spr[SPR_POWER_MMCR1]; + int sel =3D extract64(mmcr1, MMCR1_PMC4EVT_EXTR, MMCR1_EVT_SIZ= E); + if (sel =3D=3D 0x02 || (env->spr[SPR_CTRL] & CTRL_RUN)) { + tmp =3D env->spr[SPR_POWER_PMC4]; + tmp +=3D num_insns; + if (tmp >=3D PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PM= CjCE)) { + tmp =3D PMC_COUNTER_NEGATIVE_VAL; + overflow_triggered =3D true; + } + env->spr[SPR_POWER_PMC4] =3D tmp; + } + } + } =20 + if (ins_cnt & (1 << 5)) { + tmp =3D env->spr[SPR_POWER_PMC5]; + tmp +=3D num_insns; + if (tmp >=3D PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) { + tmp =3D PMC_COUNTER_NEGATIVE_VAL; overflow_triggered =3D true; - - /* - * The real PMU will always trigger a counter overflow with - * PMC_COUNTER_NEGATIVE_VAL. We don't have an easy way to - * do that since we're counting block of instructions at - * the end of each translation block, and we're probably - * passing this value at this point. - * - * Let's write PMC_COUNTER_NEGATIVE_VAL to the overflowed - * counter to simulate what the real hardware would do. - */ - env->spr[sprn] =3D PMC_COUNTER_NEGATIVE_VAL; } + env->spr[SPR_POWER_PMC5] =3D tmp; } =20 return overflow_triggered; --=20 2.33.1 From nobody Tue May 7 18:01:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641250150281853.1203770814395; Mon, 3 Jan 2022 14:49:10 -0800 (PST) Received: from localhost ([::1]:47918 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4W8b-00070K-9Y for importer@patchew.org; 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Mon, 03 Jan 2022 14:48:03 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v3 3/4] target/ppc: Use env->pnc_cyc_cnt Date: Mon, 3 Jan 2022 19:47:45 -0300 Message-Id: <20220103224746.167831-4-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220103224746.167831-1-danielhb413@gmail.com> References: <20220103224746.167831-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::72e (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72e; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x72e.google.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641250151464100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use the cached pmc_cyc_cnt value in pmu_update_cycles and pmc_update_overflow_timer. This leaves pmc_get_event and pmc_is_inactive unused, so remove them. Signed-off-by: Richard Henderson --- target/ppc/power8-pmu.c | 107 ++++------------------------------------ 1 file changed, 9 insertions(+), 98 deletions(-) diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 27c4c7915b..73713ca2a3 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -24,19 +24,6 @@ =20 #define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL =20 -static bool pmc_is_inactive(CPUPPCState *env, int sprn) -{ - if (env->spr[SPR_POWER_MMCR0] & MMCR0_FC) { - return true; - } - - if (sprn < SPR_POWER_PMC5) { - return env->spr[SPR_POWER_MMCR0] & MMCR0_FC14; - } - - return env->spr[SPR_POWER_MMCR0] & MMCR0_FC56; -} - static bool pmc_has_overflow_enabled(CPUPPCState *env, int sprn) { if (sprn =3D=3D SPR_POWER_PMC1) { @@ -46,80 +33,6 @@ static bool pmc_has_overflow_enabled(CPUPPCState *env, i= nt sprn) return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; } =20 -/* - * For PMCs 1-4, IBM POWER chips has support for an implementation - * dependent event, 0x1E, that enables cycle counting. The Linux kernel - * makes extensive use of 0x1E, so let's also support it. - * - * Likewise, event 0x2 is an implementation-dependent event that IBM - * POWER chips implement (at least since POWER8) that is equivalent to - * PM_INST_CMPL. Let's support this event on PMCs 1-4 as well. - */ -static PMUEventType pmc_get_event(CPUPPCState *env, int sprn) -{ - uint8_t mmcr1_evt_extr[] =3D { MMCR1_PMC1EVT_EXTR, MMCR1_PMC2EVT_EXTR, - MMCR1_PMC3EVT_EXTR, MMCR1_PMC4EVT_EXTR }; - PMUEventType evt_type =3D PMU_EVENT_INVALID; - uint8_t pmcsel; - int i; - - if (pmc_is_inactive(env, sprn)) { - return PMU_EVENT_INACTIVE; - } - - if (sprn =3D=3D SPR_POWER_PMC5) { - return PMU_EVENT_INSTRUCTIONS; - } - - if (sprn =3D=3D SPR_POWER_PMC6) { - return PMU_EVENT_CYCLES; - } - - i =3D sprn - SPR_POWER_PMC1; - pmcsel =3D extract64(env->spr[SPR_POWER_MMCR1], mmcr1_evt_extr[i], - MMCR1_EVT_SIZE); - - switch (pmcsel) { - case 0x2: - evt_type =3D PMU_EVENT_INSTRUCTIONS; - break; - case 0x1E: - evt_type =3D PMU_EVENT_CYCLES; - break; - case 0xF0: - /* - * PMC1SEL =3D 0xF0 is the architected PowerISA v3.1 - * event that counts cycles using PMC1. - */ - if (sprn =3D=3D SPR_POWER_PMC1) { - evt_type =3D PMU_EVENT_CYCLES; - } - break; - case 0xFA: - /* - * PMC4SEL =3D 0xFA is the "instructions completed - * with run latch set" event. - */ - if (sprn =3D=3D SPR_POWER_PMC4) { - evt_type =3D PMU_EVENT_INSN_RUN_LATCH; - } - break; - case 0xFE: - /* - * PMC1SEL =3D 0xFE is the architected PowerISA v3.1 - * event to sample instructions using PMC1. - */ - if (sprn =3D=3D SPR_POWER_PMC1) { - evt_type =3D PMU_EVENT_INSTRUCTIONS; - } - break; - default: - break; - } - - return evt_type; -} - void pmu_update_summaries(CPUPPCState *env) { target_ulong mmcr0 =3D env->spr[SPR_POWER_MMCR0]; @@ -238,18 +151,16 @@ static void pmu_update_cycles(CPUPPCState *env) { uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); uint64_t time_delta =3D now - env->pmu_base_time; - int sprn; + int sprn, cyc_cnt =3D env->pmc_cyc_cnt; =20 for (sprn =3D SPR_POWER_PMC1; sprn <=3D SPR_POWER_PMC6; sprn++) { - if (pmc_get_event(env, sprn) !=3D PMU_EVENT_CYCLES) { - continue; + if (cyc_cnt & (1 << (sprn - SPR_POWER_PMC1 + 1))) { + /* + * The pseries and powernv clock runs at 1Ghz, meaning + * that 1 nanosec equals 1 cycle. + */ + env->spr[sprn] +=3D time_delta; } - - /* - * The pseries and powernv clock runs at 1Ghz, meaning - * that 1 nanosec equals 1 cycle. - */ - env->spr[sprn] +=3D time_delta; } =20 /* Update base_time for future calculations */ @@ -278,7 +189,7 @@ static void pmc_update_overflow_timer(CPUPPCState *env,= int sprn) return; } =20 - if (pmc_get_event(env, sprn) !=3D PMU_EVENT_CYCLES || + if (!(env->pmc_cyc_cnt & (1 << (sprn - SPR_POWER_PMC1 + 1))) || !pmc_has_overflow_enabled(env, sprn)) { /* Overflow timer is not needed for this counter */ timer_del(pmc_overflow_timer); @@ -286,7 +197,7 @@ static void pmc_update_overflow_timer(CPUPPCState *env,= int sprn) } =20 if (env->spr[sprn] >=3D PMC_COUNTER_NEGATIVE_VAL) { - timeout =3D 0; + timeout =3D 0; } else { timeout =3D PMC_COUNTER_NEGATIVE_VAL - env->spr[sprn]; } --=20 2.33.1 From nobody Tue May 7 18:01:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641250352202564.3068114194652; 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Mon, 03 Jan 2022 14:48:05 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v3 4/4] target/ppc: do not call hreg_compute_hflags() in helper_store_mmcr0() Date: Mon, 3 Jan 2022 19:47:46 -0300 Message-Id: <20220103224746.167831-5-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220103224746.167831-1-danielhb413@gmail.com> References: <20220103224746.167831-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::733 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::733; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x733.google.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1641250353180100001 Content-Type: text/plain; charset="utf-8" MMCR0 writes will change only MMCR0 bits which are used to calculate HFLAGS_PMCC0, HFLAGS_PMCC1 and HFLAGS_INSN_CNT hflags. No other machine register will be changed during this operation. This means that hreg_compute_hflags() is overkill for what we need to do. pmu_update_summaries() is already updating HFLAGS_INSN_CNT without calling hreg_compure_hflags(). Let's do the same for the other 2 MMCR0 hflags. Reviewed-by: Richard Henderson Signed-off-by: Daniel Henrique Barboza --- target/ppc/power8-pmu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 73713ca2a3..236e8e66e9 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -224,12 +224,17 @@ static void pmu_update_overflow_timers(CPUPPCState *e= nv) =20 void helper_store_mmcr0(CPUPPCState *env, target_ulong value) { + bool hflags_pmcc0 =3D (value & MMCR0_PMCC0) !=3D 0; + bool hflags_pmcc1 =3D (value & MMCR0_PMCC1) !=3D 0; + pmu_update_cycles(env); =20 env->spr[SPR_POWER_MMCR0] =3D value; =20 /* MMCR0 writes can change HFLAGS_PMCC[01] and HFLAGS_INSN_CNT */ - hreg_compute_hflags(env); + env->hflags =3D deposit32(env->hflags, HFLAGS_PMCC0, 1, hflags_pmcc0); + env->hflags =3D deposit32(env->hflags, HFLAGS_PMCC1, 1, hflags_pmcc1); + pmu_update_summaries(env); =20 /* Update cycle overflow timers with the current MMCR0 state */ --=20 2.33.1