From nobody Tue Feb 10 06:07:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1640868786626511.53556207709084; Thu, 30 Dec 2021 04:53:06 -0800 (PST) Received: from localhost ([::1]:53496 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n2uvZ-0001kj-UV for importer@patchew.org; Thu, 30 Dec 2021 07:53:05 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54244) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n2ufm-0003XN-4M for qemu-devel@nongnu.org; Thu, 30 Dec 2021 07:36:46 -0500 Received: from [2607:f8b0:4864:20::62b] (port=42566 helo=mail-pl1-x62b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n2ufj-0003Rm-Mj for qemu-devel@nongnu.org; Thu, 30 Dec 2021 07:36:45 -0500 Received: by mail-pl1-x62b.google.com with SMTP id u16so18162169plg.9 for ; Thu, 30 Dec 2021 04:36:43 -0800 (PST) Received: from localhost.localdomain ([171.61.71.9]) by smtp.gmail.com with ESMTPSA id a3sm28588348pfv.47.2021.12.30.04.36.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Dec 2021 04:36:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U1wJWkXDR1O+3IU9/SiIGr76nl7NQVzZe0dCGkhC9xE=; b=r3ORz1/KFTILsuOetBwWNr5+Qstfas/au0jFJ1wAvqIZIw0HWIG3CSOKk2/6F2MMht +9AI4GGKWeH87DI4tearQTRbh3rEPjOcTz1SZw4xLu+aHmIaf/AAzaarDcgxWrBCfipK uVdU6qQGmB6k1nWVxjTRz68g2P7IiyLiEYYii7aTHVKkMLtZFkqbh2PW/E3U7nvT9y4m QdeXjjWNQn4YCZWETKAepo0B2i36JGG7rVd5EwvYSW4zCmvwEojcWJUtvTI5En4RZfci 9TaAElK0FefGYk2ncMnTn3gA9hUwOp05G+QO5UCNAwD5QFKjZ2vlKfNA5BOf8vmQDWRc nEtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U1wJWkXDR1O+3IU9/SiIGr76nl7NQVzZe0dCGkhC9xE=; b=xfAO9yAJjejfJ8EwcmBTJHUBMjm7pB3CXNGM9xmJYP3IhM9O9uZ2tTWJEEicWHR3Ao aNSdi0D6nMLJBPb9DqE34jirPqyqBDXqwJStx4DB822GNeegBBXI6qS3o3CKaS/7PZs+ Q+2girxHu+CK1RwnhMXAgyt9kNdOpWnbXWt8jxqyIKWM3I6byth+GMQ1vRVGKnXbl8lX QXoMkYm+AYi05JCVccTLBRfdvPjsJ4XYTvhGsS2lUgW6Dnb9hjVdEXhEm2X8JURVpEyl s8jgvkxfNeipaV9wbuDRI8UP0hYPEOAWm4HM7T6UhjfIoXFdyxM5Eb2fe0tKYVqQ0vue UNNg== X-Gm-Message-State: AOAM532yPuOBR1t188QUEJtawMbceqfsNKAPyZeLHZ+X/7dWSR4t8gBo zqJDz3avyxzMaa22y6QUVrMvMA== X-Google-Smtp-Source: ABdhPJxg9yOKrtpe+K91rxIegClCGtzbIJOrMAcwkztFeWrMQZVkDIv/9rkQAvSmItxbui4W1WZo9Q== X-Received: by 2002:a17:90a:b103:: with SMTP id z3mr38264777pjq.23.1640867801342; Thu, 30 Dec 2021 04:36:41 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Subject: [PATCH v6 15/23] target/riscv: Implement AIA IMSIC interface CSRs Date: Thu, 30 Dec 2021 18:05:31 +0530 Message-Id: <20211230123539.52786-16-anup@brainfault.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211230123539.52786-1-anup@brainfault.org> References: <20211230123539.52786-1-anup@brainfault.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::62b; envelope-from=anup@brainfault.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Atish Patra Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1640868787170000001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The AIA specification defines IMSIC interface CSRs for easy access to the per-HART IMSIC registers without using indirect xiselect and xireg CSRs. This patch implements the AIA IMSIC interface CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel --- target/riscv/csr.c | 202 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 202 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 488877e89c..89e74f848d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -906,6 +906,16 @@ static int aia_xlate_vs_csrno(CPURISCVState *env, int = csrno) return CSR_VSISELECT; case CSR_SIREG: return CSR_VSIREG; + case CSR_SSETEIPNUM: + return CSR_VSSETEIPNUM; + case CSR_SCLREIPNUM: + return CSR_VSCLREIPNUM; + case CSR_SSETEIENUM: + return CSR_VSSETEIENUM; + case CSR_SCLREIENUM: + return CSR_VSCLREIENUM; + case CSR_STOPEI: + return CSR_VSTOPEI; default: return csrno; }; @@ -1058,6 +1068,177 @@ done: return RISCV_EXCP_NONE; } =20 +static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong *v= al, + target_ulong new_val, target_ulong wr_mask) +{ + int ret =3D -EINVAL; + bool set, pend, virt; + target_ulong priv, isel, vgein, xlen, nval, wmask; + + /* Translate CSR number for VS-mode */ + csrno =3D aia_xlate_vs_csrno(env, csrno); + + /* Decode register details from CSR number */ + virt =3D set =3D pend =3D false; + switch (csrno) { + case CSR_MSETEIPNUM: + priv =3D PRV_M; + set =3D true; + break; + case CSR_MCLREIPNUM: + priv =3D PRV_M; + pend =3D true; + break; + case CSR_MSETEIENUM: + priv =3D PRV_M; + set =3D true; + break; + case CSR_MCLREIENUM: + priv =3D PRV_M; + break; + case CSR_SSETEIPNUM: + priv =3D PRV_S; + set =3D true; + pend =3D true; + break; + case CSR_SCLREIPNUM: + priv =3D PRV_S; + pend =3D true; + break; + case CSR_SSETEIENUM: + priv =3D PRV_S; + set =3D true; + break; + case CSR_SCLREIENUM: + priv =3D PRV_S; + break; + case CSR_VSSETEIPNUM: + priv =3D PRV_S; + virt =3D true; + set =3D true; + pend =3D true; + break; + case CSR_VSCLREIPNUM: + priv =3D PRV_S; + virt =3D true; + pend =3D true; + break; + case CSR_VSSETEIENUM: + priv =3D PRV_S; + virt =3D true; + set =3D true; + break; + case CSR_VSCLREIENUM: + priv =3D PRV_S; + virt =3D true; + break; + default: + goto done; + }; + + /* IMSIC CSRs only available when machine implements IMSIC. */ + if (!env->aia_ireg_rmw_fn[priv]) { + goto done; + } + + /* Find the selected guest interrupt file */ + vgein =3D (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; + + /* Selected guest interrupt file should be valid */ + if (virt && (!vgein || env->geilen < vgein)) { + goto done; + } + + /* Set/Clear CSRs always read zero */ + if (val) { + *val =3D 0; + } + + if (wr_mask) { + /* Get interrupt number */ + new_val &=3D wr_mask; + + /* Find target interrupt pending/enable register */ + xlen =3D riscv_cpu_mxl_bits(env); + isel =3D (new_val / xlen); + isel *=3D (xlen / IMSIC_EIPx_BITS); + isel +=3D (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0; + + /* Find the interrupt bit to be set/clear */ + wmask =3D ((target_ulong)1) << (new_val % xlen); + nval =3D (set) ? wmask : 0; + + /* Call machine specific IMSIC register emulation */ + ret =3D env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], + AIA_MAKE_IREG(isel, priv, virt, + vgein, xlen), + NULL, nval, wmask); + } else { + ret =3D 0; + } + +done: + if (ret) { + return (riscv_cpu_virt_enabled(env) && virt) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; + } + return RISCV_EXCP_NONE; +} + +static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + bool virt; + int ret =3D -EINVAL; + target_ulong priv, vgein; + + /* Translate CSR number for VS-mode */ + csrno =3D aia_xlate_vs_csrno(env, csrno); + + /* Decode register details from CSR number */ + virt =3D false; + switch (csrno) { + case CSR_MTOPEI: + priv =3D PRV_M; + break; + case CSR_STOPEI: + priv =3D PRV_S; + break; + case CSR_VSTOPEI: + priv =3D PRV_S; + virt =3D true; + break; + default: + goto done; + }; + + /* IMSIC CSRs only available when machine implements IMSIC. */ + if (!env->aia_ireg_rmw_fn[priv]) { + goto done; + } + + /* Find the selected guest interrupt file */ + vgein =3D (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; + + /* Selected guest interrupt file should be valid */ + if (virt && (!vgein || env->geilen < vgein)) { + goto done; + } + + /* Call machine specific IMSIC register emulation for TOPEI */ + ret =3D env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], + AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein, + riscv_cpu_mxl_bits(env)), + val, new_val, wr_mask); + +done: + if (ret) { + return (riscv_cpu_virt_enabled(env) && virt) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; + } + return RISCV_EXCP_NONE; +} + static RISCVException read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) { @@ -2706,6 +2887,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Machine-Level Interrupts (AIA) */ [CSR_MTOPI] =3D { "mtopi", aia_any, read_mtopi }, =20 + /* Machine-Level IMSIC Interface (AIA) */ + [CSR_MSETEIPNUM] =3D { "mseteipnum", aia_any, NULL, NULL, rmw_xsetclre= inum }, + [CSR_MCLREIPNUM] =3D { "mclreipnum", aia_any, NULL, NULL, rmw_xsetclre= inum }, + [CSR_MSETEIENUM] =3D { "mseteienum", aia_any, NULL, NULL, rmw_xsetclre= inum }, + [CSR_MCLREIENUM] =3D { "mclreienum", aia_any, NULL, NULL, rmw_xsetclre= inum }, + [CSR_MTOPEI] =3D { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, + /* Virtual Interrupts for Supervisor Level (AIA) */ [CSR_MVIEN] =3D { "mvien", aia_any, read_zero, write_ignore }, [CSR_MVIP] =3D { "mvip", aia_any, read_zero, write_ignore }, @@ -2740,6 +2928,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Supervisor-Level Interrupts (AIA) */ [CSR_STOPI] =3D { "stopi", aia_smode, read_stopi }, =20 + /* Supervisor-Level IMSIC Interface (AIA) */ + [CSR_SSETEIPNUM] =3D { "sseteipnum", aia_smode, NULL, NULL, rmw_xsetcl= reinum }, + [CSR_SCLREIPNUM] =3D { "sclreipnum", aia_smode, NULL, NULL, rmw_xsetcl= reinum }, + [CSR_SSETEIENUM] =3D { "sseteienum", aia_smode, NULL, NULL, rmw_xsetcl= reinum }, + [CSR_SCLREIENUM] =3D { "sclreienum", aia_smode, NULL, NULL, rmw_xsetcl= reinum }, + [CSR_STOPEI] =3D { "stopei", aia_smode, NULL, NULL, rmw_xtopei= }, + /* Supervisor-Level High-Half CSRs (AIA) */ [CSR_SIEH] =3D { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, [CSR_SIPH] =3D { "siph", aia_smode32, NULL, NULL, rmw_siph }, @@ -2785,6 +2980,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* VS-Level Interrupts (H-extension with AIA) */ [CSR_VSTOPI] =3D { "vstopi", aia_hmode, read_vstopi }, =20 + /* VS-Level IMSIC Interface (H-extension with AIA) */ + [CSR_VSSETEIPNUM] =3D { "vsseteipnum", aia_hmode, NULL, NULL, rmw_xset= clreinum }, + [CSR_VSCLREIPNUM] =3D { "vsclreipnum", aia_hmode, NULL, NULL, rmw_xset= clreinum }, + [CSR_VSSETEIENUM] =3D { "vsseteienum", aia_hmode, NULL, NULL, rmw_xset= clreinum }, + [CSR_VSCLREIENUM] =3D { "vsclreienum", aia_hmode, NULL, NULL, rmw_xset= clreinum }, + [CSR_VSTOPEI] =3D { "vstopei", aia_hmode, NULL, NULL, rmw_xtop= ei }, + /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, rmw_hi= delegh }, [CSR_HVIENH] =3D { "hvienh", aia_hmode32, read_zero, write_i= gnore }, --=20 2.25.1