From nobody Tue Feb 10 03:15:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1640868470995944.5802928827638; Thu, 30 Dec 2021 04:47:50 -0800 (PST) Received: from localhost ([::1]:43630 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n2uqT-0003PW-Qv for importer@patchew.org; Thu, 30 Dec 2021 07:47:50 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54090) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n2ufW-0002p9-Ph for qemu-devel@nongnu.org; Thu, 30 Dec 2021 07:36:30 -0500 Received: from [2607:f8b0:4864:20::52e] (port=37695 helo=mail-pg1-x52e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n2ufU-0003KI-VS for qemu-devel@nongnu.org; Thu, 30 Dec 2021 07:36:30 -0500 Received: by mail-pg1-x52e.google.com with SMTP id a23so21355627pgm.4 for ; Thu, 30 Dec 2021 04:36:28 -0800 (PST) Received: from localhost.localdomain ([171.61.71.9]) by smtp.gmail.com with ESMTPSA id a3sm28588348pfv.47.2021.12.30.04.36.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Dec 2021 04:36:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lPXORJntThAglwtkmuRAWOQOle2MUp3O2WcWMwe0d+c=; b=cCTMkwI+UG7+G3eLFU1FhURX3ROFI9TdPZkH3Ckr896F6pHaogcTjtvt6tdYRqR+qc SRYQABek8yBCDzGSifh5ULPcgTbupUeBi5GzTR5ZCAcqCLGj6yljjWSvgwSkUyOB3dma unwW7y+d5sV5EbB6U+2vEooff2oSBCmKSeIvxBdMbWI7jBuUWK6eS9la1SnHYfWs9Toj uAkCwYHcSk7w3TMUdDMtBiPLq1OGcEk+mYVxthaoqLjfGgOteoIAJUd2zk1MzgnGmEVy UWdqS3zGXA1ixNHncgiO+OOLrBTasncX9xtUqJXbGlyBT0s+QsoMWbtdkFPBfuKcoFR/ fpcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lPXORJntThAglwtkmuRAWOQOle2MUp3O2WcWMwe0d+c=; b=IfJVl32v7TZQB/LZwaahfl+NzrkOtJDNEVWnGud8jovtcV67WnCM9NJGarTsJB0S/Z odKwHcQbDBG4FpwmVHfGiBD/r4C6A1cvUkLL09S2j9Cn7Kzp/dSkkEnKajnMkRtFrbai QK9cC2wFuoHT8mEn8QvxS6QaDWO7Xk47/lesvPQrBhAhFaCcKaVov6Mm6P/tHUM3MLG/ 7SUggHuX6FkBIy2tkYZGe2lsBUFZiEr6SczET8zkTSjvl36NBR1hkigbGayTKBgyeuPJ Agry2i9a2jHyW2TZqvl+oQjfMS90xsxMdnjiptmzLigm2Ko/+Vvj7RUvdk2pROQPZXFL wHzA== X-Gm-Message-State: AOAM53080C74iQYLy/lPkuy19Nyn1iK7qMU2jR2YZJN52c6eQmdwUQf/ Q5yGwkt2ZX6XNqCrKTxR7G/GbQ== X-Google-Smtp-Source: ABdhPJy+YUVQAhTKq9KvKbuxV6Kb+wMQwp9IsqvaSFDfhp0Ww4zOl4dD74rS6DxAZVJBXEzRNoAEqA== X-Received: by 2002:a62:aa15:0:b0:4ba:ca5f:2841 with SMTP id e21-20020a62aa15000000b004baca5f2841mr30806924pff.73.1640867787704; Thu, 30 Dec 2021 04:36:27 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Subject: [PATCH v6 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs Date: Thu, 30 Dec 2021 18:05:27 +0530 Message-Id: <20211230123539.52786-12-anup@brainfault.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211230123539.52786-1-anup@brainfault.org> References: <20211230123539.52786-1-anup@brainfault.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52e (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::52e; envelope-from=anup@brainfault.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Anup Patel , qemu-devel@nongnu.org, Alistair Francis , Atish Patra , Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1640868472292000001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The AIA hvictl and hviprioX CSRs allow hypervisor to control interrupts visible at VS-level. This patch implements AIA hvictl and hviprioX CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu.h | 2 + target/riscv/csr.c | 126 +++++++++++++++++++++++++++++++++++++++++ target/riscv/machine.c | 2 + 3 files changed, 130 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 72d03aa126..721727c577 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -199,6 +199,7 @@ struct CPURISCVState { uint64_t htimedelta; =20 /* Hypervisor controlled virtual interrupt priorities */ + target_ulong hvictl; uint8_t hviprio[64]; =20 /* Virtual CSRs */ @@ -475,6 +476,7 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) return env->misa_mxl; } #endif +#define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) =20 /* * Encode LMUL to lmul as follows: diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 06db5ab1a8..decb0376fc 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -230,6 +230,15 @@ static RISCVException pointer_masking(CPURISCVState *e= nv, int csrno) return RISCV_EXCP_ILLEGAL_INST; } =20 +static int aia_hmode(CPURISCVState *env, int csrno) +{ + if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return hmode(env, csrno); +} + static int aia_hmode32(CPURISCVState *env, int csrno) { if (!riscv_feature(env, RISCV_FEATURE_AIA)) { @@ -1070,6 +1079,9 @@ static RISCVException rmw_sie64(CPURISCVState *env, i= nt csrno, uint64_t mask =3D env->mideleg & S_MODE_INTERRUPTS; =20 if (riscv_cpu_virt_enabled(env)) { + if (env->hvictl & HVICTL_VTI) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } ret =3D rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask); } else { ret =3D rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask); @@ -1268,6 +1280,9 @@ static RISCVException rmw_sip64(CPURISCVState *env, i= nt csrno, uint64_t mask =3D env->mideleg & sip_writable_mask; =20 if (riscv_cpu_virt_enabled(env)) { + if (env->hvictl & HVICTL_VTI) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } ret =3D rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask); } else { ret =3D rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask); @@ -1654,6 +1669,110 @@ static RISCVException write_htimedeltah(CPURISCVSta= te *env, int csrno, return RISCV_EXCP_NONE; } =20 +static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->hvictl; + return RISCV_EXCP_NONE; +} + +static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val) +{ + env->hvictl =3D val & HVICTL_VALID_MASK; + return RISCV_EXCP_NONE; +} + +static int read_hvipriox(CPURISCVState *env, int first_index, + uint8_t *iprio, target_ulong *val) +{ + int i, irq, rdzero, num_irqs =3D 4 * (riscv_cpu_mxl_bits(env) / 32); + + /* First index has to be multiple of numbe of irqs per register */ + if (first_index % num_irqs) { + return (riscv_cpu_virt_enabled(env)) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; + } + + /* Fill-up return value */ + *val =3D 0; + for (i =3D 0; i < num_irqs; i++) { + if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { + continue; + } + if (rdzero) { + continue; + } + *val |=3D ((target_ulong)iprio[irq]) << (i * 8); + } + + return RISCV_EXCP_NONE; +} + +static int write_hvipriox(CPURISCVState *env, int first_index, + uint8_t *iprio, target_ulong val) +{ + int i, irq, rdzero, num_irqs =3D 4 * (riscv_cpu_mxl_bits(env) / 32); + + /* First index has to be multiple of numbe of irqs per register */ + if (first_index % num_irqs) { + return (riscv_cpu_virt_enabled(env)) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; + } + + /* Fill-up priority arrary */ + for (i =3D 0; i < num_irqs; i++) { + if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { + continue; + } + if (rdzero) { + iprio[irq] =3D 0; + } else { + iprio[irq] =3D (val >> (i * 8)) & 0xff; + } + } + + return RISCV_EXCP_NONE; +} + +static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val) +{ + return read_hvipriox(env, 0, env->hviprio, val); +} + +static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val) +{ + return write_hvipriox(env, 0, env->hviprio, val); +} + +static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val) +{ + return read_hvipriox(env, 4, env->hviprio, val); +} + +static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val) +{ + return write_hvipriox(env, 4, env->hviprio, val); +} + +static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val) +{ + return read_hvipriox(env, 8, env->hviprio, val); +} + +static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val) +{ + return write_hvipriox(env, 8, env->hviprio, val); +} + +static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val) +{ + return read_hvipriox(env, 12, env->hviprio, val); +} + +static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val) +{ + return write_hvipriox(env, 12, env->hviprio, val); +} + /* Virtual CSR Registers */ static RISCVException read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) @@ -2308,9 +2427,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MTVAL2] =3D { "mtval2", hmode, read_mtval2, writ= e_mtval2 }, [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, writ= e_mtinst }, =20 + /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) = */ + [CSR_HVICTL] =3D { "hvictl", aia_hmode, read_hvictl, write_h= victl }, + [CSR_HVIPRIO1] =3D { "hviprio1", aia_hmode, read_hviprio1, wri= te_hviprio1 }, + [CSR_HVIPRIO2] =3D { "hviprio2", aia_hmode, read_hviprio2, wri= te_hviprio2 }, + /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, rmw_hi= delegh }, [CSR_HVIPH] =3D { "hviph", aia_hmode32, NULL, NULL, rmw_hv= iph }, + [CSR_HVIPRIO1H] =3D { "hviprio1h", aia_hmode32, read_hviprio1h, wr= ite_hviprio1h }, + [CSR_HVIPRIO2H] =3D { "hviprio2h", aia_hmode32, read_hviprio2h, wr= ite_hviprio2h }, [CSR_VSIEH] =3D { "vsieh", aia_hmode32, NULL, NULL, rmw_vs= ieh }, [CSR_VSIPH] =3D { "vsiph", aia_hmode32, NULL, NULL, rmw_vs= iph }, =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 44dca84ded..f027d5e307 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -92,6 +92,8 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINTTL(env.hgeie, RISCVCPU), VMSTATE_UINTTL(env.hgeip, RISCVCPU), VMSTATE_UINT64(env.htimedelta, RISCVCPU), + + VMSTATE_UINTTL(env.hvictl, RISCVCPU), VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64), =20 VMSTATE_UINT64(env.vsstatus, RISCVCPU), --=20 2.25.1