From nobody Tue Feb 10 05:45:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1640867935590646.478307445257; Thu, 30 Dec 2021 04:38:55 -0800 (PST) Received: from localhost ([::1]:35224 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n2uho-0005sy-2c for importer@patchew.org; Thu, 30 Dec 2021 07:38:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54024) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n2ufP-0002Nc-6C for qemu-devel@nongnu.org; Thu, 30 Dec 2021 07:36:23 -0500 Received: from [2607:f8b0:4864:20::42e] (port=36473 helo=mail-pf1-x42e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n2ufN-0003JH-32 for qemu-devel@nongnu.org; Thu, 30 Dec 2021 07:36:22 -0500 Received: by mail-pf1-x42e.google.com with SMTP id v13so21305605pfi.3 for ; Thu, 30 Dec 2021 04:36:20 -0800 (PST) Received: from localhost.localdomain ([171.61.71.9]) by smtp.gmail.com with ESMTPSA id a3sm28588348pfv.47.2021.12.30.04.36.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Dec 2021 04:36:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W3p2y0sBcG5eK7LgkiQhJZOb3l1WdarZauxTJiq5sEs=; b=6ardLmdQVOTjGIyx031aeNrU+pYsEu9UkoQrP7k2UjUyp/wkpR0NUNlQxzCYjvMSPx Z/vTs/o9xnBuPYRq/Go/Gk4XpDdjP11FQXVOsi9egKRGSc+3Y9tR9fGXVnUYw/uhJUB5 ryAwufqAoBV/7zdBrV5dsH1u7CEyeS7E/lOjaLD4RIsuefvNJA5tCBwbnfildpvHQuN6 Tn5kJu+tV//nnikMwvqFp6ObCgcXX6dThE3sqC2vuHEqRDoqmFSfZyOVueVKPeluIoBl vkO7f5LAqyL7XxsrdwL8QWB4qIIFSTZDCjRoXxaw/KL2z0VI0nCifTRHEgsZP82ZiTkI hOxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W3p2y0sBcG5eK7LgkiQhJZOb3l1WdarZauxTJiq5sEs=; b=7jOQE8Zr+IPPcEAB0GHrLm90L7FNPJigp7OJgqqMBQZPVIVU4eeCp1UBptif170zr0 Vb+2KROtt1uvkHEpwkr99sez55YiwI5ngI66QiNkZV8LiQ3ISj18g2WwXyvaPuwehU0R pBeA6B+uCfSYbQgiVRvQnHYLh9yp7wpKWsBfOSMkZBgcEWit5GWaycltHx6Ou4P9elgr zAtHA6YrDc6RePZqcLX5ADm6jwlofN3H4mtg7n6PTpkNNl5UUOmEEXsQvgWxRhkEqn79 IToPBzoSS91T1KLoRENVmqQkU5aOVwhQd697hJbuiRRIPmyQqd3wkgSHLgSHAgAHttXu 87xQ== X-Gm-Message-State: AOAM532ouEFzYPscCQE0R9iEZVcORh1w8MUY2/7ww3FP+y7OErZji3bx A3LZ7CG6khNQp3PUgUZiim5kxA== X-Google-Smtp-Source: ABdhPJzkZZiBaoxiNaFxhq42zcj+3SGvNQaQILb0IT5uFIf0O28z4U0bMIeXa8SzODKORmBY6iDyKQ== X-Received: by 2002:aa7:842b:0:b0:4ba:881b:278c with SMTP id q11-20020aa7842b000000b004ba881b278cmr31269849pfn.30.1640867779694; Thu, 30 Dec 2021 04:36:19 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Subject: [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities Date: Thu, 30 Dec 2021 18:05:25 +0530 Message-Id: <20211230123539.52786-10-anup@brainfault.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211230123539.52786-1-anup@brainfault.org> References: <20211230123539.52786-1-anup@brainfault.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42e (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::42e; envelope-from=anup@brainfault.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Anup Patel , qemu-devel@nongnu.org, Alistair Francis , Atish Patra , Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1640867937332000001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The AIA spec defines programmable 8-bit priority for each local interrupt at M-level, S-level and VS-level so we extend local interrupt processing to consider AIA interrupt priorities. The AIA CSRs which help software configure local interrupt priorities will be added by subsequent patches. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 19 ++++ target/riscv/cpu.h | 12 ++ target/riscv/cpu_helper.c | 231 ++++++++++++++++++++++++++++++++++---- target/riscv/machine.c | 3 + 4 files changed, 244 insertions(+), 21 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9f1a4d1088..9ad26035e1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -348,6 +348,10 @@ void restore_state_to_opc(CPURISCVState *env, Translat= ionBlock *tb, =20 static void riscv_cpu_reset(DeviceState *dev) { +#ifndef CONFIG_USER_ONLY + uint8_t iprio; + int i, irq, rdzero; +#endif CPUState *cs =3D CPU(dev); RISCVCPU *cpu =3D RISCV_CPU(cs); RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); @@ -370,6 +374,21 @@ static void riscv_cpu_reset(DeviceState *dev) env->miclaim =3D MIP_SGEIP; env->pc =3D env->resetvec; env->two_stage_lookup =3D false; + + /* Initialized default priorities of local interrupts. */ + for (i =3D 0; i < ARRAY_SIZE(env->miprio); i++) { + iprio =3D riscv_cpu_default_priority(i); + env->miprio[i] =3D (i =3D=3D IRQ_M_EXT) ? 0 : iprio; + env->siprio[i] =3D (i =3D=3D IRQ_S_EXT) ? 0 : iprio; + env->hviprio[i] =3D 0; + } + i =3D 0; + while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { + if (!rdzero) { + env->hviprio[irq] =3D env->miprio[irq]; + } + i++; + } /* mmte is supposed to have pm.current hardwired to 1 */ env->mmte |=3D (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 02f3ef2c3c..140fabfdf9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -182,6 +182,10 @@ struct CPURISCVState { target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ =20 + /* Machine and Supervisor interrupt priorities */ + uint8_t miprio[64]; + uint8_t siprio[64]; + /* Hypervisor CSRs */ target_ulong hstatus; target_ulong hedeleg; @@ -194,6 +198,9 @@ struct CPURISCVState { target_ulong hgeip; uint64_t htimedelta; =20 + /* Hypervisor controlled virtual interrupt priorities */ + uint8_t hviprio[64]; + /* Virtual CSRs */ /* * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. @@ -379,6 +386,11 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f= , CPUState *cs, int cpuid, void *opaque); int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); +uint8_t riscv_cpu_default_priority(int irq); +int riscv_cpu_mirq_pending(CPURISCVState *env); +int riscv_cpu_sirq_pending(CPURISCVState *env); +int riscv_cpu_vsirq_pending(CPURISCVState *env); bool riscv_cpu_fp_enabled(CPURISCVState *env); target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f94a36fa89..e3532de4cf 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -151,36 +151,225 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target= _ulong *pc, } =20 #ifndef CONFIG_USER_ONLY -static int riscv_cpu_local_irq_pending(CPURISCVState *env) + +/* + * The HS-mode is allowed to configure priority only for the + * following VS-mode local interrupts: + * + * 0 (Reserved interrupt, reads as zero) + * 1 Supervisor software interrupt + * 4 (Reserved interrupt, reads as zero) + * 5 Supervisor timer interrupt + * 8 (Reserved interrupt, reads as zero) + * 13 (Reserved interrupt) + * 14 " + * 15 " + * 16 " + * 18 Debug/trace interrupt + * 20 (Reserved interrupt) + * 22 " + * 24 " + * 26 " + * 28 " + * 30 (Reserved for standard reporting of bus or system errors) + */ + +static int hviprio_index2irq[] =3D + { 0, 1, 4, 5, 8, 13, 14, 15, 16, 18, 20, 22, 24, 26, 28, 30 }; +static int hviprio_index2rdzero[] =3D + { 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; + +int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) { - target_ulong virt_enabled =3D riscv_cpu_virt_enabled(env); + if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <=3D index) { + return -EINVAL; + } + + if (out_irq) { + *out_irq =3D hviprio_index2irq[index]; + } =20 - target_ulong mstatus_mie =3D get_field(env->mstatus, MSTATUS_MIE); - target_ulong mstatus_sie =3D get_field(env->mstatus, MSTATUS_SIE); + if (out_rdzero) { + *out_rdzero =3D hviprio_index2rdzero[index]; + } =20 - target_ulong vsgemask =3D - (target_ulong)1 << get_field(env->hstatus, HSTATUS_VGEIN); - target_ulong vsgein =3D (env->hgeip & vsgemask) ? MIP_VSEIP : 0; + return 0; +} =20 - target_ulong pending =3D (env->mip | vsgein) & env->mie; +uint8_t riscv_cpu_default_priority(int irq) +{ + int u, l; + uint8_t iprio =3D IPRIO_MMAXIPRIO; =20 - target_ulong mie =3D env->priv < PRV_M || - (env->priv =3D=3D PRV_M && mstatus_mie); - target_ulong sie =3D env->priv < PRV_S || - (env->priv =3D=3D PRV_S && mstatus_sie); - target_ulong hsie =3D virt_enabled || sie; - target_ulong vsie =3D virt_enabled && sie; + if (irq < 0 || irq > 63) { + return iprio; + } =20 - target_ulong irqs =3D - (pending & ~env->mideleg & -mie) | - (pending & env->mideleg & ~env->hideleg & -hsie) | - (pending & env->mideleg & env->hideleg & -vsie); + /* + * Default priorities of local interrupts are defined in the + * RISC-V Advanced Interrupt Architecture specification. + * + * ---------------------------------------------------------------- + * Default | + * Priority | Major Interrupt Numbers + * ---------------------------------------------------------------- + * Highest | 63 (3f), 62 (3e), 31 (1f), 30 (1e), 61 (3d), 60 (3c), + * | 59 (3b), 58 (3a), 29 (1d), 28 (1c), 57 (39), 56 (38), + * | 55 (37), 54 (36), 27 (1b), 26 (1a), 53 (35), 52 (34), + * | 51 (33), 50 (32), 25 (19), 24 (18), 49 (31), 48 (30) + * | + * | 11 (0b), 3 (03), 7 (07) + * | 9 (09), 1 (01), 5 (05) + * | 12 (0c) + * | 10 (0a), 2 (02), 6 (06) + * | + * | 47 (2f), 46 (2e), 23 (17), 22 (16), 45 (2d), 44 (2c), + * | 43 (2b), 42 (2a), 21 (15), 20 (14), 41 (29), 40 (28), + * | 39 (27), 38 (26), 19 (13), 18 (12), 37 (25), 36 (24), + * Lowest | 35 (23), 34 (22), 17 (11), 16 (10), 33 (21), 32 (20) + * ---------------------------------------------------------------- + */ =20 - if (irqs) { - return ctz64(irqs); /* since non-zero */ + u =3D IPRIO_DEFAULT_U(irq); + l =3D IPRIO_DEFAULT_L(irq); + if (u =3D=3D 0) { + if (irq =3D=3D IRQ_VS_EXT || irq =3D=3D IRQ_VS_TIMER || + irq =3D=3D IRQ_VS_SOFT) { + iprio =3D IPRIO_DEFAULT_VS; + } else if (irq =3D=3D IRQ_S_GEXT) { + iprio =3D IPRIO_DEFAULT_SGEXT; + } else if (irq =3D=3D IRQ_S_EXT || irq =3D=3D IRQ_S_TIMER || + irq =3D=3D IRQ_S_SOFT) { + iprio =3D IPRIO_DEFAULT_S; + } else if (irq =3D=3D IRQ_M_EXT || irq =3D=3D IRQ_M_TIMER || + irq =3D=3D IRQ_M_SOFT) { + iprio =3D IPRIO_DEFAULT_M; + } else { + iprio =3D IPRIO_DEFAULT_VS; + } + } else if (u =3D=3D 1) { + if (l < 8) { + iprio =3D IPRIO_DEFAULT_16_23(irq); + } else { + iprio =3D IPRIO_DEFAULT_24_31(irq); + } + } else if (u =3D=3D 2) { + iprio =3D IPRIO_DEFAULT_32_47(irq); + } else if (u =3D=3D 3) { + iprio =3D IPRIO_DEFAULT_48_63(irq); + } + + return iprio; +} + +static int riscv_cpu_pending_to_irq(CPURISCVState *env, + uint64_t pending, uint8_t *iprio) +{ + int irq, best_irq =3D RISCV_EXCP_NONE; + unsigned int prio, best_prio =3D UINT_MAX; + + if (!pending) { + return RISCV_EXCP_NONE; + } + + irq =3D ctz64(pending); + if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + return irq; + } + + pending =3D pending >> irq; + while (pending) { + prio =3D iprio[irq]; + if (!prio) { + prio =3D (riscv_cpu_default_priority(irq) < IPRIO_DEFAULT_M) ? + 1 : IPRIO_MMAXIPRIO; + } + if ((pending & 0x1) && (prio < best_prio)) { + best_irq =3D irq; + best_prio =3D prio; + } + irq++; + pending =3D pending >> 1; + } + + return best_irq; +} + +static uint64_t riscv_cpu_all_pending(CPURISCVState *env) +{ + uint32_t gein =3D get_field(env->hstatus, HSTATUS_VGEIN); + uint64_t vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; + + return (env->mip | vsgein) & env->mie; +} + +int riscv_cpu_mirq_pending(CPURISCVState *env) +{ + uint64_t irqs =3D riscv_cpu_all_pending(env) & ~env->mideleg & + ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); + + return riscv_cpu_pending_to_irq(env, irqs, env->miprio); +} + +int riscv_cpu_sirq_pending(CPURISCVState *env) +{ + uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & + ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); + + return riscv_cpu_pending_to_irq(env, irqs, env->siprio); +} + +int riscv_cpu_vsirq_pending(CPURISCVState *env) +{ + uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); + + return riscv_cpu_pending_to_irq(env, irqs >> 1, env->hviprio); +} + +static int riscv_cpu_local_irq_pending(CPURISCVState *env) +{ + int virq; + uint64_t irqs, pending, mie, hsie, vsie; + + /* Determine interrupt enable state of all privilege modes */ + if (riscv_cpu_virt_enabled(env)) { + mie =3D 1; + hsie =3D 1; + vsie =3D (env->priv < PRV_S) || + (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_= SIE)); } else { - return RISCV_EXCP_NONE; /* indicates no pending interrupt */ + mie =3D (env->priv < PRV_M) || + (env->priv =3D=3D PRV_M && get_field(env->mstatus, MSTATUS_M= IE)); + hsie =3D (env->priv < PRV_S) || + (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_= SIE)); + vsie =3D 0; } + + /* Determine all pending interrupts */ + pending =3D riscv_cpu_all_pending(env); + + /* Check M-mode interrupts */ + irqs =3D pending & ~env->mideleg & -mie; + if (irqs) { + return riscv_cpu_pending_to_irq(env, irqs, env->miprio); + } + + /* Check HS-mode interrupts */ + irqs =3D pending & env->mideleg & ~env->hideleg & -hsie; + if (irqs) { + return riscv_cpu_pending_to_irq(env, irqs, env->siprio); + } + + /* Check VS-mode interrupts */ + irqs =3D pending & env->mideleg & env->hideleg & -vsie; + if (irqs) { + virq =3D riscv_cpu_pending_to_irq(env, irqs >> 1, env->hviprio); + return (virq <=3D 0) ? virq : virq + 1; + } + + /* Indicate no pending interrupt */ + return RISCV_EXCP_NONE; } =20 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 76dd0d415c..cffc444969 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -92,6 +92,7 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINTTL(env.hgeie, RISCVCPU), VMSTATE_UINTTL(env.hgeip, RISCVCPU), VMSTATE_UINT64(env.htimedelta, RISCVCPU), + VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64), =20 VMSTATE_UINT64(env.vsstatus, RISCVCPU), VMSTATE_UINTTL(env.vstvec, RISCVCPU), @@ -173,6 +174,8 @@ const VMStateDescription vmstate_riscv_cpu =3D { .fields =3D (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), + VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64), + VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64), VMSTATE_UINTTL(env.pc, RISCVCPU), VMSTATE_UINTTL(env.load_res, RISCVCPU), VMSTATE_UINTTL(env.load_val, RISCVCPU), --=20 2.25.1