From nobody Sun May 19 11:06:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1640652931; cv=none; d=zohomail.com; s=zohoarc; b=HdH40tEnH7jqddqAYePwPXiA3PikzCbtLDrwGkJBXF29iUrp9Gpn/b+TDai4vTf+PJBv4e0NqTYGbd5YMoz56d+OJm8NdBgAXipK2SsjxmMxB6CdeAtUUlYkugFVX8QUnWWaaoYhyCDL7/NkjkuS8VzK+mcdDbMr3fZnLbHWJWo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1640652931; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=g5IXxi+MTJvB2rpocscSQO5j/XA/3WUTCgLl05fxK/4=; b=OzXXCEEGKVuZU2IQJbChOHgailyIZUjAL1geXnaUMXsGCr8uEdk4mQGzqFO1cqnIzuiEo+sREaFtPDt1uXf6n6FMbioC6xL/zevr8GUln5suBl9oYQBTwPdL8aZ7PtCiHQwlU70SYj4U7KmOnPxZD9ANGiysP3STB+tezOnoJDM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1640652931340608.6002757283396; Mon, 27 Dec 2021 16:55:31 -0800 (PST) Received: from localhost ([::1]:57054 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n20m2-0001vx-MF for importer@patchew.org; Mon, 27 Dec 2021 19:55:30 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47530) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n20kJ-0007xo-RZ for qemu-devel@nongnu.org; Mon, 27 Dec 2021 19:53:45 -0500 Received: from [2607:f8b0:4864:20::532] (port=43522 helo=mail-pg1-x532.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n20kH-0002qR-Ti for qemu-devel@nongnu.org; Mon, 27 Dec 2021 19:53:43 -0500 Received: by mail-pg1-x532.google.com with SMTP id 8so14646634pgc.10 for ; Mon, 27 Dec 2021 16:53:41 -0800 (PST) Received: from localhost.localdomain (1-169-192-165.dynamic-ip.hinet.net. [1.169.192.165]) by smtp.gmail.com with ESMTPSA id t27sm19266587pfg.41.2021.12.27.16.53.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Dec 2021 16:53:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g5IXxi+MTJvB2rpocscSQO5j/XA/3WUTCgLl05fxK/4=; b=jSIC7cSbx0CX0xZ03uAAKAvIqlAM5vZUn8e/bez6RfFrRbW1ReVszy5hE3ib89scYQ G/LWM0loNa3dAVPc7WgYqZSAjhyIEXQiiOx2I3GDjv35VF3x+wsq4UvNEZXkbi0ucpdL +9EHg86+xoySvvYf0rngJSuO2u7PezotSo8piHmog4yav8THyxFWupGcqK8p0hHpikU8 f5p+sbo5vWGDufJxRUeQa+pkmVgGTUN8TK4ymQIOPhPQzQ0h9nR7Gpzpyr1YW7Y407ov ejKkmg8XkyhglXEC6+dheRWgJMzn01drP9HeB96KRPGoGfklUGu2i9m+8O0buEPfKIhn cJcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g5IXxi+MTJvB2rpocscSQO5j/XA/3WUTCgLl05fxK/4=; b=tONFxt3ZXsmOUXOSVbz7Pn1iIQipxYPrX09huIKB0eKm/YnD6jLgwF6VUEQpxQO9Fv OEzqV+flilDuZM2P8073OTHPdAVHSbhlNrF5GCiQxiVqgLQT8gAq7cCjfijkTzQI94Wi mYj0xUjbT+ojv1ISl9pnfphcldr1/Sdr3oQRlXyIH8GDn66MhCbMIclPj7C8xA+TAqhp gW6elNzsVxAnPH+lDfg7qCOCldoFK8ANGIbcYJDfnVDdziusE2PuK5/XFOVncb8WeCy/ I4s29It885r/UPT321DIfEYAK8K2dkQ0ZEaNJbxFDQZysj48Wv/XfBNwDwSPUSv3XaYc lMQQ== X-Gm-Message-State: AOAM532f1iP0VZUPofIjAt/ESVOH+jL2Rn4a9Ora6ze0YBw5Gmg2uwn5 EabedfW4UElhsFjkukaEfEKS3w== X-Google-Smtp-Source: ABdhPJzBftlR+OCIleyxfweLHcTGNd9+rjtDgG6qY9Icb6jUl5nt6TU+viZIT80isAwBr+49YLtGTQ== X-Received: by 2002:a05:6a00:181e:b0:4ba:b71e:2126 with SMTP id y30-20020a056a00181e00b004bab71e2126mr19934272pfa.13.1640652820766; Mon, 27 Dec 2021 16:53:40 -0800 (PST) From: Jim Shu To: Alistair.Francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com, frank.chang@sifive.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register Date: Tue, 28 Dec 2021 08:52:35 +0800 Message-Id: <20211228005236.415583-2-jim.shu@sifive.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211228005236.415583-1-jim.shu@sifive.com> References: <20211228005236.415583-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::532 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=jim.shu@sifive.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jim Shu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1640653837391000001 Content-Type: text/plain; charset="utf-8" Real PDMA support high 32-bit read/write memory access of 64-bit register. The following result is PDMA tested in U-Boot on Unmatched board: 1. Real PDMA is allowed high 32-bit read/write to 64-bit register. =3D> mw.l 0x3000000 0x0 <=3D Disclaim channel 0 =3D> mw.l 0x3000000 0x1 <=3D Claim channel 0 =3D> mw.l 0x3000010 0x80000000 <=3D Write low 32-bit NextDest= (NextDest =3D 0x280000000) =3D> mw.l 0x3000014 0x2 <=3D Write high 32-bit NextDest =3D> md.l 0x3000010 1 <=3D Dump low 32-bit NextDest 03000010: 80000000 =3D> md.l 0x3000014 1 <=3D Dump high 32-bit NextDest 03000014: 00000002 =3D> mw.l 0x3000018 0x80001000 <=3D Write low 32-bit NextSrc = (NextSrc =3D 0x280001000) =3D> mw.l 0x300001c 0x2 <=3D Write high 32-bit NextSrc =3D> md.l 0x3000018 1 <=3D Dump low 32-bit NextSrc 03000010: 80001000 =3D> md.l 0x300001c 1 <=3D Dump high 32-bit NextSrc 03000014: 00000002 2. PDMA transfer from 0x280001000 to 0x280000000 is OK. =3D> mw.q 0x3000008 0x4 <=3D NextBytes =3D 4 =3D> mw.l 0x3000004 0x22000000 <=3D wsize =3D rsize =3D 2 (2^= 2 =3D 4 bytes) =3D> mw.l 0x280000000 0x87654321 <=3D Fill test data to dst =3D> mw.l 0x280001000 0x12345678 <=3D Fill test data to src =3D> md.l 0x280000000 1; md.l 0x280001000 1 <=3D Dump src/dst memory conte= nts 280000000: 87654321 !Ce. 280001000: 12345678 xV4. =3D> md.l 0x3000000 8 <=3D Dump PDMA status 03000000: 00000001 22000000 00000004 00000000 ......."........ 03000010: 80000000 00000002 80001000 00000002 ................ =3D> mw.l 0x3000000 0x3 <=3D Set channel 0 run and cla= im bits =3D> md.l 0x3000000 8 <=3D Dump PDMA status 03000000: 40000001 22000000 00000004 00000000 ...@..."........ 03000010: 80000000 00000002 80001000 00000002 ................ =3D> md.l 0x280000000 1; md.l 0x280001000 1 <=3D Dump src/dst memory conte= nts 280000000: 12345678 xV4. 280001000: 12345678 xV4. Signed-off-by: Jim Shu Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/dma/sifive_pdma.c | 174 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 152 insertions(+), 22 deletions(-) diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c index 85fe34f5f3..b8b198ab4e 100644 --- a/hw/dma/sifive_pdma.c +++ b/hw/dma/sifive_pdma.c @@ -177,18 +177,44 @@ static inline void sifive_pdma_update_irq(SiFivePDMAS= tate *s, int ch) s->chan[ch].state =3D DMA_CHAN_STATE_IDLE; } =20 -static uint64_t sifive_pdma_read(void *opaque, hwaddr offset, unsigned siz= e) +static uint64_t sifive_pdma_readq(SiFivePDMAState *s, int ch, hwaddr offse= t) { - SiFivePDMAState *s =3D opaque; - int ch =3D SIFIVE_PDMA_CHAN_NO(offset); uint64_t val =3D 0; =20 - if (ch >=3D SIFIVE_PDMA_CHANS) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n", - __func__, ch); - return 0; + offset &=3D 0xfff; + switch (offset) { + case DMA_NEXT_BYTES: + val =3D s->chan[ch].next_bytes; + break; + case DMA_NEXT_DST: + val =3D s->chan[ch].next_dst; + break; + case DMA_NEXT_SRC: + val =3D s->chan[ch].next_src; + break; + case DMA_EXEC_BYTES: + val =3D s->chan[ch].exec_bytes; + break; + case DMA_EXEC_DST: + val =3D s->chan[ch].exec_dst; + break; + case DMA_EXEC_SRC: + val =3D s->chan[ch].exec_src; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unexpected 64-bit access to 0x%" HWADDR_PRIX "\= n", + __func__, offset); + break; } =20 + return val; +} + +static uint32_t sifive_pdma_readl(SiFivePDMAState *s, int ch, hwaddr offse= t) +{ + uint32_t val =3D 0; + offset &=3D 0xfff; switch (offset) { case DMA_CONTROL: @@ -198,28 +224,47 @@ static uint64_t sifive_pdma_read(void *opaque, hwaddr= offset, unsigned size) val =3D s->chan[ch].next_config; break; case DMA_NEXT_BYTES: - val =3D s->chan[ch].next_bytes; + val =3D extract64(s->chan[ch].next_bytes, 0, 32); + break; + case DMA_NEXT_BYTES + 4: + val =3D extract64(s->chan[ch].next_bytes, 32, 32); break; case DMA_NEXT_DST: - val =3D s->chan[ch].next_dst; + val =3D extract64(s->chan[ch].next_dst, 0, 32); + break; + case DMA_NEXT_DST + 4: + val =3D extract64(s->chan[ch].next_dst, 32, 32); break; case DMA_NEXT_SRC: - val =3D s->chan[ch].next_src; + val =3D extract64(s->chan[ch].next_src, 0, 32); + break; + case DMA_NEXT_SRC + 4: + val =3D extract64(s->chan[ch].next_src, 32, 32); break; case DMA_EXEC_CONFIG: val =3D s->chan[ch].exec_config; break; case DMA_EXEC_BYTES: - val =3D s->chan[ch].exec_bytes; + val =3D extract64(s->chan[ch].exec_bytes, 0, 32); + break; + case DMA_EXEC_BYTES + 4: + val =3D extract64(s->chan[ch].exec_bytes, 32, 32); break; case DMA_EXEC_DST: - val =3D s->chan[ch].exec_dst; + val =3D extract64(s->chan[ch].exec_dst, 0, 32); + break; + case DMA_EXEC_DST + 4: + val =3D extract64(s->chan[ch].exec_dst, 32, 32); break; case DMA_EXEC_SRC: - val =3D s->chan[ch].exec_src; + val =3D extract64(s->chan[ch].exec_src, 0, 32); + break; + case DMA_EXEC_SRC + 4: + val =3D extract64(s->chan[ch].exec_src, 32, 32); break; default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\= n", + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unexpected 32-bit access to 0x%" HWADDR_PRIX "\= n", __func__, offset); break; } @@ -227,19 +272,66 @@ static uint64_t sifive_pdma_read(void *opaque, hwaddr= offset, unsigned size) return val; } =20 -static void sifive_pdma_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) +static uint64_t sifive_pdma_read(void *opaque, hwaddr offset, unsigned siz= e) { SiFivePDMAState *s =3D opaque; int ch =3D SIFIVE_PDMA_CHAN_NO(offset); - bool claimed, run; + uint64_t val =3D 0; =20 if (ch >=3D SIFIVE_PDMA_CHANS) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n", __func__, ch); - return; + return 0; + } + + switch (size) { + case 8: + val =3D sifive_pdma_readq(s, ch, offset); + break; + case 4: + val =3D sifive_pdma_readl(s, ch, offset); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid read size %u to PDMA\n= ", + __func__, size); + return 0; } =20 + return val; +} + +static void sifive_pdma_writeq(SiFivePDMAState *s, int ch, + hwaddr offset, uint64_t value) +{ + offset &=3D 0xfff; + switch (offset) { + case DMA_NEXT_BYTES: + s->chan[ch].next_bytes =3D value; + break; + case DMA_NEXT_DST: + s->chan[ch].next_dst =3D value; + break; + case DMA_NEXT_SRC: + s->chan[ch].next_src =3D value; + break; + case DMA_EXEC_BYTES: + case DMA_EXEC_DST: + case DMA_EXEC_SRC: + /* these are read-only registers */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unexpected 64-bit access to 0x%" HWADDR_PRIX "\= n", + __func__, offset); + break; + } +} + +static void sifive_pdma_writel(SiFivePDMAState *s, int ch, + hwaddr offset, uint32_t value) +{ + bool claimed, run; + offset &=3D 0xfff; switch (offset) { case DMA_CONTROL: @@ -282,13 +374,24 @@ static void sifive_pdma_write(void *opaque, hwaddr of= fset, s->chan[ch].next_config =3D value; break; case DMA_NEXT_BYTES: - s->chan[ch].next_bytes =3D value; + s->chan[ch].next_bytes =3D + deposit64(s->chan[ch].next_bytes, 0, 32, value); + break; + case DMA_NEXT_BYTES + 4: + s->chan[ch].next_bytes =3D + deposit64(s->chan[ch].next_bytes, 32, 32, value); break; case DMA_NEXT_DST: - s->chan[ch].next_dst =3D value; + s->chan[ch].next_dst =3D deposit64(s->chan[ch].next_dst, 0, 32, va= lue); + break; + case DMA_NEXT_DST + 4: + s->chan[ch].next_dst =3D deposit64(s->chan[ch].next_dst, 32, 32, v= alue); break; case DMA_NEXT_SRC: - s->chan[ch].next_src =3D value; + s->chan[ch].next_src =3D deposit64(s->chan[ch].next_src, 0, 32, va= lue); + break; + case DMA_NEXT_SRC + 4: + s->chan[ch].next_src =3D deposit64(s->chan[ch].next_src, 32, 32, v= alue); break; case DMA_EXEC_CONFIG: case DMA_EXEC_BYTES: @@ -297,12 +400,39 @@ static void sifive_pdma_write(void *opaque, hwaddr of= fset, /* these are read-only registers */ break; default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\= n", + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unexpected 32-bit access to 0x%" HWADDR_PRIX "\= n", __func__, offset); break; } } =20 +static void sifive_pdma_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + SiFivePDMAState *s =3D opaque; + int ch =3D SIFIVE_PDMA_CHAN_NO(offset); + + if (ch >=3D SIFIVE_PDMA_CHANS) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n", + __func__, ch); + return; + } + + switch (size) { + case 8: + sifive_pdma_writeq(s, ch, offset, value); + break; + case 4: + sifive_pdma_writel(s, ch, offset, (uint32_t) value); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid write size %u to PDMA\= n", + __func__, size); + break; + } +} + static const MemoryRegionOps sifive_pdma_ops =3D { .read =3D sifive_pdma_read, .write =3D sifive_pdma_write, --=20 2.25.1 From nobody Sun May 19 11:06:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1640652931; cv=none; d=zohomail.com; s=zohoarc; b=RIxawyObW/w+/jRjZtPKhdAUTrwUglssAaaQp+XxgfYXEkwafNBPwW1GeOo+GfBujTAvQxUVQEyG4U+SrCK1wKcGnyzluyhvUtEjUbcecFl5fk0eoa5t0YkSH6iR9WVrOJpDRrnBhrdkEEmpsJNFBsRKnrLVWZA544MihgaKI3M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[1.169.192.165]) by smtp.gmail.com with ESMTPSA id t27sm19266587pfg.41.2021.12.27.16.53.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Dec 2021 16:53:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+nJte6JP6EZUPzQBYs32kg6qH8WTQTkFEHae1nTePgI=; b=bHVGEvfy8rTJZ1OcncAtIJrmj984Tg5RU+HQ2T322BB7+rqQn0rKI1YZeKEjYGDsOl xDIQx9r4wW1p6ZDaU4plUQFC9xKRmxQ+3lmZqXFuTqLV1qRNWpxixPPXRBKnoWcQS1Sb FFmywveWGveQ41bwE+2FUZ/+obu/fbV5tar+Rv7AcPE/DP1bWuMwuamBr5dKHB80d4/1 yTgScS1oeKyA/DNH9CKG2xbd8ispSYzyIpIDSpXQJ5ohOsC+PKZg0QhIK58+s4tBiR9i Tuye3YErFk4L6RzdIyYDz5kM+X9zTHQaUfn8xs8IBUSLwS4HyKs3tR0WP9tWqNPOEVLf msfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+nJte6JP6EZUPzQBYs32kg6qH8WTQTkFEHae1nTePgI=; b=c6hNrAG020jG7QM8qhRODIrj7Q3mu9W7X/97QhVPrcvMCDLzkSLaXPFatRXG27Zuna 79Shd7dMRV1wLzdYUKojENxVvB5cbBSf3s/u0hEGQIxPe1BsAZuMo0G9zpBseW9bpC4w RlBNGzhGgfyLVb+t5HzbtiiWvkcFQmLVBBemAuVH+RIdurK/UBx1GWEFkhpMZxefcOwj OByXFSmjhEcoJ/cqcPmRD9xIQ8tsjbRqzbK2L9xHXBo275yNIpBLpYbAEvk+O6VuIanZ 7QkbVIId5WerD79N+soydJA5lYTkA2Zvp7VN78BjEbZcmaZZyrnMNB2DUYQ/cDQs7YrR /8rA== X-Gm-Message-State: AOAM532B4LfUiN26U/EfWQ0gOgu4/bSltKNqU4I85EX3EE0x0JVchAq0 BuyM8LJCel/ut8lTZuQDL8zM1g== X-Google-Smtp-Source: ABdhPJwoeOSjWadWH4WVesXLVrFH7Y3POkv5+eAevixjh1i4HoXbbS2RQc4B2qcPmf1QfZwZgM/FoQ== X-Received: by 2002:a63:790a:: with SMTP id u10mr8739039pgc.302.1640652824814; Mon, 27 Dec 2021 16:53:44 -0800 (PST) From: Jim Shu To: Alistair.Francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com, frank.chang@sifive.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers Date: Tue, 28 Dec 2021 08:52:36 +0800 Message-Id: <20211228005236.415583-3-jim.shu@sifive.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211228005236.415583-1-jim.shu@sifive.com> References: <20211228005236.415583-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52a (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=jim.shu@sifive.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jim Shu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1640652933417000003 Content-Type: text/plain; charset="utf-8" It's obvious that PDMA support 64-bit access of 64-bit registers, and in previous commit, we confirm that PDMA support 32-bit access of both 32/64-bit registers. Thus, we configure 32/64-bit memory access of PDMA registers as valid in general. Signed-off-by: Jim Shu Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Bin Meng --- hw/dma/sifive_pdma.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c index b8b198ab4e..731fcdcf89 100644 --- a/hw/dma/sifive_pdma.c +++ b/hw/dma/sifive_pdma.c @@ -441,6 +441,10 @@ static const MemoryRegionOps sifive_pdma_ops =3D { .impl =3D { .min_access_size =3D 4, .max_access_size =3D 8, + }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 8, } }; =20 --=20 2.25.1