From nobody Sun May 19 11:06:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1640290884629958.9522006494365; Thu, 23 Dec 2021 12:21:24 -0800 (PST) Received: from localhost ([::1]:47944 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n0UaZ-00068S-AQ for importer@patchew.org; Thu, 23 Dec 2021 15:21:23 -0500 Received: from eggs.gnu.org ([209.51.188.92]:55286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n0UXn-0003Kz-V6; Thu, 23 Dec 2021 15:18:31 -0500 Received: from [2607:f8b0:4864:20::929] (port=46856 helo=mail-ua1-x929.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n0UXm-0004Lh-Bk; Thu, 23 Dec 2021 15:18:31 -0500 Received: by mail-ua1-x929.google.com with SMTP id 30so11763143uag.13; Thu, 23 Dec 2021 12:18:25 -0800 (PST) Received: from rekt.ibmuc.com ([2804:431:c7c6:7ce4:b718:2cc0:32df:97ee]) by smtp.gmail.com with ESMTPSA id f20sm1185114vsl.31.2021.12.23.12.18.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Dec 2021 12:18:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hLWaNvqAqmmsAsLdcy1M52Mog4MXVSPT/Aa3cq/UbCI=; b=l4N0WO4VPd3pRY7eytiutBn5HQ916Dud2sXBUMhkKjU5OkkGDq8xcBzsdKQn1f6cNH sY4bI/0SM2xIufF0YxumJB++mvFgQF4xtsEO/NTNWs8TqCpcCDb+PzfvtZ+v0qppU2GG KcOmGuBIYyz8h5eSqW6NITlOctRHz8VcmxbsYyxSMMW/p92zB1iwmr0An+yZEV+w3l+R Crg2npJzRy74bjPNd7OeC3LDCmbjbB0BihihBwmsPW5JVPCB9PxvFnEO+XGV8NwB7t5g MbyILJpn3JMZQpwkqzzbXwaxC8T9FJQ82iLwLin+2mnPeGFDsUmjNLGK7GALgUJGYW5x SvsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hLWaNvqAqmmsAsLdcy1M52Mog4MXVSPT/Aa3cq/UbCI=; b=LTJffKIEQ2dw8CtUUK4nTKCCddHDKW1QoD1HhKGF/VtxZyCUvVUbmKBwp9mHH2APnB ozIzzxXZYQTbO5XvczUqLvpWinZByBa51ACilSWiowF00UL35AosQ5GHjCWb+VadLCC0 CvynIk8B/VxparEzc8NQPB5bPux8Si9iqaPoJfxvf4slRidE5UtkNvhnj6XMjGJM2JWl qIK9pWhOYQpVYwD55Bmh+z4FeFfYG91G94MjnSBzXOr5RUL4dep4X7fLd/vApMZUMvDn Y8CI9FJt/p0ETL9aQfmtyNixlISpD7vfHUKfaKv4BBK/Yd3+4Vq+n3a/e1z6tK+rlomQ 3Yiw== X-Gm-Message-State: AOAM533Ohc+M5rM5MchWbYekZZop6eNGRoHjRtz2dTihEZBpb3aKw5aF 3UIdw8lNVmIzBoZr2l0kFp2ABVwWNE0= X-Google-Smtp-Source: ABdhPJx1hwp+suwPjjKQYYVnSbydiQHoU6DZdcYJ0OHZkmxh2vHMuzdIfUsUfh82KjtYvrwdE0xHoQ== X-Received: by 2002:a05:6102:50a0:: with SMTP id bl32mr253753vsb.72.1640290705166; Thu, 23 Dec 2021 12:18:25 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v2 1/5] target/ppc: introduce power8-pmu-insn-cnt.c.inc Date: Thu, 23 Dec 2021 17:18:08 -0300 Message-Id: <20211223201812.846495-2-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211223201812.846495-1-danielhb413@gmail.com> References: <20211223201812.846495-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::929 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::929; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x929.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1640290887178100001 Content-Type: text/plain; charset="utf-8" We're going to add a significant amount of TCG ops code for instruction counting, eventually getting rid of the 'helper_insn_inc' helper entirely. Create a new file to avoid putting even more stuff on the already crowded target/ppc/translate.c. Signed-off-by: Daniel Henrique Barboza --- target/ppc/power8-pmu-insn-cnt.c.inc | 54 ++++++++++++++++++++++++++++ target/ppc/translate.c | 44 ++--------------------- 2 files changed, 56 insertions(+), 42 deletions(-) create mode 100644 target/ppc/power8-pmu-insn-cnt.c.inc diff --git a/target/ppc/power8-pmu-insn-cnt.c.inc b/target/ppc/power8-pmu-i= nsn-cnt.c.inc new file mode 100644 index 0000000000..6cdf2d2d88 --- /dev/null +++ b/target/ppc/power8-pmu-insn-cnt.c.inc @@ -0,0 +1,54 @@ +/* + * IBM Power8+ PMU TCG instruction count functions + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#if defined(TARGET_PPC64) +static void pmu_count_insns(DisasContext *ctx) +{ + /* + * Do not bother calling the helper if the PMU isn't counting + * instructions. + */ + if (!ctx->pmu_insn_cnt) { + return; + } + + #if !defined(CONFIG_USER_ONLY) + /* + * The PMU insns_inc() helper stops the internal PMU timer if a + * counter overflows happens. In that case, if the guest is + * running with icount and we do not handle it beforehand, + * the helper can trigger a 'bad icount read'. + */ + gen_icount_io_start(ctx); + + gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); +#else + /* + * User mode can read (but not write) PMC5 and start/stop + * the PMU via MMCR0_FC. In this case just increment + * PMC5 with base.num_insns. + */ + TCGv t0 =3D tcg_temp_new(); + + gen_load_spr(t0, SPR_POWER_PMC5); + tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); + gen_store_spr(SPR_POWER_PMC5, t0); + + tcg_temp_free(t0); +#endif /* #if !defined(CONFIG_USER_ONLY) */ +} +#else +static void pmu_count_insns(DisasContext *ctx) +{ + return; +} +#endif /* #if defined(TARGET_PPC64) */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 114456148c..44773bc6cd 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4183,48 +4183,8 @@ static inline void gen_update_cfar(DisasContext *ctx= , target_ulong nip) #endif } =20 -#if defined(TARGET_PPC64) -static void pmu_count_insns(DisasContext *ctx) -{ - /* - * Do not bother calling the helper if the PMU isn't counting - * instructions. - */ - if (!ctx->pmu_insn_cnt) { - return; - } - - #if !defined(CONFIG_USER_ONLY) - /* - * The PMU insns_inc() helper stops the internal PMU timer if a - * counter overflows happens. In that case, if the guest is - * running with icount and we do not handle it beforehand, - * the helper can trigger a 'bad icount read'. - */ - gen_icount_io_start(ctx); - - gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); -#else - /* - * User mode can read (but not write) PMC5 and start/stop - * the PMU via MMCR0_FC. In this case just increment - * PMC5 with base.num_insns. - */ - TCGv t0 =3D tcg_temp_new(); - - gen_load_spr(t0, SPR_POWER_PMC5); - tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); - gen_store_spr(SPR_POWER_PMC5, t0); - - tcg_temp_free(t0); -#endif /* #if !defined(CONFIG_USER_ONLY) */ -} -#else -static void pmu_count_insns(DisasContext *ctx) -{ - return; -} -#endif /* #if defined(TARGET_PPC64) */ +/* For pmu_count_insns */ +#include "target/ppc/power8-pmu-insn-cnt.c.inc" =20 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) { --=20 2.33.1 From nobody Sun May 19 11:06:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1640291005181376.33675150470526; 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Thu, 23 Dec 2021 12:18:27 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v2 2/5] target/ppc/power8-pmu-insn-cnt: introduce inc_spr_if_cond() Date: Thu, 23 Dec 2021 17:18:09 -0300 Message-Id: <20211223201812.846495-3-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211223201812.846495-1-danielhb413@gmail.com> References: <20211223201812.846495-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::935 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::935; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x935.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1640291007037100001 Content-Type: text/plain; charset="utf-8" The code that increments a PMC is repetitive: check if a given register has a bit/mask set or cleared and increment the counter. inc_spr_if_cond() will help deal with this repetition. This patch also gives a sample of how the function works by incrementing PMC5, which is supposed to be incremented only if MMCR0_FC56 is not set. We've also removing the call from the helper since that would cause PMC5 to be counted twice. Signed-off-by: Daniel Henrique Barboza --- target/ppc/power8-pmu-insn-cnt.c.inc | 43 ++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 9 deletions(-) diff --git a/target/ppc/power8-pmu-insn-cnt.c.inc b/target/ppc/power8-pmu-i= nsn-cnt.c.inc index 6cdf2d2d88..3cfb801c69 100644 --- a/target/ppc/power8-pmu-insn-cnt.c.inc +++ b/target/ppc/power8-pmu-insn-cnt.c.inc @@ -10,6 +10,38 @@ * See the COPYING file in the top-level directory. */ =20 +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +/* + * This function increments a SPR 'spr' by 'inc_val' if a given + * register 'reg' has a bitmask 'mask' set (cond =3D TCG_COND_EQ) or + * not set (TCG_COND_NE). + */ +static void inc_spr_if_cond(int reg, uint64_t mask, TCGCond cond, + int spr, int inc_val) +{ + TCGCond exit_cond =3D tcg_invert_cond(cond); + TCGLabel *l_exit; + TCGv t0, t1; + + l_exit =3D gen_new_label(); + + t0 =3D tcg_temp_new(); + gen_load_spr(t0, reg); + tcg_gen_andi_tl(t0, t0, mask); + tcg_gen_brcondi_tl(exit_cond, t0, mask, l_exit); + + t1 =3D tcg_temp_new(); + gen_load_spr(t1, spr); + tcg_gen_addi_tl(t1, t1, inc_val); + gen_store_spr(spr, t1); + + gen_set_label(l_exit); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} +#endif /* #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ + #if defined(TARGET_PPC64) static void pmu_count_insns(DisasContext *ctx) { @@ -22,15 +54,8 @@ static void pmu_count_insns(DisasContext *ctx) } =20 #if !defined(CONFIG_USER_ONLY) - /* - * The PMU insns_inc() helper stops the internal PMU timer if a - * counter overflows happens. In that case, if the guest is - * running with icount and we do not handle it beforehand, - * the helper can trigger a 'bad icount read'. - */ - gen_icount_io_start(ctx); - - gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); + inc_spr_if_cond(SPR_POWER_MMCR0, MMCR0_FC56, TCG_COND_NE, + SPR_POWER_PMC5, ctx->base.num_insns); #else /* * User mode can read (but not write) PMC5 and start/stop --=20 2.33.1 From nobody Sun May 19 11:06:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1640290889355849.2638603089159; Thu, 23 Dec 2021 12:21:29 -0800 (PST) Received: from localhost ([::1]:48192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n0Uae-0006I7-Bu for importer@patchew.org; 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Thu, 23 Dec 2021 12:18:29 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v2 3/5] target/ppc/power8-pmu-insn-cnt: add PMCs1-4 insn count Date: Thu, 23 Dec 2021 17:18:10 -0300 Message-Id: <20211223201812.846495-4-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211223201812.846495-1-danielhb413@gmail.com> References: <20211223201812.846495-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::92f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::92f; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x92f.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1640290890063100001 Content-Type: text/plain; charset="utf-8" Use inc_spr_if_cond() to count instructions of all other PMCs that are capable of counting instructions (all PMCs but PMC6). Signed-off-by: Daniel Henrique Barboza --- target/ppc/power8-pmu-insn-cnt.c.inc | 62 ++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/target/ppc/power8-pmu-insn-cnt.c.inc b/target/ppc/power8-pmu-i= nsn-cnt.c.inc index 3cfb801c69..a5a0d42e71 100644 --- a/target/ppc/power8-pmu-insn-cnt.c.inc +++ b/target/ppc/power8-pmu-insn-cnt.c.inc @@ -11,6 +11,13 @@ */ =20 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +#define MMCR1_PMC1_INS_CNT 0x02000000 +#define MMCR1_PMC1_INS_CNT2 0xFE000000 +#define MMCR1_PMC2_INS_CNT 0x00020000 +#define MMCR1_PMC3_INS_CNT 0x00000200 +#define MMCR1_PMC4_INS_CNT 0x00000002 +#define MMCR1_PMC4_INS_LATCH_CNT 0x000000FA + /* * This function increments a SPR 'spr' by 'inc_val' if a given * register 'reg' has a bitmask 'mask' set (cond =3D TCG_COND_EQ) or @@ -54,8 +61,63 @@ static void pmu_count_insns(DisasContext *ctx) } =20 #if !defined(CONFIG_USER_ONLY) + TCGv t_mmcr0, t_mmcr1, t_ctrl; + TCGLabel *l_skip_pmc14; + inc_spr_if_cond(SPR_POWER_MMCR0, MMCR0_FC56, TCG_COND_NE, SPR_POWER_PMC5, ctx->base.num_insns); + + /* + * Skip PMC1-4 increment if: + * - MMCR0_FC14 is set OR + * - MMCR1 is cleared + */ + l_skip_pmc14 =3D gen_new_label(); + + t_mmcr0 =3D tcg_temp_new(); + gen_load_spr(t_mmcr0, SPR_POWER_MMCR0); + tcg_gen_andi_tl(t_mmcr0, t_mmcr0, MMCR0_FC14); + tcg_gen_brcondi_tl(TCG_COND_EQ, t_mmcr0, MMCR0_FC14, l_skip_pmc14); + + t_mmcr1 =3D tcg_temp_new(); + gen_load_spr(t_mmcr1, SPR_POWER_MMCR1); + tcg_gen_brcondi_tl(TCG_COND_EQ, t_mmcr1, 0x0, l_skip_pmc14); + + /* PMC1 is incremented if PMC1SEL =3D 0x02 or 0xFE */ + inc_spr_if_cond(SPR_POWER_MMCR1, MMCR1_PMC1_INS_CNT, TCG_COND_EQ, + SPR_POWER_PMC1, ctx->base.num_insns); + inc_spr_if_cond(SPR_POWER_MMCR1, MMCR1_PMC1_INS_CNT2, TCG_COND_EQ, + SPR_POWER_PMC1, ctx->base.num_insns); + + /* PMC2 is incremented if PMC2SEL =3D 0x02 */ + inc_spr_if_cond(SPR_POWER_MMCR1, MMCR1_PMC2_INS_CNT, TCG_COND_EQ, + SPR_POWER_PMC2, ctx->base.num_insns); + + /* PMC3 is incremented if PMC3SEL =3D 0x02 */ + inc_spr_if_cond(SPR_POWER_MMCR1, MMCR1_PMC3_INS_CNT, TCG_COND_EQ, + SPR_POWER_PMC3, ctx->base.num_insns); + + /* + * PMC4 is incremented if PMC4SEL =3D 0x02 or 0xFA. 0xFA depends on the + * run latch (SPR_CTRL & CTRL_RUN). Check for the run latch before + * checking for PMC4SEL =3D 0xFA. + */ + inc_spr_if_cond(SPR_POWER_MMCR1, MMCR1_PMC4_INS_CNT, TCG_COND_EQ, + SPR_POWER_PMC4, ctx->base.num_insns); + + t_ctrl =3D tcg_temp_new(); + gen_load_spr(t_ctrl, SPR_CTRL); + tcg_gen_andi_tl(t_ctrl, t_ctrl, CTRL_RUN); + tcg_gen_brcondi_tl(TCG_COND_NE, t_ctrl, CTRL_RUN, l_skip_pmc14); + + inc_spr_if_cond(SPR_POWER_MMCR1, MMCR1_PMC4_INS_LATCH_CNT, TCG_COND_EQ, + SPR_POWER_PMC4, ctx->base.num_insns); + + gen_set_label(l_skip_pmc14); + + tcg_temp_free(t_mmcr0); + tcg_temp_free(t_mmcr1); + tcg_temp_free(t_ctrl); #else /* * User mode can read (but not write) PMC5 and start/stop --=20 2.33.1 From nobody Sun May 19 11:06:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1640291027029647.0465009270953; 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Thu, 23 Dec 2021 12:18:31 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v2 4/5] target/ppc/power8-pmu-insn-cnt: add pmu_check_overflow() Date: Thu, 23 Dec 2021 17:18:11 -0300 Message-Id: <20211223201812.846495-5-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211223201812.846495-1-danielhb413@gmail.com> References: <20211223201812.846495-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::930 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::930; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x930.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1640291028304100001 Content-Type: text/plain; charset="utf-8" pmu_check_overflow() will verify for overflow in the PMC1-5 counters, firing a performance monitor alert if an overflow happened with the proper MMCR0 bits set. The alert is fired by using helper_pmu_overflow(). Signed-off-by: Daniel Henrique Barboza --- target/ppc/helper.h | 1 + target/ppc/power8-pmu-insn-cnt.c.inc | 76 ++++++++++++++++++++++++++++ target/ppc/power8-pmu.c | 8 +++ 3 files changed, 85 insertions(+) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index fb6cac38b4..4d8193caab 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -26,6 +26,7 @@ DEF_HELPER_2(store_mmcr1, void, env, tl) DEF_HELPER_3(store_pmc, void, env, i32, i64) DEF_HELPER_2(read_pmc, tl, env, i32) DEF_HELPER_2(insns_inc, void, env, i32) +DEF_HELPER_1(pmu_overflow, void, env) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/power8-pmu-insn-cnt.c.inc b/target/ppc/power8-pmu-i= nsn-cnt.c.inc index a5a0d42e71..6e0e4e1270 100644 --- a/target/ppc/power8-pmu-insn-cnt.c.inc +++ b/target/ppc/power8-pmu-insn-cnt.c.inc @@ -18,6 +18,8 @@ #define MMCR1_PMC4_INS_CNT 0x00000002 #define MMCR1_PMC4_INS_LATCH_CNT 0x000000FA =20 +#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL + /* * This function increments a SPR 'spr' by 'inc_val' if a given * register 'reg' has a bitmask 'mask' set (cond =3D TCG_COND_EQ) or @@ -47,6 +49,78 @@ static void inc_spr_if_cond(int reg, uint64_t mask, TCGC= ond cond, tcg_temp_free(t0); tcg_temp_free(t1); } + +/* + * Check for overflow of PMC1-PMC5 counters and call the overflow + * helper in case any counter has overflown. + */ +static void pmu_check_overflow(DisasContext *ctx) +{ + TCGv t0, t1, t_pmc1, t_pmc; + TCGLabel *l_pmc_overflow; + TCGLabel *l_skip_pmc1_overflow; + TCGLabel *l_skip_overflow; + int i; + + /* + * Check if we have overflow bits set and fire an overflow + * event if necessary. Skip directly to 'l_pmc_overflow' + * right after finding the first overflow. + */ + l_pmc_overflow =3D gen_new_label(); + l_skip_pmc1_overflow =3D gen_new_label(); + + t0 =3D tcg_temp_new(); + gen_load_spr(t0, SPR_POWER_MMCR0); + tcg_gen_andi_tl(t0, t0, MMCR0_PMC1CE); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MMCR0_PMC1CE, l_skip_pmc1_overflow= ); + + t_pmc1 =3D tcg_temp_new(); + gen_load_spr(t_pmc1, SPR_POWER_PMC1); + tcg_gen_brcondi_tl(TCG_COND_GE, t_pmc1, PMC_COUNTER_NEGATIVE_VAL, + l_pmc_overflow); + + gen_set_label(l_skip_pmc1_overflow); + + l_skip_overflow =3D gen_new_label(); + + /* + * At this point we're sure PMC1 didn't overflow. If MMCR0_PMCjCE + * isn't set we can skip everything since PMC2-5 overflow is + * disabled. + */ + t1 =3D tcg_temp_new(); + gen_load_spr(t1, SPR_POWER_MMCR0); + tcg_gen_andi_tl(t1, t1, MMCR0_PMCjCE); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, MMCR0_PMCjCE, l_skip_overflow); + + for (i =3D SPR_POWER_PMC2; i < SPR_POWER_PMC6; i++) { + t_pmc =3D tcg_temp_new(); + gen_load_spr(t_pmc, i); + tcg_gen_brcondi_tl(TCG_COND_GE, t_pmc, PMC_COUNTER_NEGATIVE_VAL, + l_pmc_overflow); + tcg_temp_free(t_pmc); + } + + tcg_gen_br(l_skip_overflow); + + gen_set_label(l_pmc_overflow); + + /* + * The PMU overflow helper manipulates the internal PMU timer. + * In that case, if the guest is running with icount and we do not + * handle it beforehand, the helper can trigger a 'bad icount + * read'. + */ + gen_icount_io_start(ctx); + gen_helper_pmu_overflow(cpu_env); + + gen_set_label(l_skip_overflow); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t_pmc1); +} #endif /* #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ =20 #if defined(TARGET_PPC64) @@ -115,6 +189,8 @@ static void pmu_count_insns(DisasContext *ctx) =20 gen_set_label(l_skip_pmc14); =20 + pmu_check_overflow(ctx); + tcg_temp_free(t_mmcr0); tcg_temp_free(t_mmcr1); tcg_temp_free(t_ctrl); diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 08d1902cd5..6696c9b3ae 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -323,6 +323,14 @@ void helper_insns_inc(CPUPPCState *env, uint32_t num_i= nsns) } } =20 +/* Helper to fire a PMC interrupt from TCG code */ +void helper_pmu_overflow(CPUPPCState *env) +{ + PowerPCCPU *cpu =3D env_archcpu(env); + + fire_PMC_interrupt(cpu); +} + static void cpu_ppc_pmu_timer_cb(void *opaque) { PowerPCCPU *cpu =3D opaque; --=20 2.33.1 From nobody Sun May 19 11:06:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1640291161275353.34643782723276; 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Thu, 23 Dec 2021 12:18:33 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v2 5/5] target/ppc/power8-pmu.c: remove helper_insns_inc() Date: Thu, 23 Dec 2021 17:18:12 -0300 Message-Id: <20211223201812.846495-6-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211223201812.846495-1-danielhb413@gmail.com> References: <20211223201812.846495-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::92a (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::92a; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x92a.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1640291163475100001 Content-Type: text/plain; charset="utf-8" After moving all the instruction counting to TCG Ops code this helper is not needed anymore. Signed-off-by: Daniel Henrique Barboza --- target/ppc/helper.h | 1 - target/ppc/power8-pmu-insn-cnt.c.inc | 4 -- target/ppc/power8-pmu.c | 60 ---------------------------- 3 files changed, 65 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 4d8193caab..de80e82ebe 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -25,7 +25,6 @@ DEF_HELPER_2(store_mmcr0, void, env, tl) DEF_HELPER_2(store_mmcr1, void, env, tl) DEF_HELPER_3(store_pmc, void, env, i32, i64) DEF_HELPER_2(read_pmc, tl, env, i32) -DEF_HELPER_2(insns_inc, void, env, i32) DEF_HELPER_1(pmu_overflow, void, env) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) diff --git a/target/ppc/power8-pmu-insn-cnt.c.inc b/target/ppc/power8-pmu-i= nsn-cnt.c.inc index 6e0e4e1270..adb796c1c1 100644 --- a/target/ppc/power8-pmu-insn-cnt.c.inc +++ b/target/ppc/power8-pmu-insn-cnt.c.inc @@ -126,10 +126,6 @@ static void pmu_check_overflow(DisasContext *ctx) #if defined(TARGET_PPC64) static void pmu_count_insns(DisasContext *ctx) { - /* - * Do not bother calling the helper if the PMU isn't counting - * instructions. - */ if (!ctx->pmu_insn_cnt) { return; } diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 6696c9b3ae..bfc052b49e 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -135,52 +135,6 @@ bool pmu_insn_cnt_enabled(CPUPPCState *env) return false; } =20 -static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns) -{ - bool overflow_triggered =3D false; - int sprn; - - /* PMC6 never counts instructions */ - for (sprn =3D SPR_POWER_PMC1; sprn <=3D SPR_POWER_PMC5; sprn++) { - PMUEventType evt_type =3D pmc_get_event(env, sprn); - bool insn_event =3D evt_type =3D=3D PMU_EVENT_INSTRUCTIONS || - evt_type =3D=3D PMU_EVENT_INSN_RUN_LATCH; - - if (pmc_is_inactive(env, sprn) || !insn_event) { - continue; - } - - if (evt_type =3D=3D PMU_EVENT_INSTRUCTIONS) { - env->spr[sprn] +=3D num_insns; - } - - if (evt_type =3D=3D PMU_EVENT_INSN_RUN_LATCH && - env->spr[SPR_CTRL] & CTRL_RUN) { - env->spr[sprn] +=3D num_insns; - } - - if (env->spr[sprn] >=3D PMC_COUNTER_NEGATIVE_VAL && - pmc_has_overflow_enabled(env, sprn)) { - - overflow_triggered =3D true; - - /* - * The real PMU will always trigger a counter overflow with - * PMC_COUNTER_NEGATIVE_VAL. We don't have an easy way to - * do that since we're counting block of instructions at - * the end of each translation block, and we're probably - * passing this value at this point. - * - * Let's write PMC_COUNTER_NEGATIVE_VAL to the overflowed - * counter to simulate what the real hardware would do. - */ - env->spr[sprn] =3D PMC_COUNTER_NEGATIVE_VAL; - } - } - - return overflow_triggered; -} - static void pmu_update_cycles(CPUPPCState *env) { uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -309,20 +263,6 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu) return; } =20 -/* This helper assumes that the PMC is running. */ -void helper_insns_inc(CPUPPCState *env, uint32_t num_insns) -{ - bool overflow_triggered; - PowerPCCPU *cpu; - - overflow_triggered =3D pmu_increment_insns(env, num_insns); - - if (overflow_triggered) { - cpu =3D env_archcpu(env); - fire_PMC_interrupt(cpu); - } -} - /* Helper to fire a PMC interrupt from TCG code */ void helper_pmu_overflow(CPUPPCState *env) { --=20 2.33.1