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[193.152.124.33]) by smtp.gmail.com with ESMTPSA id x8sm7654513wmj.44.2021.12.23.04.00.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Dec 2021 04:00:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1640260850; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DBPP1EiSKr7NPlc65W5DPicfsUwIYcUriP04xIPwWVo=; b=MCh29Bj6cjjau2vtFk7n3he4WvZYVUpopjYyVwl16FDCcg6srlFlOGvBJEBwXPjJyc73C8 uXwASYLia8xNPZVbVht2nO9T2Qd6y6T0hOSsYFc04NjcxBlRQ9xyZs/EwRFwiI2naxIQaF x8IIdX/Amany+jUp22vxj9TpEiTYRSI= X-MC-Unique: IeAKELJ6PiKuaD2FmCtPSw-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DBPP1EiSKr7NPlc65W5DPicfsUwIYcUriP04xIPwWVo=; b=mAXvCS2GuBSTrsezu8e3D1uHzq8XDRpptWZAjEAZmk5gUzH7pgSYhC4dHemhPg6vqE l/BDemoyDnB7d3ilRj/WlymaFqXtRtiyhY7HedRgB7xGF3cIqklvUJRNiYGsIdjyl5vB uZlVsa2UBsIXlGDDO8EU1CD1ns2ERZ/1W0YN2VBZPs1I+rzGI5096bMrlOLtEmp0aABj Xedn3+oYgtoU/VDWq4mIajIcZdcAH/2F1pWYKT6L9JChOKXyaekTE4IzIZHrE7cWlN1a g7rwYvTEisEKix54jzOzTQZdDllridpIIYw+fsnwAm9i0XimQJur8xCyXW2sEutkuIzm n3dw== X-Gm-Message-State: AOAM532lNQNLAe/Hm74y5K32DmiOC9X90weX/5XNg/vZYWpEkUQ0u2lG 3HxPOdxZ9kxytWNVBqxQACPH7uH7mLnCWm3MQw7ciRjRAteTWpW4+YF7YKY0nmF74hIyXApMdWa LUx0+ZDAFswcwxw== X-Received: by 2002:adf:d841:: with SMTP id k1mr1632763wrl.396.1640260848370; Thu, 23 Dec 2021 04:00:48 -0800 (PST) X-Google-Smtp-Source: ABdhPJx3x4bEjyITPOZYC9xFTlLr/8oRH55HegaMaa82awicTJ93Fzb1rX+4CUPeSc+/f+NROOKS2g== X-Received: by 2002:adf:d841:: with SMTP id k1mr1632747wrl.396.1640260848169; Thu, 23 Dec 2021 04:00:48 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Joel Stanley , Richard Henderson , qemu-block@nongnu.org, Jason Wang , Keith Busch , "Michael S. Tsirkin" , Fam Zheng , Alistair Francis , David Hildenbrand , Eduardo Habkost , Havard Skinnemoen , Sven Schnelle , Tyrone Ting , Gerd Hoffmann , Peter Maydell , Beniamino Galvani , Daniel Henrique Barboza , Dmitry Fleytman , John Snow , Bin Meng , Greg Kurz , Eric Auger , Mark Cave-Ayland , "Edgar E. Iglesias" , Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Andrew Baumann , Hannes Reinecke , Paolo Bonzini , Peter Xu , qemu-arm@nongnu.org, Klaus Jensen , Stefan Weil , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Jan Kiszka , David Gibson Subject: [PATCH v2 21/23] pci: Let ld*_pci_dma() take MemTxAttrs argument Date: Thu, 23 Dec 2021 12:55:52 +0100 Message-Id: <20211223115554.3155328-22-philmd@redhat.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211223115554.3155328-1-philmd@redhat.com> References: <20211223115554.3155328-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1640260854654100001 Let devices specify transaction attributes when calling ld*_pci_dma(). Keep the default MEMTXATTRS_UNSPECIFIED in the few callers. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/pci/pci.h | 6 +++--- hw/audio/intel-hda.c | 2 +- hw/net/eepro100.c | 19 +++++++++++++------ hw/net/tulip.c | 18 ++++++++++-------- hw/scsi/megasas.c | 16 ++++++++++------ hw/scsi/mptsas.c | 10 ++++++---- hw/scsi/vmw_pvscsi.c | 3 ++- hw/usb/hcd-xhci.c | 1 + 8 files changed, 46 insertions(+), 29 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 9f51ef2c3c2..7a46c1fa226 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -852,11 +852,11 @@ static inline MemTxResult pci_dma_write(PCIDevice *de= v, dma_addr_t addr, =20 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ - dma_addr_t addr) \ + dma_addr_t addr, \ + MemTxAttrs attrs) \ { \ uint##_bits##_t val; \ - ld##_l##_dma(pci_get_address_space(dev), addr, &val, \ - MEMTXATTRS_UNSPECIFIED); \ + ld##_l##_dma(pci_get_address_space(dev), addr, &val, attrs); \ return val; \ } \ static inline void st##_s##_pci_dma(PCIDevice *dev, \ diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c index 3309ae0ea18..e34b7ab0e92 100644 --- a/hw/audio/intel-hda.c +++ b/hw/audio/intel-hda.c @@ -335,7 +335,7 @@ static void intel_hda_corb_run(IntelHDAState *d) =20 rp =3D (d->corb_rp + 1) & 0xff; addr =3D intel_hda_addr(d->corb_lbase, d->corb_ubase); - verb =3D ldl_le_pci_dma(&d->pci, addr + 4*rp); + verb =3D ldl_le_pci_dma(&d->pci, addr + 4 * rp, MEMTXATTRS_UNSPECI= FIED); d->corb_rp =3D rp; =20 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb); diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c index 83c4431b1ad..eb82e9cb118 100644 --- a/hw/net/eepro100.c +++ b/hw/net/eepro100.c @@ -737,6 +737,7 @@ static void read_cb(EEPRO100State *s) =20 static void tx_command(EEPRO100State *s) { + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; uint32_t tbd_array =3D s->tx.tbd_array_addr; uint16_t tcb_bytes =3D s->tx.tcb_bytes & 0x3fff; /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes.= */ @@ -772,11 +773,14 @@ static void tx_command(EEPRO100State *s) /* Extended Flexible TCB. */ for (; tbd_count < 2; tbd_count++) { uint32_t tx_buffer_address =3D ldl_le_pci_dma(&s->dev, - tbd_address); + tbd_address, + attrs); uint16_t tx_buffer_size =3D lduw_le_pci_dma(&s->dev, - tbd_address + 4); + tbd_address + 4, + attrs); uint16_t tx_buffer_el =3D lduw_le_pci_dma(&s->dev, - tbd_address + 6); + tbd_address + 6, + attrs); tbd_address +=3D 8; TRACE(RXTX, logout ("TBD (extended flexible mode): buffer address 0x%08x,= size 0x%04x\n", @@ -792,9 +796,12 @@ static void tx_command(EEPRO100State *s) } tbd_address =3D tbd_array; for (; tbd_count < s->tx.tbd_count; tbd_count++) { - uint32_t tx_buffer_address =3D ldl_le_pci_dma(&s->dev, tbd_add= ress); - uint16_t tx_buffer_size =3D lduw_le_pci_dma(&s->dev, tbd_addre= ss + 4); - uint16_t tx_buffer_el =3D lduw_le_pci_dma(&s->dev, tbd_address= + 6); + uint32_t tx_buffer_address =3D ldl_le_pci_dma(&s->dev, tbd_add= ress, + attrs); + uint16_t tx_buffer_size =3D lduw_le_pci_dma(&s->dev, tbd_addre= ss + 4, + attrs); + uint16_t tx_buffer_el =3D lduw_le_pci_dma(&s->dev, tbd_address= + 6, + attrs); tbd_address +=3D 8; TRACE(RXTX, logout ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\= n", diff --git a/hw/net/tulip.c b/hw/net/tulip.c index 1f2c79dd58b..c76e4868f73 100644 --- a/hw/net/tulip.c +++ b/hw/net/tulip.c @@ -70,16 +70,18 @@ static const VMStateDescription vmstate_pci_tulip =3D { static void tulip_desc_read(TULIPState *s, hwaddr p, struct tulip_descriptor *desc) { + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; + if (s->csr[0] & CSR0_DBO) { - desc->status =3D ldl_be_pci_dma(&s->dev, p); - desc->control =3D ldl_be_pci_dma(&s->dev, p + 4); - desc->buf_addr1 =3D ldl_be_pci_dma(&s->dev, p + 8); - desc->buf_addr2 =3D ldl_be_pci_dma(&s->dev, p + 12); + desc->status =3D ldl_be_pci_dma(&s->dev, p, attrs); + desc->control =3D ldl_be_pci_dma(&s->dev, p + 4, attrs); + desc->buf_addr1 =3D ldl_be_pci_dma(&s->dev, p + 8, attrs); + desc->buf_addr2 =3D ldl_be_pci_dma(&s->dev, p + 12, attrs); } else { - desc->status =3D ldl_le_pci_dma(&s->dev, p); - desc->control =3D ldl_le_pci_dma(&s->dev, p + 4); - desc->buf_addr1 =3D ldl_le_pci_dma(&s->dev, p + 8); - desc->buf_addr2 =3D ldl_le_pci_dma(&s->dev, p + 12); + desc->status =3D ldl_le_pci_dma(&s->dev, p, attrs); + desc->control =3D ldl_le_pci_dma(&s->dev, p + 4, attrs); + desc->buf_addr1 =3D ldl_le_pci_dma(&s->dev, p + 8, attrs); + desc->buf_addr2 =3D ldl_le_pci_dma(&s->dev, p + 12, attrs); } } =20 diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index 65451d34e64..f93c34c4201 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -202,7 +202,9 @@ static uint64_t megasas_frame_get_context(MegasasState = *s, unsigned long frame) { PCIDevice *pci =3D &s->parent_obj; - return ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, c= ontext)); + return ldq_le_pci_dma(pci, + frame + offsetof(struct mfi_frame_header, contex= t), + MEMTXATTRS_UNSPECIFIED); } =20 static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd) @@ -534,7 +536,8 @@ static MegasasCmd *megasas_enqueue_frame(MegasasState *= s, s->busy++; =20 if (s->consumer_pa) { - s->reply_queue_tail =3D ldl_le_pci_dma(pcid, s->consumer_pa); + s->reply_queue_tail =3D ldl_le_pci_dma(pcid, s->consumer_pa, + MEMTXATTRS_UNSPECIFIED); } trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context, s->reply_queue_head, s->reply_queue_tail, s->= busy); @@ -565,14 +568,14 @@ static void megasas_complete_frame(MegasasState *s, u= int64_t context) stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context, attrs); } - s->reply_queue_tail =3D ldl_le_pci_dma(pci_dev, s->consumer_pa); + s->reply_queue_tail =3D ldl_le_pci_dma(pci_dev, s->consumer_pa, at= trs); trace_megasas_qf_complete(context, s->reply_queue_head, s->reply_queue_tail, s->busy); } =20 if (megasas_intr_enabled(s)) { /* Update reply queue pointer */ - s->reply_queue_tail =3D ldl_le_pci_dma(pci_dev, s->consumer_pa); + s->reply_queue_tail =3D ldl_le_pci_dma(pci_dev, s->consumer_pa, at= trs); tail =3D s->reply_queue_head; s->reply_queue_head =3D megasas_next_index(s, tail, s->fw_cmds); trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail, @@ -637,6 +640,7 @@ static void megasas_abort_command(MegasasCmd *cmd) =20 static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd) { + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; PCIDevice *pcid =3D PCI_DEVICE(s); uint32_t pa_hi, pa_lo; hwaddr iq_pa, initq_size =3D sizeof(struct mfi_init_qinfo); @@ -675,9 +679,9 @@ static int megasas_init_firmware(MegasasState *s, Megas= asCmd *cmd) pa_lo =3D le32_to_cpu(initq->pi_addr_lo); pa_hi =3D le32_to_cpu(initq->pi_addr_hi); s->producer_pa =3D ((uint64_t) pa_hi << 32) | pa_lo; - s->reply_queue_head =3D ldl_le_pci_dma(pcid, s->producer_pa); + s->reply_queue_head =3D ldl_le_pci_dma(pcid, s->producer_pa, attrs); s->reply_queue_head %=3D MEGASAS_MAX_FRAMES; - s->reply_queue_tail =3D ldl_le_pci_dma(pcid, s->consumer_pa); + s->reply_queue_tail =3D ldl_le_pci_dma(pcid, s->consumer_pa, attrs); s->reply_queue_tail %=3D MEGASAS_MAX_FRAMES; flags =3D le32_to_cpu(initq->flags); if (flags & MFI_QUEUE_FLAG_CONTEXT64) { diff --git a/hw/scsi/mptsas.c b/hw/scsi/mptsas.c index f6c77655443..ac9f4dfcd2a 100644 --- a/hw/scsi/mptsas.c +++ b/hw/scsi/mptsas.c @@ -172,14 +172,15 @@ static const int mpi_request_sizes[] =3D { static dma_addr_t mptsas_ld_sg_base(MPTSASState *s, uint32_t flags_and_len= gth, dma_addr_t *sgaddr) { + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; PCIDevice *pci =3D (PCIDevice *) s; dma_addr_t addr; =20 if (flags_and_length & MPI_SGE_FLAGS_64_BIT_ADDRESSING) { - addr =3D ldq_le_pci_dma(pci, *sgaddr + 4); + addr =3D ldq_le_pci_dma(pci, *sgaddr + 4, attrs); *sgaddr +=3D 12; } else { - addr =3D ldl_le_pci_dma(pci, *sgaddr + 4); + addr =3D ldl_le_pci_dma(pci, *sgaddr + 4, attrs); *sgaddr +=3D 8; } return addr; @@ -203,7 +204,7 @@ static int mptsas_build_sgl(MPTSASState *s, MPTSASReque= st *req, hwaddr addr) dma_addr_t addr, len; uint32_t flags_and_length; =20 - flags_and_length =3D ldl_le_pci_dma(pci, sgaddr); + flags_and_length =3D ldl_le_pci_dma(pci, sgaddr, MEMTXATTRS_UNSPEC= IFIED); len =3D flags_and_length & MPI_SGE_LENGTH_MASK; if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK) !=3D MPI_SGE_FLAGS_SIMPLE_ELEMENT || @@ -234,7 +235,8 @@ static int mptsas_build_sgl(MPTSASState *s, MPTSASReque= st *req, hwaddr addr) break; } =20 - flags_and_length =3D ldl_le_pci_dma(pci, next_chain_addr); + flags_and_length =3D ldl_le_pci_dma(pci, next_chain_addr, + MEMTXATTRS_UNSPECIFIED); if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK) !=3D MPI_SGE_FLAGS_CHAIN_ELEMENT) { return MPI_IOCSTATUS_INVALID_SGL; diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index 59c3e8ba048..33e16f91116 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -52,7 +52,8 @@ =20 #define RS_GET_FIELD(m, field) \ (ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \ - (m)->rs_pa + offsetof(struct PVSCSIRingsState, field))) + (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), \ + MEMTXATTRS_UNSPECIFIED)) #define RS_SET_FIELD(m, field, val) \ (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \ (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), va= l, \ diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index da5a4072107..14bdb896768 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -3440,6 +3440,7 @@ static int usb_xhci_post_load(void *opaque, int versi= on_id) } ldq_le_dma(xhci->as, dcbaap + 8 * slotid, &addr, MEMTXATTRS_UNSPEC= IFIED); slot->ctx =3D xhci_mask64(addr); + xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx)); slot->uport =3D xhci_lookup_uport(xhci, slot_ctx); if (!slot->uport) { --=20 2.33.1